Category Archives: 3D Integration

Samsung Electronics and Apple remained the top two semiconductor chip buyers in 2016, representing 18.2 percent of the total worldwide market, according to Gartner, Inc. (see Table 1). Samsung and Apple together consumed $61.7 billion of semiconductors in 2016, an increase of $0.4 billion from 2015.

“This is the sixth consecutive year that Samsung Electronics and Apple have topped the semiconductor consumption table,” said Masatsune Yamaji, principal research analyst at Gartner. “While both companies continue to exert considerable influence on technology and price trends for the wider semiconductor industry, their impact has lessened due to falling expectations for future growth.”

Although Samsung Electronics experienced intense competition from Chinese original equipment manufacturers (OEMs) in various markets including smartphones, LCD TV and LCD panel through 2016, the company increased its design total available market (TAM) and came back as the global top design TAM company in 2016 with 9.3 percent share. Apple decreased its design TAM in 2016 for the first time since Gartner started design TAM research in 2007, ending the year with 8.8 percent share of the market. The iPad did not sell well through 2016 and Apple also lost market share in the PC market.

Table 1. Preliminary Ranking of Top 10 Companies by Semiconductor Design TAM, Worldwide, 2016 (Millions of Dollars)

2015 Ranking

2016Ranking

Company

 2015

 2016

Growth (%) 2015-2016

2016 Market Share (%)

2

1

Samsung Electronics

30,343

31,667

4.4

9.3

1

2

Apple

30,885

29,989

-2.9

8.8

4

3

Dell

10,606

13,308

25.5

3.9

3

4

Lenovo

13,535

12,847

-5.1

3.8

6

5

Huawei

7,597

9,886

30.1

2.9

5

6

HP Inc.

8,673

8,481

-2.2

2.5

8

7

Hewlett Packard Enterprises

6,485

6,206

-4.3

1.8

7

8

Sony

6,892

6,071

-11.9

1.8

21

9

BBK Electronics

2,515

5,818

131.4

1.7

9

10

LG Electronics

5,502

5,172

-6.0

1.5

Others

211,736

210,238

-0.7

61.9

Total

334,768

339,684

1.5

100.0

Note: Numbers may not add to totals shown because of rounding.
Source: Gartner (February 2017)

Nine of the top 10 companies in 2015 remained in the top 10 in 2016. Cisco Systems dropped out of the top 10 in 2016 to be replaced by Chinese smartphone OEM, BBK Electronics, which grew rapidly in 2016. The top 10 now consists of four companies from the U.S., three companies from China, two from South Korea and one from Japan. This is the first time that three Chinese companies have ranked in the top 10, proving that even with the slowing macroeconomic situation in China, the importance of the Chinese electronics market is increasing.

“Even though the influence on the semiconductor industry of the top two strongest OEMs is weakening, the combined design TAM of the top 10 companies outperformed the average growth rate of the total semiconductor market in 2016,” said Mr. Yamaji. “However, semiconductor chip vendors can no longer secure their businesses by relying on a few strong customers because market share changes much faster these days. BBK Electronics grew very fast in 2016 and increased its design TAM, but this extraordinarily fast growth also underlines how volatile the businesses in China can be. Technology product marketing leaders at semiconductor chip vendors need to take the risks of their major customers into account, and always try to diversify their customer base.”

Axcelis Technologies, Inc. (Nasdaq:  ACLS), a supplier of innovative, high-productivity solutions for the semiconductor industry, announced today that it has received orders for the Purion H high current implanter from two leading manufacturers of memory devices in the Asia Pacific region. One of the orders is a follow-on order and the second order is a new customer placement. The systems will be used to support capacity ramps for next generation memory products. The systems will ship in the first quarter.

“The Purion H continues to gain ground as the high current tool of choice due to its ability to provide exceptional doping precision for enhanced device performance and yields,” said John Aldeborgh, executive vice president, customer operations. “We’re excited about the potential at this new customer placement, and remain focused on expanding our market share through both new and established customers by providing innovative, enabling technology to ensure their success.”

The power of Purion

The Purion platform redefines the ion implanter application space, delivering unmatched purity, precision and productivity to enhance customers’ device performance and yield.   On this platform, Axcelis has built the industry’s first complete implant product solution designed specifically for advanced planar and 3D devices while providing the most flexible and productive manufacturing capability for our customers. The systems’ common cross-product platform architecture is designed to drive manufacturing flexibility and lower the total cost of fab operations. All Purion implanters incorporate Axcelis’ industry leading Purion Contamination Shield Defense System, for unsurpassed implant quality, so even the most sensitive devices can realize optimized device performance.  The platform’s proprietary Purion Vector dose and angle control system, and constant focal length scanning deliver the most precise and repeatable dopant placement available today.   The platform’s superior beam current performance combined with the Purion 500wph end station provides the industry’s highest productivity. The Purion platform includes the Purion M medium current implanter, the Purion H high current implanter, and the Purion XE and Purion VXE high energy implanters.

Technavio’s latest market research report on the global field-programmable gate array (FPGA) market provides an analysis of the most important trends expected to impact the market outlook from 2017-2021. Technavio defines an emerging trend as a factor that has the potential to significantly impact the market and contribute to its growth or decline.

Sunil Kumar Singh, a lead analyst from Technavio, specializing in research on semiconductor equipment sector says, “The global FPGA market is expected to grow at a CAGR of close to 9% during the forecast period. The market is witnessing growth due to increased adoption in flourishing end-user segments such as telecommunications and consumer electronics. Demand for optimization in big data analytics is also leading to increased use of FPGAs in networking and storage applications.”

The top three emerging trends driving the global FPGA market according to Technavio hardware and semiconductor research analysts are:

  • Increased proliferation of IoT
  • Automation in automobiles
  • Increasing number of embedded processors in FPGA design

Increased proliferation of IoT

IoT is the latest trend in the global technology arena. IoT connects all essential home devices to the internet. This includes car, TV, laptop, coffee maker, automated door locks, GPS-enabled pet trackers, wearable devices, and mobile phones, forming a network of connected devices.

IoT comprises a staggering list of applications ranging from smart consumer electronics to wearables and automobiles. Designers must tackle significant implementation challenges, to deal with interfaces that are incompatible to IoT configuration, and create future systems that can accommodate billions of more devices and their performance requirements and processes. An FPGA-based design approach will assist in addressing these challenges due to their key ability of reprogrammability and low power consumption.

Automation in automobiles

Leading manufacturers such as Toyota, Audi, and Mercedes have invested considerable resources dedicated to R&D of automobile automation. Next-generation automobiles are expected to include speech recognition and video and image compatibilities, to provide optimal driving experience.

FPGAs allow multi-threading, which enables them to perform different functions in parallel. For instance, in Park Assist app, pictures are captured by cameras and are sent to a data fusion module. The data fusion module processes the image to display the corners of a car on the screen.

“Image processing functions such as image warping, analytics and object classification, and high dynamic range could be implemented on one chip using an FPGA due to its multi-threading feature. This allows fast booting of videos, enabling FPGAs to be widely used for surround-view camera systems and night vision systems in automobiles,” says Sunil.

Increasing number of embedded processors in FPGA design

Since 2012, the global FPGA market is witnessing an increase in the number of embedded processors in FPGA designs, to support growing demand for multiple function capability of FPGAs. This demand is further driven by emerging technologies such as IoT and new age smart devices such as wearables and their demanding processor requirements. FPGA modules can reduce power consumption and at the same time, improve on performance to deliver optimum output in reduced time.

According to the latest market study released by Technavio, the global semiconductor chip packaging market is expected to grow at a CAGR of more than 31% during the forecast period.

This research report titled ‘Global Semiconductor Chip Packaging Market 2017-2021’ provides an in-depth analysis of the market in terms of revenue and emerging market trends. This market research report also includes up to date analysis and forecasts for various market segments and all geographical regions.

The global semiconductor chip packaging market is dominated by APAC, which holds more than 71% of the total market share. The presence of many prominent semiconductor foundries is driving the market in the region.

One of the important driving factors of the semiconductor chip packaging market is the high adoption of semiconductor ICs in automobiles. The increasing automation of automobiles is creating high demand for semiconductors for use in automotive products such as GPS, airbag control, anti-lock braking system (ABS), infotainment, and collision detection technology, which is beneficial for the market growth.

Based on packaging techniques, the report categorizes the global semiconductor chip packaging market into the following segments:

  • 3DIC TSV stacks
  • Flip-chip wafer bumping
  • 2.5D interposers
  • 3D WLP
  • Fan-in WL CSP
  • FO WLP/Sip

The top three revenue-generating packaging technique segments in the global semiconductor chip packaging market are discussed below:

3DIC through-silicon via (TSV) stacks

“The 3DIC through-silicon via stacks packaging technique will be responsible for generating almost 75% of the market revenue by 2021, posting a CAGR of 45% through the forecast period. This high adoption of TSV platforms is pushed by the growing need to increase functionalities, performance, and integration,” says Sunil Kumar Singh, one of the lead analysts at Technavio for semiconductor equipment research.

Form factor and cost reduction of the TSV platforms also play an important part in its rising adoption. This technology is emerging as one of the most crucial platforms for high-end memory applications, heterogeneous interconnection with micro-electro-mechanical systems (MEMS), sensors, radio frequency (RF) filters, and performance applications.

Flip-chip wafer bumping

Flip-chip or controlled collapse chip connection (C4) is used to solder connections between semiconductor devices, such as IC chips and micro-electro-mechanical systems (MEMS), and an external circuit. This technology reduces power consumption by a great extent and also offers high-frequency transmission, which attracts a higher number of end-users to adopt this technology.

2.5D interposers

The increasing number of devices with access to the internet is creating additional bandwidth needs, which supports high-performance computing and cloud infrastructure. The growing popularity of connected cars is also a major driver of streaming bandwidth. Silicon interposer packaging architectures are being developed and manufactured to meet these continually increasing bandwidth requirements.

“2.5D silicon interposers manufactured using four-metal layer back-end-of-line process has achieved data rates up to 11.5 Gbps. These impressive statistics are pushing for the high adoption of the 2.5D interposers packaging technique,” says Sunil.

The top vendors highlighted by Technavio’s research analysts in this report are:

  • Applied Materials
  • ASM Pacific Technology
  • Kulicke & Soffa Industries
  • TEL
  • Tokyo Seimitsu

Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2017.

Driving the industry forward with materials engineering

Raja_Prabu_fullPrabu Raja, vice president and general manager, Patterning and Packaging Group, Applied Materials, Inc.

Over the past few years, the industry has made remarkable progress in bringing 3D chip architectures to volume production. In 2017, we will continue to see exciting technology innovations for scaling 3D NAND devices to 64 layers, ramping the 10nm process node into volume manufacturing and increasing the adoption of highly integrated chip packages.

With the transition to the 3D and sub-10nm era, the semiconductor world is changing from lithography-based scaling to materials-enabled scaling. This shift requires multiple new materials and capabilities in selective processing.

The magnitude and pace of these changes are truly disruptive. For example, with 3D NAND materials innovations for hard mask deposition and hard mask etch are essential. The challenge is to build high aspect ratio vertical structures with uniform profiles from the top to the bottom as more layers are added. Selective removal processes can remove targeted materials in vertical and horizontal structures without damage or residue throughout the stack.

For logic/foundry, the introduction of the 10nm process node in volume manufacturing brings significant growth in the number of patterning steps. This trend will increase even more for 7nm and below designs. Patterning these advanced nodes requires innovative etch capabilities to deliver feature-scale uniformity with low line edge roughness. Selective processes and alternative manufacturing schemes will also be needed as the industry seeks solutions for layer-to-layer vertical alignment. We expect this to result in a two-fold increase in the number of materials to be deposited and removed.

Finally, the industry will continue to adopt new and improved packaging schemes for enabling increased device performance, lower power consumption and to deliver desired form factors. In 2016, we saw the volume adoption of Fan-Out packaging in mobile devices and this trend is expected to grow further in 2017. The high performance computing segment will pursue 2.5D interposer and/or 3D TSV packaging schemes for higher memory bandwidth, lower latency and better power efficiency.

Applied Materials is focused on delivering game-changing selective process technologies and materials innovations to help solve the industry’s toughest challenges.

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STATS ChipPAC Pte. Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has been ranked among the world’s top 10 semiconductor equipment manufacturing companies in the 2016 Patent Power Scorecards published by the Institute of Electrical and Electronics Engineers (IEEE), the world’s largest professional association for the advancement of technology. This is the seventh consecutive year that STATS ChipPAC has been recognized in the annual scorecards.

The 2016 Patent Power Scorecards are based on objective, quantitative benchmarking of U.S. Patent and Trademark Office records by 1790 Analytics, an Intellectual Property (IP) evaluation firm. The patent portfolios of more than 6,500 leading commercial enterprises, academic institutions, nonprofit organizations, and government agencies worldwide were reviewed through the end of 2015.  The scorecards rate the most valuable IP portfolios based on several factors including the size of an organization’s patent portfolio, quality, impact, originality and general applicability.

STATS ChipPAC was ranked eighth in the Semiconductor Equipment Manufacturing scorecard, the highest ranking received by an Outsourced Semiconductor Assembly and Test (OSAT) provider for the year. As of the end of 2015, STATS ChipPAC had been granted more than 1,500 patents by the U.S. Patent and Trademark Office (USPTO). STATS ChipPAC has been the leading U.S. patent holder among OSAT providers worldwide since 2011 and has built up a patent portfolio in which advanced or future technologies comprise more than 65% of its IP, significantly higher than other OSATs in the industry.

“Year after year we have continued to focus on technology innovation and prioritized our investments in key areas such as wafer level packaging, flip chip interconnection, System-in-Package (SiP), 2.5D and 3D integration. By driving technology development in these areas, we are able to provide innovative integration solutions that enable our customers to differentiate their products in the marketplace,” said Shim Il Kwon, Chief Technology Officer, STATS ChipPAC. “With the combined strength of the JCET Group, we offer our customers an IP portfolio that is unmatched in the OSAT industry.”

At the 2017 European 3D Summit in Grenoble (France, Jan 23-25), research and innovation hub for nano-electronics and digital technology imec and supplier of wafer-bonding equipment EV Group (EVG) announce an extension to their successful collaboration, achieving excellent wafer-to-wafer overlay accuracy results in both hybrid bonding and dielectric bonding. Expanding this collaboration, EVG will become a partner in imec’s 3D integration program through a joint development agreement to further improve overlay accuracy in wafer-to-wafer bonding.

Wafer-to-wafer bonding is a promising technique for enabling high-density integration of future ICs through three-dimensional (3D) integration. This is achieved by aligning top and bottom wafers that are then bonded, thus creating a stacked IC. An important advantage is that wafers/ICs with different technologies can be stacked, e.g. memory and processor ICs.

Many of the alignment techniques and bonding methods for 3D integration have evolved from microelectromechanical system (MEMS) fabrication methods. The fundamental difference between MEMS and 3D integration is that the alignment or overlay accuracy has to be improved by 5–10 times. Accurate overlay is needed to align the bonding pads of the stacked wafers and it is essential to achieving a high yield with wafer-to-wafer bonding. Imec and EVG have realized excellent results on overlay accuracy.

Firstly, the hybrid (via-middle) wafer-to-wafer bonding technique was improved by using EVG’s high quality bonding system with integration definition of bonding pads, resulting in a high yield and a 1.8µm pitch, which is significantly better compared to recently published results at recognized conferences such as ECTC and 3DIC reporting 3.6µm pad size,.

Secondly, the dielectric (via-last) wafer-to-wafer bonding technique was tackled. This technique requires extremely good overlay accuracy to align the copper pads from both wafers, which are then contacted by through-silicon vias (TSVs). In this case, 300nm overlay across the wafer was achieved.

“By joining forces, we achieved these excellent results on overlay accuracy,” explains Eric Beyne, fellow at imec. “We are excited that we can expand our collaboration with EVG with a JDP and the installation of EVG’s GEMINI FB XT wafer bonder in our cleanroom. The GEMINI FB XT has the potential to further reduce the wafer-to-wafer overlay errors and therefore allow for the development of sub-micron wafer-to-wafer interconnects technologies.”

“Further improving the overlay accuracy for wafer-to-wafer bonding into the sub-200nm range requires optimization of the interaction between the wafer bonding tool and processes as well as pre-and post-processing and the wafer material,” explains Markus Wimplinger, corporate technology development & IP director at EVG. “We are excited to partner with imec in an effort to advance overlay accuracies for wafer-to-wafer bonding to meet the needs of future 3D IC designs that rely on high density interconnects”

Imec’s 3D integration program explores technology options to define innovative solutions for cost-effective realization of 3D interconnect with TSVs. Imec’s 3D integration processes are completely executed on 300mm. Imec also explores 3D design to propose methodologies for critical design issues, enabling effective use of 3D interconnection on system level.

imec wafer to wafer

Analog Devices, Inc. (NASDAQ: ADI), a developer of high-performance semiconductors for signal processing applications, today announced that Mark M. Little, former Senior Vice President, GE Global Research and Chief Technology Officer of General Electric Company, has been elected as a Director of the Company, and that the Board of Directors of the Company intends to elect Robert H. Swanson, Executive Chairman of Linear Technology Corporation, as a Director following the closing of the Company’s acquisition of Linear Technology Corporation. Richard Beyer and John Hodgson will retire from the Company’s Board of Directors, effective as of the Company’s 2017 Annual Meeting of Shareholders.

“We are very grateful to Rich and John for their years of dedicated service to ADI, and for their wise counsel as members of our Board,” said Ray Stata, ADI Chairman of the Board. “We are pleased to welcome Mark Little as a new Director, and we are also looking forward to Bob Swanson joining the Board following our acquisition of Linear Technology Corporation.”

Dr. Little is the former Senior Vice President, GE Global Research and Chief Technology Officer of General Electric Company, a global digital industrial company. Dr. Little joined GE in 1978, and during his 37-year tenure, held management positions in engineering and business, culminating with his most recent position, which he held from 2005 to 2015. In addition to his technology leadership, Dr. Little led several multi-billion dollar business units at GE including GE Energy’s power-generation segment. Dr. Little holds bachelor’s and master’s degrees in mechanical engineering from Tufts and Northeastern universities, respectively, and a Ph.D. in mechanical engineering from Rensselaer Polytechnic Institute.

Mr. Swanson, a founder of Linear Technology, has served as Executive Chairman of the Linear Technology board of directors since January 2005. Prior to that time, he served as Chairman and Chief Executive Officer of Linear Technology since its incorporation in 1981. Mr. Swanson has a B.S. degree in Industrial Engineering from Northeastern University.

On July 26, 2016, ADI and Linear Technology entered into an agreement and plan of merger that provides for the acquisition of Linear Technology by the Company. The Company and Linear Technology currently expect the acquisition to be completed by the end of the Company’s second fiscal quarter of 2017, subject to receipt of the remaining required regulatory approvals and subject to the satisfaction or waiver of the other conditions contained in the merger agreement. The Board of Directors of the Company intends to elect Mr. Swanson to the Board at the later of the completion of the acquisition or the Board of Directors meeting following the Company’s 2017 Annual Meeting of Shareholders, currently anticipated to be held on March 8, 2017.

TechSearch International predicts strong market growth for fan-in wafer level packages (WLPs) and fan- out WLP (FO-WLP). Driven by demand for thin, low-profile packages in smartphones, tablets, and wearable devices such as smart watches, fitness bands, and virtual reality headsets, fan-in WLPs are projected to have a >10% growth rate from 2015 to 2020. Starting from shipments of a few hundred million packages in 2015, FO-WLP shows a staggering growth rate of 82% over the five-year period. The use of FO-WLP for RF, audio CODEC, and power management ICs, coupled with Apple’s adoption of TSMC’s InFO FO-WLP as the bottom package-on-package (PoP) in Apple’s iPhone 7, is driving unit volume shipments. Automotive radar, connectivity modules, and other applications promise continued growth for FO-WLPs. Cost-reduction pressures are driving the development of alternatives to reconstituted wafer FO-WLP in the form of large area panel processing and flip chip on coreless or thin core substrates. Chip package interaction (CPI) is analyzed for WLPs and flip chip.

TechSearch International’s new study, Flip Chip and WLP: Market Forecasts and Technology Analysis, provides detailed analysis of the drivers for fan-in WLP, FO-WLP, and flip chip. The detailed analysis is based on the company’s 29-year history of studying markets and critical technology and infrastructure issues.

Driven by small size devices such as filters, low noise amplifiers, power amplifiers, and switches found in smartphones, flip chip growth shows >13% CAGR in unit volume from 2015 to 2020. Documentation of the continued transition to Cu pillar is provided. Flip chip applications, bump types, and pitch trends are based on extensive interviews and research. Flip chip assembly options are discussed. Growth in gold bumping for LCD driver ICs is included. A critical analysis of planned capacity and utilization is provided for each geographic region, showing projections for strong growth in China.

The 115-page report with full references provides forecasts for the flip chip wafer bumping market by application, device type, number of wafers, and die shipments. Merchant and captive capacity is included. Forecasts for fan-in and FO-WLP demand are projected in number of die and wafer shipments. Bumping, wafer level packaging, substrate suppliers, assembly equipment, underfill material, and contract assembly service providers are listed. A set of 78 PowerPoint slides accompanies the report.

TechSearch International, Inc., founded in 1987, is a market research leader specializing in technology trends in microelectronics packaging and assembly. Multi- and single-client services encompass technology licensing, strategic planning, and market and technology analysis. TechSearch International professionals have an extensive network of more than 17,000 contacts in North America, Asia, and Europe. For more information, contact TechSearch at tel: 512-372-8887 or see www.techsearchinc.com.

Fire, rain, and M&A 


January 19, 2017

By SEMI staff

The expert panel, “The Future of M&A in the Semiconductor Industry,” was a hot topic at SEMI’s Industry Strategy Symposium (ISS) conference on January 11.  So hot, it seems, that midway through the panel discussion, a fire alarm triggered and the whole group stepped outside for a quick breather.  Fortunately, this came at a break in the almost nonstop rain – that felt as though the Ritz Carlton might wash off the bluffs of Half Moon Bay.

fire rain

The rain couldn’t put a damper on the mood, though.  Forecasters throughout the conference revised upwards their 2016 results and 2017 forecasts (http://www.semi.org/en/semi-iss-2017-uncovers-new-growth-forecast-upgrades-1) and Diane Bryant, EVP and GM of Intel’s Data Center Group sparked the audience with an amazing keynote that made clear this is the best time ever to be in the semiconductor manufacturing supply chain.

But, how that industry might look in the future was the business of the M&A panel moderated by Robert Maire of Semiconductor Advisors with experts:

  • Patrick Ho, senior research analyst, Semiconductor Capital Equipment at Stifel Nicolaus
  • John Ippolito, VP Corporate Development at MKS Instruments
  • Israel Niv, former CEO of DCG Systems
  • Tom St. Dennis, chairman of the Board of FormFactor.

Will the huge deals of 2015 and 2016 continue?

Setting up the panel, Maire observed that 2015 and 2016 were huge in transaction size (over $100 billion announced in 2015), but while the values of the deals have jumped, the number of deals has remained fairly consistent over the past several years. Also, China has more significantly moved into the M&A market in 2015, in the range $4 to $5 billion.

It appears that M&A will continue, but not at the same pace as 2015 and 2016 due to increasing political, regulatory, and industry pushback.  In the equipment space, while big deals such as Advantest and Verigy were possible in 2011, the current climate has seen big deals falter including Applied Materials and Tokyo Electron; Lam Research and KLA-Tencor; and Aixtron and Fujian Grand Chip.

However, Maire observed that the motivations for M&A continue; for instance, Intel needs to offset a declining PC market and ramp IoT, VR, and Cloud activity and will likely consider M&A as part of its approach.  Similarly, opportunities for equipment companies to increase scale and size exist for process control companies and in the back-end segment where further consolidation appears necessary.

China becomes a player

China’s ambitions in M&A may have been complicated by recent events, but with a $150 billion investment fund there are likely more opportunities ahead.  China has stated the intent to move from producing just 10 percent of its IC consumption to 70 percent in ten years and catching up technologically by 2030.  While some see concerns given China’s investment and later pricing collapses in FPD, PV, and LED, others see China’s efforts to increase its indigenous production of ICs as similar to what has happened as the industry spread from U.S. and Europe to Japan, Taiwan, and Korea.

The panel responded to questions from Maire, questions submitted from the audience, and live audience questions.  Ho noted that big deals in semiconductor equipment appear, for the time being, to be difficult or over.  However, there is still low-hanging fruit and smaller deals.  There is a need to focus on scale and size because customers (IC manufacturers) are bigger and fewer.  For example, Form Factor’s combination with Cascade brought size and scale and enabled Form Factor to be more competitive.

The future for semiconductor equipment consolidation

Several questions revolved around where M&A would happen in the semiconductor equipment space.  There was general consensus that M&A of any of the “big five” (not named, but likely ASML, Applied Materials, Lam Research, Tokyo Electron, and KLA-Tencor) were off the table in the short term due to both regulatory pressure and industry pushback given fears of overly strong supplier power.  Niv thought there were opportunities for consolidation in the metrology and process control space.  Ippolito thought there might be further consolidation opportunities in motion control.  St. Dennis thought there were opportunities throughout the whole supply chain.  He pointed out that the benefits of acquiring a good company were significant, including great talent (difficult and time consuming to develop organically), synergies in not just SG&A, but in technology and field organizations.

The role of private equity was raised.  Ippolito noted that the private market and private equity have roles to play in consolidation opportunities, noting the success of Atlas Copco with Edwards Vacuum and Oerlikon Leybold as an example.

Several questions focused on China.  Niv pointed out the industry needs to think about China similar to how they thought about Japan when Japan was emerging as an IC manufacturing power.  Partnering with Japanese companies was an effective strategy for many and brought long-term success in that market.  Ippolito thought that very large China deals might be off the table for a while, but smaller deals would likely go through.  He noted that $150 billion (the China investment fund) is a lot of money and that tends to find a way forward.

Size matters

The panel seemed to agree size matters.  Niv observed that deals have to be the right size to be digestible with a deal of 10 percent size ratios being easier than other ratios.  Niv noted that one cannot realistically aspire to be acquired by Applied Materials at a revenue of only $20 to $30 million.  For this size, he advised that you are better off getting there by first being an aggregator.  Ho expanded on this by noting that small cap equipment companies can’t attract the attention of the “big five.”  $200 million of revenue only gives the “big five” about a penny of accretion.  For MKS Instruments, the deal with Newport was positive because it added almost $1 in accretion and is an example of a better match in size.

It was a testament to the keen interest in the M&A panel that after the fire alarm evacuation, virtually everyone returned and the audience was nearly immediately again fully engaged in trying to understand what stamp M&A will next leave upon future of the industry.  If we learned anything in 2016, it is that surprises will happen (so it seems, fire alarms will ring when you least expect them).  And, predicting rain, like predicting which deals will go through in a fundamentally new geopolitical environment, will be a guessing game.  However, there’s no doubt that M&A will continue and the opportunities ahead of us will rewrite our industry map.

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