Category Archives: 3D Integration

TSMC’s UBM-free fan-in WLCSP


September 21, 2016

BY DR. PHIL GARROU, Contributing Editor

At the 2016 ECTC Conference, TSMC discussed their UFI (UBM-Free Integration) Fan-In WLCSP technology which they claim enables large die fine pitch packages.

Development of low-cost WLCSP for large die with high I/O count is desired for broadening its applications. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5×5 mm2 with ball pitch smaller than 350 μm.

TSMC has discovered that by controlling the maximum strain location and optimizing materials, chip warpage and the stress between silicon and the PCB can be reduced which improves both component and board-level reliabilities of WLCSP packages. Packages as large as 10.3×10.3 mm2 with both 400 and 350 μm ball pitches have been developed.

Screen Shot 2017-04-21 at 9.21.34 AM

UBM is used as an interfacial layer between the metal pad of the integrated circuit and the solder ball. The formation of UBM/ solder intermetallic compounds (IMC) limits the board level reliability of the package due to the poor mechanical robustness of IMCs. When the die size is increased, stress increases which promotes cracking at the UBM/solder ball interface.

TSMC claims their UFI WLCSP fabrication cost is lower than conventional WLCSPs due to the elimination of the UBM. Removal of the UBM also reduces the thickness of the package by 30%. Figure 1 compares the structures of a standard WLCSP vs the TSMC UFI WLCSP. In the UFI WLCSP, the solder balls are directly mounted to the Cu RDL followed by the polymeric PL (protection layer which secure the balls.

Very similar removal of UBM and subsequent thickening of the copper pad has been reported before by Amkor in 2010 [1].

TSMC simulation results showed the solder joint fatigue life decreases with increasing die sizes for both UFI and the conventional WLCSP. Predicted solder ball fatigue life was found to increases with decreasing die thickness. The authors suggest that decreasing the die thickness not only reduces the thermal expansion difference between the die and the PCB, but also causes the die to bend more under thermal loading. In addition, simulation results imply that solder joint creep strain for solder mask defined (SMD) structures is 72% higher than for non-solder mask defined (NSMD) structures because of its reduced flexible solder joint height and the constraint of the solder mask. Thus they concluded that it is better to use NSMD type of PCB for UFI WLCSP. The use of NSMD structures to increase reliability has been known since the work of Bell Labs Ejim [2].

The UFI WLCSP passes all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution, respectively. 10mm UFI WLCSP have passed component-level reliability tests such as TCB1000, uHAST96 and HTS1000, and board- level reliability tests of TCG500 and drop tests.
To demonstrate the possibility of higher interconnect density, they fabricated UFI- WLCSP with multiple RDL layers. The package with two RDL layers had die size of 10.3 x 10.3 mm2 and ball pitch of 350 μm (Figure 2). Again such structures passed all component level reliability testing.

References

1. http://imapsource.org/doi/abs/10.4071/2010DPC- tha32?journalCode=apap
2. TI Ejim et. al., “Reliability performance and failure mode of high I/O thermally enhanced ball grid array packages” Electronics Manufacturing
Technology Symposium, 1998, p.323 – 332.

Solid State Technology announced today that its premier semiconductor manufacturing conference and networking event, The ConFab, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. A 30% increase in attendance in 2016 with a similar uplift expected in 2017, makes the venue an ideal meeting location as The ConFab continues to expand.

    

For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collaborate on critical issues.

“The semiconductor industry is maturing, yet opportunities abound,” said Pete Singer, Editor-in-Chief of Solid State Technology and Conference Chair of The ConFab. “The Internet of Things (IoT) is exploding, which will result in a demand for “things” such as sensors and actuators, as well as cloud computing. 5G is also coming and will be the key technology for access to the cloud.”

The ConFab is the best place to seek a deeper understanding on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportunities facing semiconductor manufacturers. “In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities,” Singer added.

Dave Mount

David Mount

Solid State Technology is also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees that will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GLOBALFOUNDRIES, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For details on attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

Toshiba America Electronic Components, Inc. (TAEC) has expanded its family of 24nm single-level cell (SLC) NAND flash memory solutions. The new 16 gigabit (Gb) BENAND is housed in an industry-standard 48-pin TSOP package, and offers a combination of high read/write performance, effective write endurance (using 8-bit BCH error correction code), and extended temperature operation. This makes it suitable for a wide variety of commercial and industrial applications.

The new addition rounds out Toshiba’s broad SLC product lineup, allowing designers to take advantage of the price/performance of advanced 24nm NAND flash SLC technology at densities from 1Gb to 128Gb. Based on a 4x4Gb die, 16Gb BENAND operates from a power supply of 2.7V to 3.3V with a temperature range of -40°C to 85°C. Many industrial applications have a long life expectancy. Toshiba designed BENAND with this in mind. With the ability to replace older generations of discrete SLC NAND, BENAND extends the product life of everything from telecom applications and LCD TVs to robots and printers – while also potentially reducing BOM costs.

According to Brian Kumagai, director of business development for TAEC, “SLC NAND is still very much an integral part of the overall NAND market, and leading-edge 24nm devices play a key role in enabling replacement of the older NAND devices that are still being used today.”

Toshiba’s 24nm BENAND requires no ECC from the host controller. This enables it to be used with host controllers that do not have 8-bit ECC capability.  Many legacy designs still use older processors that do not have 8-bit ECC capability, making BENAND a viable option for companies looking to design in a cutting-edge NAND solution with existing hardware. To ensure easy migration, BENAND’s features such as page/block size, spare area size, commands, interface and package remain the same as legacy 4xnm SLC NAND.

Toshiba’s continuing commitment to supporting 24nm SLC NAND flash provides industrial designers with the confidence of knowing that they have chosen the correct technology for their applications requiring production longevity. This support eliminates concerns about redesigning to a newer generation.

By Ted Shafer, Business Manager, Mature Product Sales, ASML

Ted Shafer of ASML reports on the highlights from the ≤200mm manufacturing session during SEMICON West, organized by the SEMI Secondary Equipment and Applications Special Interest Group. Your next opportunity to catch up on latest trends on ≤200mm manufacturing trends and its impact on the secondary equipment and applications market is SEMICON Europa 2016 and the Secondary Equipment Tech Arena session. 

Wednesday July 13th at SEMICON West a seminar and panel discussion were held to discuss the longevity and growth of the 200mm equipment market, and responses from IDMs, OEMs and 3rd parties to the challenges this growth presents.

Tim Tobin of Entrepix was the first speaker.  Entrepix is a premier 3rd party refurbisher of CMP and other process equipment.  Tim was the first to remark on a phenomenon that the other speakers and panelists also noted: a huge portion of the die in the devices we use daily do not require state of the art 300mm manufacturing.  For example, 60% – 80% of the chips in your smartphone or tablet are manufactured on 200mm – or smaller – wafers.  These wafers are created using mature equipment, which is frequently purchased from the secondary market, often from refurbishers such as Entrepix.

SEMI’s Christian Dieseldorff next provided a great overview of 200mm market trends, titled “200mm Fab: Trends, Status, and Forecast”.  Driven by the growth of IoT (Internet of Things), new 200mm fabs are being built and additional capacity is being added at existing fabs.  Key take-away is that after peaking in 2006, then declining for several years, 200mm wafer starts per month are now forecasted to exceed 2006’s level of 5.4M by 2019.  The question on everyone’s mind is, once that level is exceeded, where will the tools come from to manufacture those wafers?

200mm-image1

Pierric Gueguen of Yole spoke of the increased adoption of exotic substrates like GaN, Sapphire and Silicon Carbide.  These substrates provide many performance advantages, such as lower power consumption, faster switching speed, and high temperature resistance.  Yet the substrates cannot scale to 12”, and sometimes not to 8”.  So the increased adoption of these substrates is driving additional demand for 150mm/200mm tools.

As a counter-point to the 200mm discussions, Karen Erz of Texas Instruments gave a very well-received presentation on TI’s pivot to 300mm for analog, which has traditionally been manufactured on 200mm wafers.  A key to TI’s success is to embrace without fear buying opportunities for used equipment when they present themselves.  TI does not compete at the leading edge – their minimum feature size is 130nm – and thus mature, pre-owned, cost-effective equipment is always their first choice.  In fact, surplus 300mm is often more available, and less expensive, than comparable 200mm tools.  TI capitalized on the bankruptcies of the 300mm fabs of Qimonda Dresden, Qimonda Richmond, and PROMOS, also surplus tools at Powerchip, to scoop up large batches of inexpensive 300mm tools.  They continue to buy surplus 300mm tools when they come on the market, even in advance of actually requiring the tools.  As a result, 92% of RFAB’s analog production is done with pre-owned 300mm equipment.

Emerald Greig of Surplus Global, in addition to organizing the seminar, also provided a well-researched presentation on surplus equipment trends, titled “The Indispensable Secondary Market”.  Surplus Global is one of the largest surplus equipment traders, and they track the used equipment market very closely.  Emerald discussed how the supply of tools per year is trending dramatically downwards.  In 2009 they saw 6,000 tools come on the market, and that run-rate has steadily decreased to the point where by last year it was under 1,000/year.  This year we are at just 600.

200mm-image2

AMAT’s John Cummings provided the first OEM perspective on the 200mm market.  John showed how over 70% of the chips in the segments of automotive, wearables and mobile are produced on <=200mm wafers.  These segments are growing – for example a BMW i3 contains an astonishing 545 total die, and 484 of them are manufactured on <=200mm wafers.   AMAT reports that there are not enough used 200mm tools on the market to support the demand, and thus AMAT supplies their customers with new 200mm tools to augment the upgrades and refurbs they perform on pre-owned tools.  AMAT also provides new functionality for their mature 200mm products, increasing their usefulness and extending their lifetime.

Finally there was the OEM panel discussion, consisting of Kevin Chasey of TEL, David Sachse of LAM, Hans Peters from Ebara, and Ted Shafer of ASML.  Emerald Greig of Surplus Global provided some initial questions and solicited additional ones from the audience.   The OEMs echoed one common theme of the presentations, that 200mm demand is robust, and core tools are increasingly hard to find.  TEL additionally noted that China is a growing player in this market, and that OEMs must now support their 200mm product lines much longer than initially planned.  LAM said that 200mm core supply is so tight that the prices are rising above even comparable 300mm cores.  In response, LAM augments the supply of used tools by creating new 200mm tools.  Ebara added that the core tools coming on the market are often undesirable first-generation tools or tools in very bad condition.  On the other hand, this creates a role for the OEM, who has the expertise to make these tools production-worthy.  ASML noted that many of their larger 200mm customers are considering a migration from the PAS 5500 platform to ASML’s TWINSCAN platform for 200mm production.  Although developed for 300mm, and in general larger and more expensive than the 200mm 5500 series, ASML has spent the last 15 years making TWINSCANs increasingly productive and reliable, to the point where they often offer superior cost of ownership at 200mm than ASML’s 5500 platform.  Furthermore, customers buying TWINSCAN for 200mm production have an easy upgrade to 300mm when/if their plans call for it.

200mm-image3

In summary, the seminar showcased a robust exchange of ideas, where the presenters and panelists examined the resurgent 200mm market, and described many solutions to the common challenge of limited and expensive 200mm cores.

Attend SEMICON Europa and the Secondary Equipment & Applications session on October 26 to find out the latest trends and discuss in what areas OEMs, IDMs and secondary  market operators can cooperate more closely to improve sustainable access to legacy manufacturing equipment.

Find out more about SEMI’s Secondary Equipment and Applications Special Interest Group and the Secondary Equipment Legacy Management Program that is currently under development. For more information and to get involved, contact [email protected] (Ms. Rania Georgoutsakou, Director Public Policy for Europe, SEMI).

By Zvi Or-Bach, President & CEO, MonolithIC 3D Inc.

As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

Our March 2014 blog Moore’s Law has stopped at 28nm has recently been re-confirmed. At the time we wrote: “From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.” This reconfirmation can be found in the following IBS cost analysis table slide, presented at the early Sept FD-SOI event in Shanghai.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

As reported by EE Times – Chip Process War Heats Up, and quoting Handel Jones of IBS “28nm node is likely to be the biggest process of all through 2025”.

IBS prediction was seconded by “Samsung executive showed a foil saying it believes 28nm will have the lowest cost per transistor of any node.” The following chart was presented by Samsung at the recent SEMICON West (2016).

Zvi 2

And even Intel has given up on its “every two years” but still claims it can keep reducing transistor cost. Yet Intel’s underwhelming successes as a foundry suggests otherwise. We have discussed it in a blog titled Intel — The Litmus Test, and it was essentially repeated by SemiWiki’s Apple will NEVER use Intel Custom Foundry!

This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, with a few products pursuing scaling to 7nm while the majority of designs use 28nm or older nodes.

The following chart derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Zvi 3

Yes, the 50-year march of Moore’s Law has ended, and the industry is now facing a new reality.

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new markets and products such as the emerging market of IoT.

A good opportunity to learn more about these new scaling technologies is the IEEE S3S ’16, to be held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. It starts with 3D and FDSOI tutorials, the emerging technologies for the IC future. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from an imec, MIT, and Korea university collaboration will present their work on advanced monolithic 3D integration technologies. Many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.

As part of an initiative to optimize service to the growing global polymer processing market, Nordson Corporation (Nasdaq:NDSN) today announced it plans to combine its existing screw and barrel operations in Youngstown, Ohio; New Castle, Pennsylvania; and Pulaski, Virginia into a single expanded manufacturing center of excellence in Austintown, Ohio.

“We expect this initiative to drive efficiencies in manufacturing processes, decrease lead times, enhance customer service, improve competitiveness and accelerate growth,” said John Keane, Nordson Corporate Senior Vice President. “Our plan is for Austintown to join similar regional hubs for our screw and barrel products in Thailand and Germany. No other single supplier will be able to provide the polymer industry with such localized service on a global scale.”

Nordson expects the transition to an existing facility in Austintown to be completed over the next 18 months, subject to the conclusion of customary negotiations with local and state officials. The transition will occur in stages to minimize any potential impact to current customers. Planned investments in the facility over the period include upgraded bi-metallic processing and machining systems to improve product quality, precision and throughout.

The majority of positions in the existing Youngstown, New Castle and Pulaski facilities will transfer to the Austintown facility. Total employment in Austintown is expected to be approximately 260. Nordson will be actively recruiting for any positions not being filled by current employees.

GLOBALFOUNDRIES today announced plans to deliver a new leading-edge 7nm FinFET semiconductor technology that will offer the ultimate in performance for the next era of computing applications. This technology provides more processing power for data centers, networking, premium mobile processors, and deep learning applications.

GLOBALFOUNDRIES’ new 7nm FinFET technology is expected to deliver more than twice the logic density and a 30 percent performance boost compared to today’s 16/14nm foundry FinFET offerings. The platform is based on an industry-standard FinFET transistor architecture and optical lithography, with EUV compatibility at key levels. This approach will accelerate the production ramp through significant re-use of tools and processes from the company’s 14nm FinFET technology, which is currently in volume production at its Fab 8 campus in Saratoga County, N.Y. GLOBALFOUNDRIES plans to make an additional mutli-billion dollar investment in Fab 8 to enable development and production for 7nm FinFET.

“The industry is converging on 7nm FinFET as the next long-lived node, which represents a unique opportunity for GLOBALFOUNDRIES to compete at the leading edge,” said GLOBALFOUNDRIES CEO Sanjay Jha. “We are well positioned to deliver a differentiated 7nm FinFET technology by tapping our years of experience manufacturing high-performance chips, the talent and know-how of our former IBM Microelectronics colleagues and the world-class R&D pipeline from our research alliance. No other foundry can match this legacy of manufacturing high-performance chips.”

“GLOBALFOUNDRIES made a bold decision to jump directly from 14nm to 7nm–a decision that is now supported by several leading semiconductor companies as they see only marginal performance and power benefits for the high cost of the 10nm process node,” said Jim McGregor, founder and principal analyst at TIRIAS Research. “Much like the 28nm and 16/14nm process nodes, 7nm appears to be the next major process node that will be widely leveraged by the entire semiconductor industry for at least the next decade.”

“Leading-edge technologies like GLOBALFOUNDRIES 7nm FinFET are an important part of how we deliver our long-term roadmap of computing and graphics products that are capable of powering the next generation of computing experiences,” said Dr. Lisa Su, president and CEO, AMD. “We look forward to continuing our close collaboration with GLOBALFOUNDRIES as they extend the solid execution and technology foundation they are building at 14nm to deploy high-performance, low-power 7nm technology in the coming years.”

“IBM is committed to pushing the limits of semiconductor technology as part of its aggressive long term research agenda,” said Arvind Krishna, senior vice president and director of IBM Research. “IBM Research continues to collaborate with GLOBALFOUNDRIES in developing new ideas, new skills and new technologies that will help accelerate our joint research in 7nm technology and beyond.”

GLOBALFOUNDRIES will deliver a comprehensive and competitive IP library, co-optimized with process development. To enable customers to accelerate adoption of 7nm FinFET technology, GLOBALFOUNDRIES has expanded its strategic partnership with INVECAS beyond 14LPP and FDX™ processes to now include foundry IP development for 7nm process technologies. This will provide customers with a strong foundation to build early designs that meet their performance, power and area requirements.

“INVECAS specializes in providing unrivaled IP solutions, ASIC and design services to GLOBALFOUNDRIES’ customers that span the wide-range of GLOBALFOUNDRIES’ leading edge FinFET and FDX processes,” said Dasaradha Gude, CEO, INVECAS. “Our strategic partnership with GLOBALFOUNDRIES combined with our tailor-made foundry IP model allows us to develop a 7nm FinFET process foundation IP that meets the challenging performance requirements of 7nm customers’ leading-edge applications.”

Building on the success of its 14LPP technology platform, GLOBALFOUNDRIES’ 7nm FinFET technology is positioned to enable next-generation computing applications that demand ultra-high performance, from high-end mobile SoCs to processors for cloud servers and networking infrastructure. The company’s high-performance offerings are complemented by its 22FDXTM and 12FDXTMtechnologies, which have been developed to meet the ultra-low-power requirements of the next generation of intelligent connected devices, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

GLOBALFOUNDRIES’ 7nm FinFET technology will be supported by a full platform of foundation and complex intellectual property (IP), including an application-specific integrated circuit (ASIC) offering. Test chips with IP from lead customers have already started running in Fab 8. The technology is expected to be ready for customer product design starts in the second half of 2017, with ramp to risk production in early 2018.

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry’s first multi-node FD-SOI roadmap. Building on the success of its 22FDX offering, the company’s next-generation 12FDX platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

As the world becomes more and more integrated through billions of connected devices, many emerging applications demand a new approach to semiconductor innovation. The chips that make these applications possible are evolving into mini-systems, with increased integration of intelligent components including wireless connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption. GLOBALFOUNDRIES’ new 12FDX technology is specifically architected to deliver these unprecedented levels of system integration, design flexibility, and power scaling.

12FDX sets a new standard for system integration, providing an optimized platform for combining radio frequency (RF), analog, embedded memory, and advanced logic onto a single chip. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate energy efficiency.

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

GLOBALFOUNDRIES’ new 12FDX technology is built on a 12nm fully-depleted silicon-on-insulator (FD-SOI) platform, enabling the performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET. The platform offers a full node of scaling benefit, delivering a 15 percent performance boost over today’s FinFET technologies and as much as 50 percent lower power consumption.

“Chip manufacturing is no longer one-shrink-fits-all. While FinFET is the technology of choice for the highest-performance products, the industry roadmap is less clear for many cost-sensitive mobile and IoT products, which require the lowest possible power while still delivering adequate clock speeds,” said Linley Gwennap, founder and principal analyst of the Linley Group. “GLOBALFOUNDRIES’ 22FDX and 12FDX technologies are well positioned to fill this gap by offering an alternative migration path for advanced node designs, particularly those seeking to reduce power without increasing die cost. Today, GLOBALFOUNDRIES is the only purveyor of FD-SOI at 22nm and below, giving it a clear differentiation.”

“When 22FDX first came out from GLOBALFOUNDRIES, I saw some game-changing features. The real-time tradeoffs in power and performance could not be ignored by those needing to differentiate their designs,” said G. Dan Hutcheson, chairman and CEO of VLSI Research. “Now with its new 12FDX offering, GLOBALFOUNDRIES is showing a clear commitment to delivering a roadmap for this technology — especially for IoT and Automotive, which are the most disruptive forces in the market today. GLOBALFOUNDRIES’ FD-SOI technologies will be a critical enabler of this disruption.”

“FD-SOI technology can provide real-time trade-offs in power, performance and cost for those needing to differentiate their designs,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ new 12FDX offering delivers the industry’s first FD-SOI roadmap that brings the lowest cost migration path for advanced node design, enabling tomorrow’s connected systems for Intelligent Clients, 5G, AR/VR, Automotive markets.”

GLOBALFOUNDRIES Fab 1 in Dresden, Germany is currently putting the conditions in place to enable the site’s 12FDX development activities and subsequent manufacturing. Customer product tape-outs are expected to begin in the first half of 2019.

“We are excited about the GLOBALFOUNDRIES 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

“NXP’s next generation of i.MX multimedia applications processors are leveraging the benefits of FD-SOI to achieve both leadership in power efficiency and scaling performance-on-demand for automotive, industrial and consumer applications,” said Ron Martino, vice president, i.MX applications processor product line at NXP Semiconductors. “GLOBALFOUNDRIES’ 12FDX technology is a great addition to the industry because it provides a next generation node for FD-SOI that will further extend planar device capability to deliver lower risk, wider dynamic range, and compelling cost-performance for smart, connected and secure systems of tomorrow.”

“As one of the first movers of design for FD-SOI, VeriSilicon leverages its Silicon Platform as a Service (SiPaaS) together with experience in delivering best-in-class IPs and design services for SoCs,” said Wayne Dai, president and CEO of VeriSilicon. “The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments. We look forward to extending our collaboration with GLOBALFOUNDRIES on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market.”

“12FDX development will deliver another breakthrough in power, performance, and intelligent scaling as 12nm is best for double patterning and delivers best system performance and power at the lowest process complexity,” said Marie Semeria, CEO of Leti, an institute of CEA Tech. “We are pleased to see the results of the collaboration between the Leti teams and GLOBALFOUNDRIES in the U.S. and Germany extending the roadmap for FD-SOI technology, which will become the best platform for full system on chip integration of connected devices.”

“We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering. Now this new 12FDX offering will further expand FD-SOI market adoption,” said Paul Boudre, Soitec CEO. “At Soitec, we are fully prepared to support GLOBALFOUNDRIES with high volumes, high quality FD-SOI substrates from 22nm to 12nm. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

GLOBALFOUNDRIES today announced a new partner program, called FDXcelerator, an ecosystem designed to facilitate 22FDX system-on-chip (SoC) design and reduce time-to-market for its customers.

With the recent announcement of the company’s next-generation 12FDX™ technology, the FDXcelerator Partner Program builds upon GLOBALFOUNDRIES industry-first FD-SOI roadmap, a lower cost migration path for customers desiring advanced node design.

Together with GLOBALFOUNDRIES and FDXcelerator Partner solutions, customers will be able to build innovative 22FDX SoC solutions as well as ease migration to FD-SOI from bulk nodes such as 40nm and 28nm. Initial FDXcelerator Partners have committed a set of key offerings to the program, including:

  •  tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features,
  •  a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements,
  • platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX,
  • reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market,
  • resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology, and;
  • product packaging and test (OSAT) solutions.

“22FDX is increasingly gaining momentum as the platform of choice to build differentiated, highly-integrated system solutions,” said Alain Mutricy, senior vice president of Product Management at GLOBALFOUNDRIES.  “Now is the time to step up industry collaboration to enable our customers to accelerate adoption of 22FDX. FDXcelerator will extend the reach of the FD-SOI ecosystem by creating a market place for truly innovative FDX-tailored solutions and services.”

The FDXcelerator Partner Program creates an open framework to allow selected Partners to integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.

FD-SOI technology has been gaining ground as designers leverage the process as an alternative to Fin-FET-based technologies for chips that require performance on demand and energy efficiency at the lowest solution cost. According to a recent Linley Group Microprocessor Report, FD-SOI Offers Alternative to FinFET, GLOBALFOUNDRIES’ FDX technologies provide an alternative path for applications that cannot accept the cost and complexity of FinFETs.

Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semiconductor (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services. Additional FDXcelerator members will be announced in the following months.

Last March, the artificial intelligence (AI) program AlphaGo beat Korean Go champion LEE Se-Dol at the Asian board game.

“The game was quite tight, but AlphaGo used 1200 CPUs and 56,000 watts per hour, while Lee used only 20 watts. If a hardware that mimics the human brain structure is developed, we can operate artificial intelligence with less power,” points out Professor YU Woo Jong.

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In collaboration with Sungkyunkwan University, researchers from the Center for Integrated Nanostructure Physics within the Institute for Basic Science (IBS), have devised a new memory device inspired by the neuron connections of the human brain. The research, published in Nature Communications, highlights the devise’s highly reliable performance, long retention time and endurance. Moreover, its stretchability and flexibility makes it a promising tool for the next-generation soft electronics attached to clothes or body.

The brain is able to learn and memorize thanks to a huge number of connections between neurons. The information you memorize is transmitted through synapses from one neuron to the next as an electro-chemical signal. Inspired by these connections, IBS scientists constructed a memory called two-terminal tunnelling random access memory (TRAM), where two electrodes, referred to as drain and source, resemble the two communicating neurons of the synapse. While mainstream mobile electronics, like digital cameras and mobile phones use the so-called three-terminal flash memory, the advantage of two-terminal memories like TRAM is that two-terminal memories do not need a thick and rigid oxide layer. “Flash memory is still more reliable and has better performance, but TRAM is more flexible and can be scalable,” explains Professor Yu.

TRAM is made up of a stack of one-atom-thick or a few atom-thick 2D crystal layers: One layer of the semiconductor molybdenum disulfide (MoS2) with two electrodes (drain and source), an insulating layer of hexagonal boron nitride (h-BN) and a graphene layer. In simple terms, memory is created (logical-0), read and erased (logical-1) by the flowing of charges through these layers. TRAM stores data by keeping electrons on its graphene layer. By applying different voltages between the electrodes, electrons flow from the drain to the graphene layer tunnelling through the insulating h-BN layer. The graphene layer becomes negatively charged and memory is written and stored and vice versa, when positive charges are introduced in the graphene layer, memory is erased.

IBS scientists carefully selected the thickness of the insulating h-BN layer as they found that a thickness of 7.5 nanometers allows the electrons to tunnel from the drain electrode to the graphene layer without leakages and without losing flexibility.

Flexibility and stretchability are indeed two key features of TRAM. When TRAM was fabricated on flexible plastic (PET) and stretachable silicone materials (PDMS), it could be strained up to 0.5% and 20%, respectively. In the future, TRAM can be useful to save data from flexible or wearable smartphones, eye cameras, smart surgical gloves, and body-attachable biomedical devices.

Last but not least, TRAM has better performance than other types of two-terminal memories known as phase-change random-access memory (PRAM) and resistive random-access memory (RRAM).