Category Archives: 3D Integration

SEMI announced today that the deadline for presenters to submit an abstract for the annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is October 17.  ASMC, which takes place May 15-18, 2017 in Saratoga Springs, New York, will feature technical presentations of more than 90+ peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, as well as educational tutorials.

ASMC, in its 28th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.  Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. In addition to publication in the ASMC proceedings, select papers will be invited to participate in a special section of ASMC 2017 to be featured in IEEE Transactions on Semiconductor Manufacturing. Technical abstracts are due October 17, 2016. 

This year SEMI (www.semi.org) is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:

  • Packaging and Through Silicon Via (3D/TSV)
  • Fabless Experience (FE)
  • Advanced Equipment Processes and Materials (AEPM)
  • Advanced Metrology
  • Advanced Patterning / Design for Manufacturability (AP/DFM)
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Defect Inspection and Reduction (DI)
  • Data Management and Data Mining Tools (DM)
  • Discrete Power Devices (DP)
  • Equipment Reliability and Productivity Enhancements (ER)
  • Enabling Technologies and Innovative Devices (ET/ID)
  • Factory Automation (FA)
  • Green Factory (GF)
  • Industrial Engineering (IE)
  • Lean Manufacturing (LM)
  • MOL and Junction Interfaces (MJ)
  • Smart Manufacturing (SM)
  • Yield Methodologies (YM)

Complete descriptions of each topic and author kit can be accessed at http://www.semi.org/en/node/38316.  If you would like to learn more about the conference and the selection process, please contact Margaret Kindling at [email protected] or call 1.202.393.5552.

Papers co-authored between device manufacturers, equipment or materials suppliers, and/or academic institutions that demonstrate innovative, practical solutions for advancing semiconductor manufacturing are highly encouraged.  To submit an abstract, click here.

Technical abstracts are due October 17, 2016.  To learn more about the SEMI Advanced Semiconductor Manufacturing Conference, visit http://www.semi.org/en/asmc2017.

Applying an electric field to some materials causes their atoms to “switch” their electric polarization from one direction to another, making one side of the material positive and the other negative. This switching property of “ferroelectric” materials allows them to be used in a wide range of applications. For example, ferroelectric capacitors are used to store binary bits of data in memory devices.

The newly synthesized crystal is ferroelectric above room temperature (a-b, e-f) and turns into "plastic phase", meaning highly deformable, at higher temperature (a to c). The electric polarity of each molecule can be aligned in one direction by applying electric field as it cools (c to e). Credit: Harada J. et al., July 11, 2016, Nature Chemistry, DOI: 10.1038/NCHEM.2567

The newly synthesized crystal is ferroelectric above room temperature (a-b, e-f) and turns into “plastic phase”, meaning highly deformable, at higher temperature (a to c). The electric polarity of each molecule can be aligned in one direction by applying electric field as it cools (c to e). Credit: Harada J. et al., July 11, 2016, Nature Chemistry, DOI: 10.1038/NCHEM.2567

Researchers at Japan’s Hokkaido University have developed a novel ferroelectric plastic crystal that could accelerate the development of more flexible, cost-efficient and less toxic ferroelectrics than those currently in use.

The crystal is ferroelectric above room temperature, then turns into a plastic, more pliable phase at higher temperatures. At the higher temperatures, the molecules in the crystal have randomly different polarity axes, but they can be aligned in one direction by applying an electric field as the crystal cools, bringing it back to a ferroelectric state.

Being able to control the polarity in this manner addresses a major challenge previously faced by researchers working with organic compound-based ferroelectric crystals. These are less symmetric than inorganic crystals, and can thus be polarized only in one direction leading to a very weak overall polarization of randomly oriented crystals.

A distinct advantage of this particular crystal is its transition to a plastic state when heat is applied. This plasticity – as opposed to fracturing that occurs in regular organic and inorganic crystals when a mechanical stress is applied – makes it extremely advantageous for use as a thin ferroelectric film in devices, such as non-volatile ferroelectric random-access memory devices, which maintain memory when the power is turned off.

Exploring crystals composed of molecules similar to quinuclidine could lead to the discovery of more ferroelectric crystals, write the researchers in their paper published in the journal Nature Chemistry. Chemical modifications of the molecules’ constituent ions could also improve their performance, the researchers add.

Littelfuse, Inc., (NASDAQ:LFUS) today announced it has entered into definitive agreements to acquire the product portfolio of transient voltage suppression (“TVS”) diodes, switching thyristors and insulated gate bipolar transistors (“IGBT”) for automotive ignition applications from ON Semiconductor Corporation for a combined purchase price of $104 million. This portfolio has annualized sales of approximately $55 million. The transactions are expected to close in late August, 2016.

“The acquisition of this portfolio aligns with our strategy to expand in power semiconductor applications as well as increase our presence in the automotive electronics market,” said Ian Highley, senior vice president and general manager, semiconductor products and chief technology officer for Littelfuse. “These products have strong synergies with our existing circuit protection business, will strengthen our channel partnerships and customer engagement, and expand our power semiconductor portfolio.”

Littelfuse also plans to invest approximately $30 million in its semiconductor fabrication locations to enhance its production capabilities, add significant capacity to its China fabrication facility and transfer the production of the acquired portfolio. The transfers will occur over the next few years, as the company works with customers on their timing and requirements. The expected productivity gains from this investment will drive long term profitable growth across the company’s semiconductor business.

“Once we complete the transfer of these products, we expect this acquisition to have EBITDA margins of more than 30 percent,” added Meenal Sethna, executive vice president and chief financial officer. “Including amortization, interest and integration expenses, we expect the earnings per diluted share impact of this acquisition to be neutral in 2016, and accretive in 2017 and beyond.”

2016 is a turning point for the Fan-Out market since both leaders, Apple and TSMC, changed the game and may create a trend of acceptance of Fan-Out packages. Yole Développement (Yole) is analyzing the current market and technologies trends and offers you to discover these results within a new report entitled Fan-Out: Technologies & Market Trends 2016.

fowlp_history_yole_aug2016_280x433

TSMC investment in FO WLP and development of InFO changed the WLP landscape. Following high volume adoption of InFO and further development of eWLB technology, a wave of new players and FO WLP technologies may enter the market. TSMC’s FO WLP solution called InFO will be used to package the Apple A10 application processor, implemented in the new iPhone 7 series. The success of FO packaging platforms is so undeniable today. What will be the status of the market tomorrow? What are the next steps of the leading FO players? Which technology will be the winning solutions? Yole’s analysts tell the story.

“Production starts in 2016 and represents a big change in the Fan-Out industry for several reasons”, confirms Jérôme Azémar, Market & Technology Analyst, Advanced Packaging & Manufacturing at Yole. And he explains:

  • First of all, in terms of volume, capturing the Apple processor market is a big asset for Fan-Out technology. iPhone 7 phones are expected to be sold in more than 200 million units.
  • In terms of technology capability it is also a major turn: processors require thousands of connections while the FO market was essentially focused on limited IO count applications so far.
  • Eventually, the potential for market spread is very high: the Apple brand brings more interest to the FO platform.

According to Yole’s advanced packaging & semiconductor manufacturing team, the market will actually be split in two types:

  • The “core” market of FO, including single die applications such as Baseband, Power management, RF transceivers, etc. This is the main pool for FO WLP solutions and will keep growing.
  • The “high-density” FO market, started by Apple APE that will include larger IO count applications such as processors, memories, etc. This market is more uncertain and will require new integration solutions and high performing FO packages but has a very high potential.

Apart from TSMC, STATS ChipPAC is willing to make further investments powered by JCET, ASE extends its partnership with Deca Technologies while Amkor, SPIL and Powertech are in development phase eyeing future production. Samsung is seemingly lagging behind and is considering its options to raise competitiveness. “With such a high potential for the high-density FO and solid growth of the core FO, the supply chain is also expected to evolve with a considerable amount of investment in Fan-Out packaging capabilities,” said Jérôme Azemar from Yole. Several players are already offering FO WLP while many others are developing their competitive Fan-Out platforms to enter the Fan-Out landscape and enlarge their portfolio.

What are the next steps of the leading Fan-Out players? Yole’s FO report analyzes in detail the strategies and offers of main players involved. It describes potential success scenarios for all of them. It also helps to define what FO Packaging is and what are the different products and platforms, player per player.

IC Insights released its August Update to the 2016 McClean Report earlier this month.  This Update included an update of the semiconductor industry capital spending forecast, a look at the top-25 semiconductor suppliers for 1H16, including a forecast for the full year ranking, and Part 1 of an extensive analysis of the IC foundry industry (the ranking of the top-10 pure-play foundries is covered in this research bulletin).

In 2014, the pure-play IC foundry market registered a strong 17% increase, the largest increase since 2010 and eight points greater than the 9% increase in the worldwide IC market.  In 2015, the pure-play foundry market showed a 6% increase, about one-third the rate of growth in the previous year, but seven points higher than the total IC market growth rate of -1%.  For 2016, the pure-play foundry market is expected to increase by 9% and greatly outperform the growth rate of total IC market, which is forecast to drop by 2% this year.

Figure 1 shows that the top 10 pure-play foundries are expected to hold 95% of the total pure-play foundry market this year.  This year, the “Big 4” pure-play foundries (i.e., TSMC, GlobalFoundries, UMC, and SMIC) are forecast to hold an imposing 84% share of the total worldwide pure-play IC foundry market.  As shown, TSMC is expected to hold a 58% marketshare in 2016, down one point from 2015, as its sales are forecast to increase by $2.1 billion this year, up from a $1.5 billion increase in 2015.  GlobalFoundries, UMC, and SMIC’s combined share is expected to be 26% this year, the same as in 2015.

The two top-10 pure-play foundry companies that are forecast to display the highest growth rates this year are Israel-based TowerJazz, which is expected to edge-out Powerchip for the 5th spot in the pure-play foundry ranking in 2016, and China-based SMIC, with 30% and 27% sales increases, respectively. TowerJazz and SMIC have been on a very strong growth curve over the past few years.  TowerJazz is expected to grow from $505 million in sales in 2013 to $1,245 million in 2016 (a 35% CAGR) while SMIC is forecast to more than double its revenue from 2011 ($1,220 million) to 2016 ($2,850 million) and register a 19% CAGR over this five-year timeperiod.

Figure 1

Figure 1

Eight of the top-10 pure-play foundries listed in Figure 1 are based in the Asia-Pacific region.  Israel-based TowerJazz, and U.S.-headquartered GlobalFoundries are the only non-Asia-Pacific companies in the top-10 group.  While LFoundry is currently headquartered in Avezzano, Italy, China-based SMIC agreed in 2Q16 to purchase 70% of the company for approximately $55 million.  Since LFoundry has an installed capacity of 40K 200mm wafers/month, the acquisition of a controlling interest in the company essentially serves to immediately expand SMIC’s capacity by 13% this year.

Although SMIC is forecast to register strong sales growth of 27% this year, Chinese foundries, in total, are expected to hold only 8.2% of the pure-play foundry market in 2016, down 5.1 points from the peak share of 13.3% reached in 2006 and 2007.  IC Insights believes that the total Chinese company share of the pure-play foundry market will increase through 2020, as the China-based foundries take advantage of the huge amount of government and private investment that will be flowing into the Chinese semiconductor market infrastructure over the next five years.

Researchers at Queen’s University Belfast and ETH Zurich, Switzerland, have created a new theoretical framework which could help physicists and device engineers design better optoelectronics, leading to less heat generation and power consumption in electronic devices which source, detect, and control light.

Speaking about the research, which enables scientists and engineers to quantify how transparent a 2D material is to an electrostatic field, Dr. Elton Santos from the Atomistic Simulation Research Centre at Queen’s, said: “In our paper we have developed a theoretical framework that predicts and quantifies the degree of ‘transparency’ up to the limit of one-atom-thick, 2D materials, to an electrostatic field.

“Imagine we can change the transparency of a material just using an electric bias, e.g. get darker or brighter at will. What kind of implications would this have, for instance, in mobile phone technologies? This was the first question we asked ourselves. We realised that this would allow the microscopic control over the distribution of charged carriers in a bulk semiconductor (e.g. traditional Si microchips) in a nonlinear manner. This will help physicists and device engineers to design better quantum capacitors, an array of subatomic power storage components capable to keep high energy densities, for instance, in batteries, and vertical transistors, leading to next-generation optoelectronics with lower power consumption and dissipation of heat (cold devices), and better performance. In other words, smarter smart phones.”

Explaining how the theory could have important implications for future work in the area, Dr. Santos added: “Our current model simply considers an interface formed between a layer of 2D material and a bulk semiconductor. In principle, our approach can be readily extended to a stack of multiple 2D materials, or namely, van der Waals heterostructures recently fabricated. This will allow us to design and predict the behaviour of these cutting-edge devices in prior to actual fabrication, which will significantly facilitate developments for a variety of applications. We will have an in silico search for the right combination of different 2D crystals while reducing the need for expensive lab work and test trials.”

SEMI announced today that over 43,000 visitors are expected to attend SEMICON Taiwan September 7-9 at the TWTC Nangang Exhibition Hall in Taipei. Over 550 exhibitors, 16 themed pavilions, and more than 20 international forums are being readied to connect attendees with companies, people, products, and information forming the future of advanced electronics, including a major focus on advanced packaging.

Douglas Yu, senior director of Integrated Interconnect and Packaging Technology at TSMC, recently announced that TSMC needs to transition – from the world’s leading IC foundry – to the industry’s first System in Package (SiP) foundry (SEMICON West; July 2016).  Yu stated, “We are a wafer foundry, but we are doing some packaging business to survive and grow . . . Moore’s law is becoming more challenging, so we are preparing for those days.”  Sources say that TSMC’s chip packaging changes have led to improvements of 20 percent in both speed and packaging thickness and 10 percent in thermal performance.

SEMICON Taiwan is an exceptional event to learn about the latest advances in packaging. On September 7, the SEMI Advanced Packaging Technology Symposium‘s theme is “Fan Out Solutions – Cost-effective FO Solutions, 3D/SiP FO Solutions, and Fine Patterning.” Industry experts from a wide range of companies will present, including: Amkor, APIC Yamada, ASE, ASM, IEK, Kulicke & Soffa, Lam Research, Protec, Senju, SPTS, SUSS MicroTec Photonic Systems, and Ueno SEIKI.

On September 8, SEMICON Taiwan’s SiP Global Summit begins with a 2.5/3D-IC Technology Forum with presentations from TSMC, Amkor, ANSYS, ASE Group, EVG, Fraunhofer IZM, Hitachi Chemical, IBM, IMEC, NMC, and SPIL.  On September 9, the SiP Summit features an Embedded and Wafer Level Package Technology Forum, with moderators from ASM Pacific Technology, ITRI, and SPIL.

Beyond packaging, many other innovation areas such as Smart Manufacturing, Semiconductor Materials and Executive Summit –Grand Opening Keynote session which always draws the most attention will be presented in technical and business programs, as well as on the show floor at the TechXPOTs, including:

  • High-Tech Facility TechXPOT: AccuDevice, Forbo Flooring, Hantech Engineering, Lumax International, Organo Technology, Particle Measuring, Rockwell Automation, Supenergy, Techgo Industrial, Trusval Technology, VIVOTEK, Wholetech Systems Hitech, and many more
  • Materials TechXPOT: AI Technology, Atotech Taiwan, CohPros International, CSI Chemical, Nippon Pulse Motor Trading (Taiwan), Tatsuta Electric Wire & Cable, and Uniwave Enterprise
  • New Product Launch TechXPOT: AblePrint Technology, Chemleader, Creating Nano Technologies, EVG-Jointech, First Elite Enterprise, SEIPI, Sigmatek, Sil-More Industrial, and YXLON/Teltec Semiconductor Pacific
  • Smart Manufacturing TechXPOT: Balluff Taiwan, Cimetrix, Dah Hsing Electric, and Gallant Precision Machining

For more information and registration for SEMICON Taiwan, please visit: www.semicontaiwan.org/en

Reno Sub-Systems, a developer of high-performance radio frequency (RF) matching networks, RF power generators and gas flow management systems for semiconductor manufacturing, today announced that it has secured its first platform design win for its Electronically Variable Capacitor (EVC) matching network. The order comes from a tier-one equipment manufacturer and will be installed as the default standard on its etch systems in a leading global semiconductor manufacturer’s high-volume production facility. Reno secured the design win following successful beta testing with the end customer.

Leading semiconductor manufacturers are driving semiconductor OEMs to improve film characteristics and process consistency between chambers and systems. These challenges are becoming greater as technology nodes shrink and move to multiple patterning, finFET logic gates, 3D NAND and through silicon via (TSV) devices.

“Our EVC matching network was specifically designed to address the most challenging plasma-related deposition and etch processes,” said Bob MacKnight, CEO of Reno Sub-Systems. “Microsecond RF tuning is essential for 14nm and below high volume manufacturing.”

The new, disruptive EVC technology enables unprecedented RF matching speeds not possible with vacuum variable capacitors (VVCs), which is the current industry standard. Reno’s patented EVC technology facilitates the speed, accuracy and plasma stability unachievable by RF matches being used for etch and deposition processes today.This run-to-run repeatable and accurate Instantaneous Match technology enables the precise, high-aspect ratio, selectively anisotropic sharp-edge plasma processing required for next-generation devices, including 3D structures.

“We recently completed our Series B round of funding to ramp to high-volume manufacturing,” said MacKnight. “Having received our first major production order validates our technology and we are proud to be shipping in volume.”

New wafer processing technologies overcome FOWLP’s technical hurdles, paving the way for a new generation of ultra compact, high I/O electronic devices.

BY DAVID BUTLER, SPTS Technologies, an Orbotech company, Hereford, UK

Our ability to create ever-smaller electronic devices that maintain or surpass the performance of their physically larger predecessors – exemplified by today’s wearables, smartphones and tablets – is dictated by many factors that extend well beyond Moore’s Law, from the underlying embedded components to the ways in which they’re packaged together. With regard to the latter, fan-out wafer level packaging (FOWLP) is quickly emerging as the new die and wafer level packaging technique of choice, and is widely antici- pated to underpin the next generation of compact, high performance electronic devices.

Whereas with conventional flip-chip WLP schemes the I/O terminals are spread over the chip surface area, limiting the number of I/O connections, FOWLP embeds individual die in an epoxy mold compound (EMC) with space allocated between each die for additional I/O connection points, avoiding the use of more expensive silicon real estate to accommodate a higher I/O count. Redistribution layers (RDLs) are formed using physical vapor deposition (PVD) and subsequent electroplating and patterning to re-route I/O connections on the die to the mold compound regions on the periphery (FIGURE 1).

FIGURE 1. FOWLP process flow.

FIGURE 1. FOWLP process flow.

Leveraging FOWLP, semiconductor devices with thousands of I/O points can be seamlessly connected via finely-spaced lines as thin as two to five microns, maximizing interconnect density while enabling high bandwidth data transfer. Significant height and cost savings are achieved via the elimination of the substrate.

With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers and power management ICs in these mold wafers, thereby enabling the latest gener- ation of ultra-thin wearables and mobile wireless devices. With continued line and space reductions, FOWLP has the potential to accommodate higher performing devices including memory and application processors, positioning FOWLP to extend into new markets including automotive and medical applications and beyond.

Leading vendors implementing FOWLP today include Amkor, ASE, Freescale, NANIUM, STATS ChipPAC, and TSMC, with TSMC being the most high-profile vendor given its widely-reported contract win to produce A10 processors for Apple’s iPhone 7 – a deal said to be attrib- utable in part to TSMC’s mature FOWLP-based InFO technology.

According to a report entitled “FO WLP Forecast update 09/2015” published by research firm Yole Développement in September 2015, the launch of TSMC’s InFO format is expected to increase industry packaging revenues for FOWLP from $240M in 2015 to $2.4B in 2020. With a projected 54% CAGR, Yole expects FOWLP to be the fastest growing advanced packaging technology in the semiconductor industry.

Low heat, high speed processing

All fan-out wafers feature singulated die embedded in the EMC, with spin-on dielectrics surrounding the RDL. These materials present some unique challenges, including moisture absorption, excessive outgassing and a limited tolerance to elevated temperatures. If not dealt with properly, contamination at the metal deposition stage can compromise contact resistance.

Whereas conventional circuits built on silicon can withstand heat up to 400oC and can be degassed in under one minute, the EMC and dielectrics used in FOWLP have a heat tolerance closer to 120oC. Temperatures exceeding this low threshold can cause decompo- sition and excessive wafer warping. Degassing wafers at such low temperatures naturally takes a longer amount of time, and can drastically reduce the throughput of a conventional sputter system.

Multi-wafer degas (MWD) technology has emerged as a compelling solution to this problem, enabling up to 75 wafers to be degassed at 120oC in parallel before being individually transferred to subsequent pre-clean and sputter deposition, without breaking vacuum.

With this approach, wafers are dynamically pumped under clean, high vacuum conditions, with radiation heat transfer warming wafers directly to temperatures within the operating budget for packaging applications.

Each wafer can spend up to 30 minutes inside the MWD, but because they’re processed in parallel, a “dry” wafer is outputted for metal deposition every 60 to 90 seconds, at a rate of between 30 to 50 wafers per hour. This approach increases PVD system throughput by 2-3 times compared to a single wafer degas processing technology, and as materials emerge with even lower thermal budgets based on increased passivation thickness, longer degas times can be accommodated with no impact on throughput (FIGURE 2).

FIGURE 2. The Sigma fxP PVD system with multi-wafer degas module from Orbotech-SPTS.

FIGURE 2. The Sigma fxP PVD system with multi-wafer degas module from Orbotech-SPTS.

These benefits are not readily attainable, however, unless we can overcome the attendant warping challenges. Epoxy mold wafers can be warped after curing, and the size and shape of the warpage hinge on the different shapes, densities and placement of the embedded die. A FOWLP PVD system must therefore be able to minimize temperature-induced shape shifting, and accommodate wafers with up to a 10mm bow. The acceptable industry threshold for bowing is probably lower than 6mm, however, as it’s not easy to make uniformly thick conductors on a substrate exhibiting 6mm+ warpage.

Utmost integrity

After successful degas, but prior to metal deposition, the FO wafer is pre-cleaned in a plasma etch module. This facilitates the removal of trace oxide layers from the contacts, but due to the composition of the organic dielectric surrounding the contacts, will result in carbon build-upon the chamberwalls.This carbon does not adhere well to ceramic chamber surfaces, and if not carefully managed, can result in early particle failure.

New in-situ paste technologies allow these carbon deposits to better adhere to chamber surfaces during the pre-cleaning process, enabling preventative maintenance intervals that exceed 6,000 wafers. This approach can significantly improve productivity by reducing the frequency of dedicated wafer pastes, which typically require production to be paused every 10 to 20 wafers for chamber pasting when using conventional techniques.

The myriad benefits that FOWLP promises for the production of ultra compact, high I/O electronic devices far outweigh the aforementioned technical barriers to mainstream FOWLP adoption. With the ability to overcome the degassing, warping, and integrity challenges that can impede FOWLP implementations, electronics manufacturers can unlock the full potential of FOWLP while eliminating frictions affecting production speeds and yields.

BY DR. ZHIHONG LIU, Chairman and CEO, ProPlus Design Solutions

Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.

The success of the foundry-fabless business model over the past 20 years has been one of the main drivers of the booming of semiconductor industry. The cooperation between foundries and IC designs in fabless companies for process development worked so well that process engineers and circuit designers only needed to focus on their area of expertise. EDA flows simplified the interaction by using process design kits (PDKs) as the information carrier for circuit designs and sent tapeout databases (GDSII) back to the foundry for chip fabrication. Most designers didn’t need to dig into the process.

That was then. The designer now is forced to understand process and devices when moving to smaller nodes in order to achieve more competitive designs. Because process is the least understood, the loose link between process and design should be enhanced to improve design and tapeout confidence.

Knowing processes and devices would help designers make better use of the process platform and improve designs. Device geometries are getting smaller and new structures such as FinFET and FD-SOI are becoming mainstream leading to complicated device characteristics and SPICE models, the most critical components in the PDK. They represent a process platform’s performance and device characteristics, fundamental to good circuit design. A solid understanding of SPICE models becomes necessary to make full use of the process. This is true not only for designs at advanced nodes at 28nm beyond, such as 16nm, 14nm and10nm, but critical for some refreshed older technologies for IoT/Wearable applications.

Running a full evaluation of process and device performance would provide guidance to better select device types, optimize device sizes and bias conditions, trade-off circuit speed and power. The same logic can be applied to generic circuit designs at any technology node, such as analog
designs at 180nm or above.

This practice is used mostly within IDMs where process and design teams have fairly direct channels to work cooperatively. Recently, fabless companies strengthened links with foundries to under- stand the process and devices to improve design output or for process-circuit co-design for high-end chip designs with more aggressive speed, power and performance specifications.

These efforts are significant. Most companies don’t have the resources and time to build a dedicated team and flow and there have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions. Increasing time-to-market pressures and tough competition drive the need to a higher priority.

Without an EDA tool, current practices can easily take weeks or months to build, maintain and run a flow by creating scripts or SPICE netlists for different evaluation items. It’s practically impossible to run through the cases to generate a full picture of process platform for designers within a short turnaround time.

As a result, it’s hard to come up with a set standard for process evaluation before using it in design, as efforts can vary for different projects. For a big corporation with many design projects, dealing with multiple foundries, using multiple technology nodes and different process platforms, this type of work is critical to its success however becomes overloaded.

Furthermore, the complexity of SPICE models is exploding. Thousands of parameters in each model and a huge model library file with more than 100K lines of code are quite common. Macro models with complicated layout- dependent effects and random variations add more dimensions of complexity.

Complexity and time pressures are huge. An EDA tool to manage both would be indispensable.

One tool could use the PDK library as the input to explore, compare and verify models. It could help designers under- stand and explore the process-design space to guide process platform selection and enable quick adoption of the process and assist designs. It would help designers dig into the process from different angles, including a high-level summary of the process and device performance, device characteristics, statistical behavior and circuit performance related to the application. This should enable designers quickly adopt and make full use of a process platform that suits their needs.