Category Archives: 3D Integration

Mentor Graphics Corporation (NASDAQ:  MENT) today announced the first phase of the new Xpedition printed circuit design (PCB) flow to address the increasing complexity of today’s advanced systems designs. The increasing densities of electronics products are forcing companies to develop highly compact system designs with more functionality, and at lower costs. To efficiently manage the density and performance requirements for advanced PCB systems, the new Xpedition flow provides advanced technologies to enable design and verification of 3D rigid-flex structures, and to automate layout of high-speed topologies with advanced constraints.

“Our customers are industry leaders developing the world’s most advanced electronics systems. They require access to technologies that enable deployment of advanced technologies and techniques, from design for high performance, advanced packaging, growth of rigid-flex, and higher speeds and densities,” said AJ Incorvaia, vice president and general manager, Mentor Graphics Board Systems Division. “To deliver the latest Xpedition Enter­prise flow, we have partnered with our customers to address their strategic initiatives to manage increasing complexity, increase organizational collaboration, drive greater end-product quality, and facilitate enterprise IP management.”

Managing advanced rigid flex design complexity

Flex and rigid-flex PCBs are now found in all types of electronics products, from small consumer devices to aerospace, defense and automotive electronics where high reliability and safety are critical. The Xpedition rigid-flex technology enables a streamlined design process from initial stack-up creation through manufacturing.

Engineers can design complex rigid and flex PCBs in a fully supported 3D environment (3D design and verification—not just a 3D view), resulting in a correct-by-construction methodology for optimum reliability and product quality. 3D verification ensures that bends are in the right position, and elements on the board do not interfere with folding; this can be reviewed early in the design stage to prevent costly redesigns. Users can then export a 3D solid model to MCAD for efficient bi-directional PCB-enclosure co-design.

Integration with Mentor’s leading HyperLynx high-speed analysis technology enables optimization of signal and power integrity across complex rigid-flex stack-up structures. For fabrication preparation, the Xpedition flow provides all flex and rigid information using the ODB++ common data format. This methodology eliminates data ambiguities by clearly communicating the finished board intent to the fabricator. The new Xpedition flow is the optimum solution designed specifically for flex and rigid-flex design, from conception through fabrication output.

“Mentor’s new Xpedition flow provides multiple board outlines, stack-ups, and bend areas which allow us to define a rigid flex within the design environment, and export a folded 3D step model for efficient mechanical design integration,” stated Charles Ietswaard, PCB design engineer at NIKHEF, the national institute for sub-atomic physics in The Netherlands. “The automated rigid-flex capabilities in Xpedition help us manage the growing complexities of today’s advanced PCB systems with ease, higher productivity and overall product reliability.”

Samsung Electronics Co., Ltd. this week introduced a blueprint for next-generation flash memory solutions that will meet the ever-increasing demands of big data networks, cloud computing and real-time analysis.

Samsung 32TB SAS SSD - world's largest capacity drive (Photo: Business Wire)

Samsung 32TB SAS SSD – world’s largest capacity drive (Photo: Business Wire)

At Flash Memory Summit 2016, held in the Santa Clara (CA) Convention Center, Samsung showcased its 4th generation Vertical NAND (V-NAND) and a line-up of high-performance, high-capacity solid state drives (SSDs) available for its enterprise customers as well as Z-SSD, a new solution providing breakthrough performance for flash-based storage.

Samsung’s new flash storage devices are expected to contribute significantly to the global IT industry in meeting the growing storage requirements of today’s enterprise computing environment. These solutions will accommodate enormous amounts of data, and extremely high-speed information processing, while enhancing the total cost of ownership (TCO) for data centers.

“With our 4th generation V-NAND technology, we can provide leading-edge differentiated values in high-capacity, high-performance and compact product dimensions, which together will contribute to our customers achieving better TCO results,” said Young-Hyun Jun, President of the Memory Business at Samsung Electronics. “We will continue to introduce more advanced V-NAND solutions and expand our flash business initiatives in maximizing an unbeatable combination of performance and value.”

Samsung’s 4th Generation V-NAND stacks 30 percent more layers of cell-arrays than its predecessor

Samsung introduced its 4th generation, 64-layer triple-level-cell V-NAND flash memory that pushes the envelope of NAND scaling, performance and storage capacity. Stacking 64 layers of cell-arrays, the new V-NAND can increase its single-die density to an industry-leading 512Gb and its IO speed to 800Mbps. Starting in August 2013, Samsung has previously introduced three generations of “industry-first” V-NAND products with 24, 32 and 48-layer vertical cell-array stacking technologies.

Samsung plans to provide the world’s first 4th generation V-NAND flash memory products in the fourth quarter of this year, which will help manufacturers to produce faster, more stylish and portable computing devices, while offering consumers a more responsive computing environment.

World’s largest capacity drive − 32TB SAS SSD − for enterprise storage systems

Samsung’s latest Serial Attached SCSI (SAS) SSD is the world’s largest single drive ever introduced to the industry based on 512-gigabit (Gb) V-NAND chips. A total of 512 V-NAND chips are stacked in 16 layers to form a 1-terabyte (TB) package and the 32-terabyte (TB) SSD contains 32 of those packages.

By adopting a new 4th generation V-NAND design, the 32TB SAS SSD can reduce system space requirements up to 40 times compared with the same type of system using two racks of hard disk drives (HDDs). The 32TB SAS SSD will come in a 2-5-inch form factor and be produced in 2017. Samsung also expects that SSDs with more than 100TB of storage capacity will be available by 2020, thanks to continued refinement of V-NAND technology.

1TB memory in a single BGA package

The Samsung 1TB BGA SSD features an extremely compact, ball grid array (BGA) package design that contains all essential SSD components including triple-level-cell V-NAND flash chips, LPDDR4 mobile DRAM and a state-of-the-art Samsung controller.

It will deliver unprecedented performance, reading sequentially at 1,500MB/s and writing sequentially at 900MB/s. By reducing its size up to 50 percent compared to its predecessor, the SSD weighs only about one gram (less than half the weight of a U.S. dime), making it ideal for ultra-compact next generation notebooks, tablets and convertibles.

Next year, Samsung plans to launch its 1TB BGA SSD by adopting a high-density packaging technology called “FO-PLP (Fan-out Panel Level Packaging)” which Samsung Electronics developed with Samsung Electro-Mechanics.

New ‘Z-SSD’ breaks through performance limits of current NAND flash memory storage

Samsung has also developed a high-performance, ultra-low latency SSD solution, the Z-SSD. Samsung’s Z-SSD shares the fundamental structure of V-NAND and has a unique circuit design and controller that can maximize performance, with four times faster latency and 1.6 times better sequential reading than the Samsung PM963 NVMe SSD.

The Z-SSD will be used in systems that deal with extremely intensive real-time analysis as well as extending high performance to all types of workloads. It is expected to be released next year.

ChipMOS TECHNOLOGIES (Bermuda) LTD. (Nasdaq:  IMOS), a provider of outsourced semiconductor assembly and test services, today announced that its shareholders have approved the merger of ChipMOS with and into ChipMOS TECHNOLOGIES INC. (Taiwan Stock Exchange: 8150), a company limited by shares incorporated under the laws of the Republic of China and a 58.3% directly owned subsidiary of ChipMOS as of January 21, 2016, with ChipMOS Taiwan being the surviving company after the Merger at ChipMOS’s annual general meeting of shareholders (the “Annual General Meeting”) held today.  It was announced that 83.41% of the outstanding shares ChipMOS were voted in favor of the Merger (1.03% of the outstanding shares of ChipMOS were voted against the Merger, 0.44% abstained, and 15.12% did not vote).  In addition, 83.66% of the outstanding shares ChipMOS Taiwan were voted in favor of the Merger at the ChipMOS Taiwan Extraordinary General Meeting, which was also held today (0.0% of the outstanding shares of ChipMOS were voted against the Merger, 5.84% abstained, and 10.50% did not vote). Both ChipMOS and ChipMOS Taiwan expect to close the Merger by October 31, 2016.

In connection with the Merger, the Annual General Meeting has also approved (i) the Agreement and Plan of Merger dated January 21, 2016 (the “Merger Agreement”) by and between ChipMOS and ChipMOS Taiwan and the transactions contemplated therein, (ii) the statutory merger agreement between ChipMOS and ChipMOS Taiwan (the “Bermuda Merger Agreement”) and the transactions contemplated therein and (iii) ChipMOS’s adoption of the Merger Agreement and the Bermuda Merger Agreement, and has authorized any one or more of the directors of ChipMOS to execute and deliver documents on his behalf and on behalf of ChipMOS in connection with, and to do all things necessary to give effect to, the Merger, the Merger Agreement, the Bermuda Merger Agreement and the matters contemplated thereby.

All other proposals at the Annual General Meeting were approved by the ChipMOS shareholders, including the re-election to the Board of Directors of ChipMOS (the “Board”) of Messrs. John Yee Woon Seto, Chao-Jung Tsai and Rong Hsu, as directors for three-year terms; and the re-appointment of PricewaterhouseCoopers, Taiwan, as the independent auditors of ChipMOS, to hold office until the close of the next annual general meeting, and the authorization of the Board to determine their remuneration.

S.J. Cheng, Chairman and Chief Executive Officer of ChipMOS and ChipMOS Taiwan, commented, “Today’s overwhelmingly positive vote is a strong endorsement of the strategic rationale and potential cost savings to the Company. We are very excited to be near the end of our multi-year corporate streamlining process. We will now work to secure the two approvals required in Taiwan, as we have already received necessary approvals by the U.S. Securities and Exchange Commission and Bermuda authorities. Our goal is to now finalize the merger on an accelerated schedule by October 31, 2016. Importantly, we will be moving forward as a unified, more efficient company with diverse and compelling near and longer term growth opportunities.”

POET Technologies Inc. (OTCQX:POETF) (TSX Venture:PTK), a developer of opto-electronics fabrication processes for the semiconductor industry, today announced that it has taken one more significant step toward its goal of developing a fully integrated commercial opto-electronic technology platform.

The milestone achieved is the first demonstration of functional Hetero-junction Field Effect Transistors (HFETs) down to 250nm effective gate lengths on the same proprietary epitaxy and utilizing the same integrated process sequence that was previously used to demonstrate high performance detectors. This milestone is the latest in POET’s initiative to integrate a detector, HFET and laser together into a single chip, the three key components of an active optical cable, a current market target for POET.

“Two of the three critical individual pieces of an integrated opto-electronic product are now in place and undergoing their respective optimization cycles,” said Dr. Subhash Deshmukh, POET’s Chief Operating Officer.  “As reported earlier, we have encountered delays in completing the VCSEL milestone.  The VCSEL continues to be our focus, even while we simultaneously make progress on other aspects of the technology.  The characterization that has been done to date on the VCSEL points to required optimization of a few layers in a very complex and unique epitaxial stack and fine tuning of the resonant cavity mode. The new and optimized epitaxial structure is expected to be delivered to the foundry for processing over the next couple of months,” said Dr. Deshmukh.  “We have not uncovered any fundamental show-stoppers.  We are charting new territory here and as pointed out at the recent town hall meeting and at the annual meeting of shareholders, technical issues are commonly encountered throughout the R&D process and we are systematically understanding and addressing these issues.”

POET has already demonstrated electrical functionality of the VCSEL with desired thyristor characteristics and demonstrated lasing modes through optical pumping of the VCSEL cavity (in other words light emission was detected on the epitaxial wafer surface).  However in order to enable electrical pumping of the VCSEL, the team has had to redesign some aspects of the epitaxial stack. VCSEL functionality was previously verified in a lab setting and the functionality of that original laser has been retested and reconfirmed.

“POET management is delighted to report this new achievement and reaffirms their confidence in the roadmap and progress in the lab to fab to commercialization of monolithic opto-electronic products. We will provide the next update around the earnings call, which we intend to schedule for early Q4 2016,” said Dr. Suresh Venkatesan.

Researchers from Moscow Institute of Physics and Technology (MIPT), Skolkovo Institute of Science and Technology (Skoltech), the Technological Institute for Superhard and Novel Carbon Materials (TISNCM), the National University of Science and Technology MISiS (Russia), and Rice University (USA) used computer simulations to find how thin a slab of salt has to be in order for it to break up into graphene-like layers. Based on the computer simulation, they derived the equation for the number of layers in a crystal that will produce ultrathin films with applications in nanoelectronics. Their findings were in The Journal of Physical Chemistry Letters (which has an impact factor of 8.54).

Transition from a cubic arrangement into several hexagonal layers. Credit: Authors of the study

Transition from a cubic arrangement into several hexagonal layers. Credit:
Authors of the study

From 3D to 2D

Unique monoatomic thickness of graphene makes it an attractive and useful material. Its crystal lattice resembles a honeycombs, as the bonds between the constituent atoms form regular hexagons. Graphene is a single layer of a three-dimensional graphite crystal and its properties (as well as properties of any 2D crystal) are radically different from its 3D counterpart. Since the discovery of graphene, a large amount of research has been directed at new two-dimensional materials with intriguing properties. Ultrathin films have unusual properties that might be useful for applications such as nano- and microelectronics.

Previous theoretical studies suggested that films with a cubic structure and ionic bonding could spontaneously convert to a layered hexagonal graphitic structure in what is known as graphitisation. For some substances, this conversion has been experimentally observed. It was predicted that rock salt NaCl can be one of the compounds with graphitisation tendencies. Graphitisation of cubic compounds could produce new and promising structures for applications in nanoelectronics. However, no theory has been developed that would account for this process in the case of an arbitrary cubic compound and make predictions about its conversion into graphene-like salt layers.

For graphitisation to occur, the crystal layers need to be reduced along the main diagonal of the cubic structure. This will result in one crystal surface being made of sodium ions Na? and the other of chloride ions Cl?. It is important to note that positive and negative ions (i.e. Na? and Cl?)–and not neutral atoms–occupy the lattice points of the structure. This generates charges of opposite signs on the two surfaces. As long as the surfaces are remote from each other, all charges cancel out, and the salt slab shows a preference for a cubic structure. However, if the film is made sufficiently thin, this gives rise to a large dipole moment due to the opposite charges of the two crystal surfaces. The structure seeks to get rid of the dipole moment, which increases the energy of the system. To make the surfaces charge-neutral, the crystal undergoes a rearrangement of atoms.

Experiment vs model

To study how graphitisation tendencies vary depending on the compound, the researchers examined 16 binary compounds with the general formula AB, where A stands for one of the four alkali metals lithium Li, sodium Na, potassium K, and rubidium Rb. These are highly reactive elements found in Group 1 of the periodic table. The B in the formula stands for any of the four halogens fluorine F, chlorine Cl, bromine Br, and iodine I. These elements are in Group 17 of the periodic table and readily react with alkali metals.

All compounds in this study come in a number of different structures, also known as crystal lattices or phases. If atmospheric pressure is increased to 300,000 times its normal value, an another phase (B2) of NaCl (represented by the yellow portion of the diagram) becomes more stable, effecting a change in the crystal lattice. To test their choice of methods and parameters, the researchers simulated two crystal lattices and calculated the pressure that corresponds to the phase transition between them. Their predictions agree with experimental data.

Just how thin should it be?

The compounds within the scope of this study can all have a hexagonal, “graphitic”, G phase (the red in the diagram) that is unstable in 3D bulk but becomes the most stable structure for ultrathin (2D or quasi-2D) films. The researchers identified the relationship between the surface energy of a film and the number of layers in it for both cubic and hexagonal structures. They graphed this relationship by plotting two lines with different slopes for each of the compounds studied. Each pair of lines associated with one compound has a common point that corresponds to the critical slab thickness that makes conversion from a cubic to a hexagonal structure energetically favourable. For example, the critical number of layers was found to be close to 11 for all sodium salts and between 19 and 27 for lithium salts.

Based on this data, the researchers established a relationship between the critical number of layers and two parameters that determine the strength of the ionic bonds in various compounds. The first parameter indicates the size of an ion of a given metal–its ionic radius. The second parameter is called electronegativity and is a measure of the ? atom’s ability to attract the electrons of element B. Higher electronegativity means more powerful attraction of electrons by the atom, a more pronounced ionic nature of the bond, a larger surface dipole, and a lower critical slab thickness.

And there’s more

Pavel Sorokin, Dr. habil., is head of the Laboratory of New Materials Simulation at TISNCM. He explains the importance of the study, ‘This work has already attracted our colleagues from Israel and Japan. If they confirm our findings experimentally, this phenomenon [of graphitisation] will provide a viable route to the synthesis of ultrathin films with potential applications in nanoelectronics.’

The scientists intend to broaden the scope of their studies by examining other compounds. They believe that ultrathin films of different composition might also undergo spontaneous graphitisation, yielding new layered structures with properties that are even more intriguing.

Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production (Figure 1).  It has oftentimes been quoted over the last couple of years that China’s imports of semiconductors exceeds that of oil.

In its upcoming Mid-Year Update to The McClean Report 2016 (released at the end of this week), IC Insights examines the “Three-Phase” history of China’s attempt at strengthening its position in the IC industry that started in earnest in the late 1990s (Figure 2).

Figure 1

Figure 1

Figure 2

Figure 2

In the late 1990s, China began to contemplate ways to grow its indigenous IC industry and assisted in creating Hua Hong NEC, which was founded in 1997 as a joint venture between Shanghai Hua Hong and Japan-based NEC (it merged with Grace in 2011).  Then, as part of the country’s 10th Five Year Plan (2000-2005), establishing a strong China-based IC foundry industry became a priority.  As a result, pure play foundries SMIC and Grace (now Hua Hong Semiconductor) were both founded in 2000 and XMC was founded in 2006.  This effort is categorized by IC Insights as Phase 1 of China’s IC industry strategy.

In the early 2000s, to help boost the sales of its indigenous foundries, as well as ride the strong wave of fabless IC supplier growth, the Chinese government began attempts to foster a positive environment for the creation of Chinese fabless companies. It should be noted that eight of the current top 10 Chinese fabless IC suppliers were started between 2001 and 2004 and seven of them were in the top 50 worldwide ranking of fabless IC companies last year. This stage of China’s IC industry strategy is labeled by IC Insights as Phase 2.

IC Insights believes that Phase 3 of China’s attempt at creating a strong China-based IC industry began in 2014, just before the start of its 13th Five Year Plan which runs from 2015 through 2020.  As discussed in detail in the Mid-Year Update, this Phase is being supported by a huge “war chest” of cash that is intended to be used to purchase IC companies and their associated intellectual property, provide additional funding to China’s existing IC producers (e.g., SMIC, Grace, XMC, etc.), and to help establish new IC producers (e.g., Sino King Technology, Fujian Jin Hua, etc.).

In 1Q16, the U.S. Department of Commerce slapped an export ban on U.S. IC suppliers’ shipments of ICs to China-based telecom giant ZTE in response to the company allegedly shipping telecommunications equipment to Iran while it was under trade sanctions by the U.S. This ban, if fully enacted, would have a devastating effect on ZTE’s telecom equipment sales (including mobile phones). Thus far, the export ban has been postponed until August 30, 2016 pending further investigation by the U.S. Department of Commerce.

The situation regarding ZTE and the abrupt announcement earlier this year of export controls on the company by the U.S. government sent shock waves throughout the Chinese government as well as China’s electronic system manufacturers.  At this point in time, such potentially drastic measures taken by the U.S. government against such a large Chinese electronics company has bolstered the Chinese government’s resolve to make China more self-sufficient regarding IC component production, spurring increased emphasis on “Phase Three.”

Smaller and faster has been the trend for electronic devices since the inception of the computer chip, but flat transistors have gotten about as small as physically possible. For researchers pushing for even faster speeds and higher performance, the only way to go is up.

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

University of Illinois researchers have developed a way to etch very tall, narrow finFETs, a type of transistor that forms a tall semiconductor “fin” for the current to travel over. The etching technique addresses many problems in trying to create 3-D devices, typically done now by stacking layers or carving out structures from a thicker semiconductor wafer.

“We are exploring the electronic device roadmap beyond silicon,” said Xiuling Li, a U. of I. professor of electrical and computer engineering and the leader of the study. “With this technology, we are pushing the limit of the vertical space, so we can put more transistors on a chip and get faster speeds. We are making the structures very tall and smooth, with aspect ratios that are impossible for other existing methods to reach, and using a material with better performance than silicon.”

The team published the results in the journal Electron Device Letters.

Typically, finFETs are made by bombarding a semiconductor wafer with beams of high-energy ions. This technique has a number of challenges, Li said. For one, the sides of the fins are sloped instead of straight up and down, making them look more like tiny mountain ranges than fins. This shape means that only the tops of the fins can perform reliably. But an even bigger problem for high-performance applications is how the ion beam damages the surface of the semiconductor, which can lead to current leakage.

The Illinois technique, called metal-assisted chemical etching or MacEtch, is a liquid-based method, which is simpler and lower-cost than using ion beams, Li said. A metal template is applied to the surface, then a chemical bath etches away the areas around the template, leaving the sides of the fins vertical and smooth.

“We use a MacEtch technique that gives a much higher aspect ratio, and the sidewalls are nearly 90 degrees, so we can use the whole volume as the conducting channel,” said graduate student Yi Song, the first author of the paper. “One very tall fin channel can achieve the same conduction as several short fin channels, so we save a lot of area by improving the aspect ratio.”

The smoothness of the sides is important, since the semiconductor fins must be overlaid with insulators and metals that touch the tiny wires that interconnect the transistors on a chip. To have consistently high performance, the interface between the semiconductor and the insulator needs to be smooth and even, Song said.

Right now, the researchers use the compound semiconductor indium phosphide with gold as the metal template. However, they are working to develop a MacEtch method that does not use gold, which is incompatible with silicon.

“Compound semiconductors are the future beyond silicon, but silicon is still the industry standard. So it is important to make it compatible with silicon and existing manufacturing processes,” Li said.

The researchers said the MacEtch technique could apply to many types of devices or applications that use 3-D semiconductor structures, such as computing memory, batteries, solar cells and LEDs.

New levels of performance of electronics technology have been enabled by flip-chip technology, fueling the growth of global markets for semiconductors, electronic devices, and a host of industrial and consumer products. BCC Research reveals in its new report that increasing complexity of the architecture of chip design and fabrication is spurring this market’s exponential growth rate.

Semiconductor devices like integrated circuits (ICs) are connected to external circuitry using flip-chip technology by means of solder bumps deposited onto chip pads. Traditionally, devices are connected from substrates or other active components using wire bonds. More specifically, flip chip is directly attached to a board, substrate, or carrier by various conductive methods called bumping. The chip is “bumped” by laying it on a substrate and thus uses a “face down” process. Wire bonding, the older methodology gradually being replaced by flip chip, used a “face up” process.

The global market for flip-chip technology, which totaled $24.9 billion in 2015, should reach $27.2 billion and $41.4 billion in 2016 and 2021, respectively, increasing at a five-year compound annual growth rate (CAGR) of 8.8%. As a segment, copper (Cu) pillar bumping process owned the largest market share in 2015, and should retain its position during the forecast period. The Cu pillar bumping process is expected to reach $21.2 billion by 2021, reflecting a five-year CAGR of 16.7%.

The flip-chip market is a technology-driven market. Manufacturers are focusing on developing new technologies for the bumping process, which in turn is increasing the demand for raw materials required for manufacturing. This leads to aggressive growth in this industry among raw material suppliers. The many advantages over other packaging methods such as reliability, size, flexibility, performance, and cost are the prime factors driving the growth of the flip-chip market. The market is also driven by availability of flip-chip raw materials, equipment, and services.

Demand for flip chips with controlled collapse chip connection (C4) technology has grown significantly due to the shrinking size of chips and demand for more sophisticated structures. Improved thermal heat transfer and performance at higher frequencies also drive the market for flip chips.

Flip-chip bumping extensively uses various wafer bumping technologies, such as lead-free solder, gold stud bumping, and so forth. Copper bumping accounts for the major share of the market. Tin-lead (Sn-Pb) solder is expected to show a highly negative growth rate. Government initiatives to ban toxic substances have impacted its market heavily.

“The Cu pillar bumping process provides better performance, low cost, and is a nontoxic process,” says BCC Research analyst Sinha Guarav. “In addition, increasing demand for communication devices and other computing devices is also expected to have a positive impact on the Cu pillar bumping market.”

Flip-Chip Technologies and Global Markets (SMC089B) analyzes the evolution, architecture, and value chain of flip-chip technologies. Global market drivers and trends, with data from 2015, 2016, and projections of CAGRs through 2021 also are provided.

BCC Research is a publisher of market research reports that provide organizations with intelligence to drive smart business decisions.

Applied Materials, Inc. today announced the appointment of Judy Bruner to serve on its Board of Directors. Ms. Bruner has also been appointed to serve as a member of the Audit Committee of the Board.

“As a well-respected chief financial officer with deep experience in the global high-tech industry, Judy will be an asset to Applied Materials’ Board of Directors,” said Wim Roelandts, chairman of the board of Applied Materials. “Having built her career in increasingly sophisticated finance roles across some of Silicon Valley’s top hardware companies, she is a welcome addition to our team of directors and will be a valued member of our Audit Committee.”

Judy Bruner served as Executive Vice President, Administration and Chief Financial Officer of SanDisk Corporation, a supplier of flash storage products, from June 2004 until its acquisition by Western Digital in May 2016. Previously, she was Senior Vice President and Chief Financial Officer of Palm, Inc., a provider of handheld computing and communications solutions, from September 1999 until June 2004. Prior to Palm, Inc., Ms. Bruner held financial management positions at 3Com Corporation, Ridge Computers and Hewlett-Packard Company. She currently serves as a member of the board of directors of Brocade Communications Systems, Inc. and a member of the board of trustees of the Computer History Museum.

For more than six decades, the annual IEEE International Electron Devices Meeting (IEDM) has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors and related micro/nanoelectronics devices.

That tradition continues this year with a few new twists, including a supplier exhibition and a later paper-submission deadline (August 10) of a final, four-page paper. Accepted papers will appear in the proceedings without any changes. This streamlined process will ensure that even as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016, beginning with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events will precede a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of great interest, IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

Here are some of the noteworthy events that will take place at this year’s IEDM:

Special Focus Sessions

  • Wearable Electronics and Internet of Things
  • Quantum Computing
  • System-Level Impact of Power Devices
  • Ultra-High-Speed Electronics

90-Minute Tutorials – Saturday, Dec. 3

A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research. Advance registration is recommended.

  • The Struggle to Keep Scaling BEOL, and What We Can Do Next, Rod Augur, Distinguished Member of the Technical Staff, GLOBALFOUNDRIES
  • Electronic Circuits and Architectures for Neuromorphic Computing Platforms, Giacomo Indiveri, Univ. of Zurich and ETH Zurich
  • Physical Characterization of Advanced Devices, Robert Wallace, Univ. Texas at Dallas
  • Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Ben Kaczer, Principal Scientist, imec
  • Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications, Bernard Dieny, Chief Scientist, Spintec CEA
  • Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Short Courses – Sunday, Dec. 4

The Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance registration is recommended.

  • Technology Options at the 5-Nanometer Node, organized by An Steegen and Dan Mocuta of imec (Sr. Vice President of Technology Development/Director of Logic Device and Integration, respectively)
  • Design/Technology Enablers for Computing Applications, organized by John Chen, Vice President of Technology and Foundry Management, NVIDIA

Plenary Presentations – Monday, Dec. 5

  • Memory Scaling – Challenges and Opportunities, Seok-Hee Lee, Executive Vice President and Head of DRAM Product and Technology, Hynix
  • Brain-Inspired Computing, Dharmendra S. Modha, IBM Fellow and Chief Scientist for Brain-Inspired Computing, IBM
  • Differentiating Technologies and Novel Opportunities for the Future Internet of Everything: the Quest for Power Efficiency, Marie-Noëlle Semeria, CEO, Leti

Evening Panel Session – Tuesday evening, Dec. 6

The IEDM offers attendees two evening sessions where experts give their views on important industry topics. Audience participation is encouraged to foster an open and vigorous exchange of ideas.

  • How Will the Semiconductor Industry Change to Enable 50 Billion Connected Devices? Moderator: Prof. Aaron Thean, University of Singapore
  • Challenges and Opportunities for Neuromorphic and Machine Learning, Moderator: Marc Duranton, Sr. Member of the Embedded Computing Lab, CEA

Entrepreneurs Lunch – Wednesday, Dec. 7

Jointly sponsored by IEDM and IEEE Women in Engineering, the Entrepreneurs Lunch will feature Vamsee Pamula, co-founder of Baebies, Inc. a company developing digital microfluidics technology for newborn screening and pediatric testing. Pamula co-founded Baebies in 2014, following the sale of a predecessor microfluidics company that he also co-founded – Advanced Liquid Logic – to Illumina, Inc.

Vamsee has years of experience with digital microfluidics. He has served as Principal Investigator on several National Institutes of Health-funded projects, and has led many talks and published more than 60 articles, five book chapters and a book on the topic. He has more than 200 issued and pending patents, a PhD in Electrical and Computer Engineering from Duke University, and also serves as Adjunct Professor there.

Late-News Deadline

A very limited number of Late News Papers will be accepted, focusing on very recent developments, with a submission deadline of September 12. The submission format is the same as for regular papers.

Further information about IEDM

For registration and other information, visit www.ieee-iedm.org.