Category Archives: 3D Integration

Contributing editor and blogger Phil Garrou received the 3D InCites “Device of the Year” award during the 2016 SEMICON West conference for “Excellence in 3D Packaging Technologies.” The awards were a result of industry voting for individuals, companies and products exhibiting excellence in 3D packaging expertise and contributing to the commercialization of game-changing technologies such as: fan-out wafer level packaging (FOWLP), interposer-based packages, 3D stacks and 3D System-in-Package (SiP).

  • Since his retirement from Dow Chemical in 2004, Dr. Garrou has provided information as a consultant, expert witness and reporter on high end packaging with a focus on 2.5 / 3D Integration.
  • His weekly Solid State Technology packaging blog “Insights From the Leading Edge” (IFTLE) is now approaching its 300th post.
  • He has written 130 articles for Yole Developpement’s iMicronews that took “A Closer Look” at advanced packaging technologies focusing on 3DIC.
  • He co-edited Vol. 1-3 of the Wiley VCH series “Handbook of 3D Integration” in 2008 and 2014 and co-edited the first MRS Proceedings on 3DIC (2006 & 2008).
  • Garrou helped create and chaired the 1st and 4th “IEEE 3D System Integration Conference” that is now entering its 7th year and has been Technical Chair of the RTI “3D Architectures for Semiconductor Integration & Packaging” Conference (3D ASIP) for the past 9 years.
Phil Garrou accepts the award for "Excellence in 3D Packaging Technologies"                                                                      from 3D InCites Francoise von Trapp.

Phil Garrou accepts the award for “Excellence in 3D Packaging Technologies” from 3D InCites Francoise von Trapp.

Amkor Technology, Inc. recently received the 3D InCites “Device of the Year” award during SEMICON West for its’ SWIFT semiconductor package. The awards were a result of industry voting for individuals, companies and products exhibiting excellence in 3D packaging expertise and contributing to the commercialization of game-changing technologies such as: fan-out wafer level packaging (FOWLP), interposer-based packages, 3D stacks and 3D System-in-Package (SiP).

Amkor’s SWIFT product was uniquely developed to deliver a high yielding, high-performance package with the thinnest profile in the industry. This package can deliver 2 µm line/space lithography with up to 4 layers of RDL and a very dense network of memory interface vias from bottom package to the top package at a very cost competitive price.

Jon Woodyard, Amkor's VP of Technical Programs accepts the 3D InCites award for "Device of the Year" from Francoise von Trapp and Stephen Hiebert, KLA-Tencor.

Jon Woodyard, Amkor’s VP of Technical Programs accepts the 3D InCites award for “Device of the Year” from Francoise von Trapp and Stephen Hiebert, KLA-Tencor.

Toshiba Corporation (TOKYO:6502) and Western Digital Corporation (NASDAQ:WDC) today celebrated the opening of the New Fab 2 semiconductor fabrication facility located in Yokkaichi, Mie Prefecture, Japan.

Expanded use of flash memory in smartphones, SSDs, and other applications is driving continued growth of the global flash memory market. The New Fab 2 facility will support the conversion of the companies’ 2D NAND capacity to 3D flash memory, allowing realization of solutions offering higher densities and better device performance.

Construction of New Fab 2 began in September 2014. Following partial completion of the facility in October 2015, Toshiba and SanDisk (acquired in May 2016 by Western Digital Technologies Inc., a wholly owned subsidiary of Western Digital Corporation) worked together to implement leading-edge manufacturing capabilities for mass production of 3D flash memory, and first-phase production started in March of this year. The parties intend to further invest to expand production capacity over time, depending on market conditions.

In addition, Yokkaichi operations will leverage the site-wide integrated production system, which employs big data processing to analyze over 1.6 billion data points each day, to further improve manufacturing efficiency and the quality of 3D flash memory.

The parties are committed to working together to enhance the value they offer to customers and to continue innovation as market leaders.

Satoshi Tsunakawa, President and CEO of Toshiba Corporation, said, “Advanced technologies underline our commitment to respond to continued demand as an innovator in flash memory. We are enhancing manufacturing efficiency and the quality of our world-class facility. Building on that, we also plan investments of as much as 860 billion yen by FY2018, in line with market situation. Our commitment is firm, and we are confident that our joint venture with Western Digital will produce cost competitive next generation memories at Yokkaichi.”

Steve Milligan, Chief Executive Officer of Western Digital, said, “As a leader in non-volatile memory products and solutions, we are excited to be entering the 3D NAND era with our partner Toshiba. The New Fab 2 enables us to begin the conversion of our existing 2D NAND capacity to 3D NAND and continues our long-standing presence in Yokkaichi, Mie Prefecture, and Japan.”

Leti, an institute of CEA Tech, and the Korea Institute of Science and Technology (KIST) today announced an agreement to jointly explore a variety of technologies, including monolithic 3D, neuromorphic architectures, non-volatile 3D memory, spintronics and ultra-low power semiconductors.

The five-year joint project also will focus on creating a broad network to foster international collaboration on ultra-low power semiconductors, which both institutes agree will be required to power the ever-increasing spread of digital devices and the Internet of Things.

“Like Leti, KIST has helped set the standards for government-supported research institutes for 50 years,” said Leti CEO Marie Semeria. “This agreement reflects that we have identified numerous vital technology fields that must be developed to make industry more productive, companies more innovative and society more responsive to people in many aspects of their lives.”

“Post-Silicon Semiconductor Institute (PSI) of KIST is playing a key role in semiconductor R&D in Korea. With this agreement, KIST and Leti will strengthen the collaborative relationship to achieve global leadership in the field of semiconductors.” said KIST president Byung Gwon LEE.

Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 59 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,900, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo.

KIST is a multi-disciplinary research institute located in Seoul, S. Korea. Founded in 1966, it is the first multi-disciplinary scientific research institute in Korea and has contributed significantly to the economic development of the country, particularly during the years of accelerated growth in the 1970s and 1980s.

Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy efficient than current solutions and is compatible with 3D architectures.​

Leti researchers, working in the frame of IRT Nanoelec, boosted computing power and slashed energy consumption by stacking chips on top of each other in a single enclosure, or by placing the chips side by side on a silicon interposer. The chips, which have progressed from demonstrator to fabrication-ready, exchange data via a new communications network that is part of the network on chip (NoC) called 3D-NoC.

3D-NoC technology has been demonstrated with a homogeneous 3D circuit that is comprised of regular tiles assembled using a 4x4x2 NoC. It also features robust and fault-tolerant asynchronous 3D links, and provides 326 MFlit/s @ 0.66 pJ/bit. It was fabricated in a CMOS 65nm technology using 1,980 TSVs in a Face2Back configuration.

This second generation 3D-NoC technology has been integrated in the INTACT circuit developed in the frame of IRT Nanoelec. The 3D circuit, currently in foundry, combines a series of chiplets fabricated at the FDSOI 28nm node and co-integrated on a 65nm CMOS interposer.  The active interposer embeds several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components.

Moreover, the chip requires 20 times less energy for data transmission than chips placed on an electronic circuit board. This new IP is compatible with standard remote direct-memory-access-type software used for data transmission and has likely industrial uses in virtual-server migration applications.

“The steady rise in the number of applications that require high-performance computing creates a demand for new hardware-plus-software communications solutions that improve both performance and energy consumption,” said Denis Dutoit, Leti strategic marketing manager. “This new technology brick makes it possible to transfer data between processors via a network-on-chip delivering more powerful, energy-efficient computing.”

Leti will host its annual workshop during Semicon West on “Sensing your Future with Leti” at 5 p.m., July 12, at the W Hotel.  Registration is here.

Leti scientists will be available at booth #2028 in the South Hall during Semicon West to discuss this announcement and other recent research developments and initiatives.

Applied Materials, Inc. today announced its next-generation e-beam inspection system is delivering the highest resolution and image quality at the fastest throughput to leading foundry, logic, DRAM and 3D NAND customers as they move to advanced nodes.

The Applied PROVision system is the industry’s most advanced e-beam inspection tool, incorporating innovations based on more than 20 years of leading expertise in e-beam technology for review and metrology. It is the only e-beam hotspot inspection tool offering down to 1nm resolution, allowing customers to detect the most challenging “killer” defects that other technologies cannot find, and to monitor process marginality to rapidly resolve ramp issues and achieve higher yields.

“The PROVision system is the latest addition to our e-beam portfolio, and is a key part of Applied’s growth strategy,” said Bob Perlmutter, vice president and general manager of Applied’s Imaging and Process Control Group. “Our differentiated e-beam column technology is the best in the industry and when coupled with our customers’ new inspection methodologies, enables the PROVision system to go beyond R&D use and into production environments.”

The PROVision system is gaining momentum with already more than a dozen shipments, including repeat orders from a leading foundry and a major memory manufacturer. Additional systems are scheduled for shipment to existing and new customers in the second half of 2016.

“The PROVision system’s unique combination of high resolution and massive sampling has helped accelerate time to solution and time to market for our advanced nodes,” said Dr. Oh-Jang Kwon, SK hynix R&D EBI Group.

Offering 3x faster throughput over existing e-beam hotspot inspection tools, the PROVision system ensures accurate process characterization, prediction and detection of performance- and yield-limiting defects throughout the fab product life cycle. The PROVision system complements Applied’s e-beam metrology and review products as well as the optical patterned wafer inspection product line.

071116 Applied PROVision system

The health of the semiconductor industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong semiconductor market growth without at least “good” worldwide economic growth to support it. Consequently, IC Insights expects annual global semiconductor market growth rates to continue to closely track the performance of worldwide GDP growth (Figure 1).  In its upcoming Mid-Year Update to The McClean Report 2016 (to be released at the end of July), IC Insights forecasts 2016 global GDP growth of only 2.3%, which is below the 2.5% level that is considered to be the global recession threshold.

Figure 1

Figure 1

In many areas of the world, local economies have slowed.  China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to continue to lose economic momentum in 2016.  Its GDP is forecast to increase 6.6% this year, which continues a slide in that country’s annual GDP growth rate that started in 2010 when growth rates exceeded 10%.

IC Insights believes that the worldwide economy will be negatively impacted, at least over the next year or two, by the Brexit vote this past June.  At this point, since the U.K. is unlikely to officially be able to leave the European Union (EU) for a couple of years, the biggest negative effect on economic growth is the uncertainty of the entire situation.  Some of the uncertainty created by the vote includes:

•    Whether the U.K. will actually leave the EU.  Since the Brexit vote is not legally binding, and still needs to be approved by the U.K. government, there is uncertainty if its departure from the EU will actually happen.

•    Whether the U.K. will come apart itself.  There are rumblings about Scotland breaking away from being a part of the U.K. in order for it to remain as part of the EU.

•    What trade deals will be made by the U.K. if it does leave the EU?  As part of its exit from the EU, the U.K. will need to establish numerous new trade deals with the EU.  There is tremendous uncertainty regarding whether these deals would have a positive or negative effect on the U.K. economy.

•    Will other countries follow the U.K. and depart from the EU?  Anxiety persists over whether the EU will fall apart as other countries attempt their own exit.  Some countries mentioned as possibly following the U.K. out of the EU include the Netherlands (Nexit), France (Frexit), Italy, Austria, and Sweden (Swexit).

The other major “culprit” dragging down semiconductor industry growth this year is the very weak DRAM market.  At $45.0 billion, the DRAM market was the largest single product category in the semiconductor industry in 2015.  IC Insights forecasts that the DRAM market will register a 19% drop of $8.5 billion this year to $36.5 billion.  The DRAM market alone is forecast to shave three percentage points off of total semiconductor market growth this year. Semiconductor market growth excluding DRAM is forecast to be +2%.

Most of the DRAM market decline expected for this year is due to a rapid decline in DRAM pricing over the past 18 months.  For 2016, the average price for a DRAM device is forecast to drop to $2.55, a steep 16% decline as compared to 2015’s DRAM ASP of $3.03. Further trends and analysis relating to semiconductor market forecasts through 2020 will be covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.

Kulicke & Soffa Industries, Inc. (NASDAQ: KLIC), a designer and manufacturer of semiconductor and LED assembly equipment, has joined A*STAR’s Institute of Microelectronics (IME)’s Chip-on-Wafer Consortium II, together with other major industry players. Through this collaboration, K&S is confident that with the combined experience and knowledge, the consortium will extend the capabilities of Chip-on-Wafer (CoW) assembly with low-temperature copper-to-copper bonding for 2.5D and 3D IC integration.

Deepak Sood, Kulicke & Soffa’s Vice President of Global Engineering, said, “As the features and functionalities of ICs increase, growing demand for reduced pitch and higher I/O count are driving the need for innovative solutions. Addressing the fundamental challenges to enable the next generation of fine-pitch 2.5D and 3D devices, at high throughputs, will create meaningful production value.”

Low temperature copper-to-copper bonding is a key enabler to fine-pitch Chip-on-Wafer bonding (<10um copper pillar pitch). Often, the higher I/O, fine-pitch layout poses inherent challenges for existing production techniques. Through developments focused on reducing bonding temperature and force requirements, the consortium is driving solutions for yield improvements, cost reductions and ultimately broad market adoption.

“We are pleased to welcome K&S as a member in the Chip-on-Wafer Consortium II. We have worked with K&S for close to two years and achieved encouraging results in the development of advanced packaging technology. Our collaboration with valuable industry players such as K&S is an example of how IME’s research capabilities can drive innovation and help semiconductor companies capture new growth opportunities in the electronics market. We look forward to our continued collaboration and helping it to develop new products on flip chip bonding that will meet emerging market requirements on 2.5D and 3D IC packaging,” said Prof. Dim-Lee Kwong, Executive Director of IME.

Related news: A*STAR’S IME launches Chip-On-Wafer Consortium II and Cost Effective Interposer Consortium

A*STAR’s Institute of Microelectronics (IME) has partnered semiconductor companies to develop cost-effective solutions in 2.5D and 3D wafer-level integrated circuit (IC) packaging. The newly formed Chip-on- Wafer Consortium II and the Cost-Effective Interposer Consortium will leverage IME’s expertise in 3D and 2.5D IC integration; bonding technologies; as well as the design and packaging of semiconductor dies to develop advanced chip packaging solutions. All these capabilities will lead to cost savings and high- volume manufacturing.

In today’s mobile and connected world, consumers demand next-generation devices that are multi-functional, more compact, offer better performance, and consume less power. As the industry moves towards more innovative technologies to keep pace with market trends, it must also keep manufacturing costs low to remain competitive.

The Chip-on-Wafer (CoW) Consortium II will build on the success of the first CoW consortium to further reduce production time and costs for 3D and 2.5D packaging. In the CoW Consortium I, IME and its partners successfully demonstrated Chip-on-Wafer bonding with Copper-Copper (Cu-Cu) diffusion bonding technology. The two-step process involves temporary flip-chip bonding and permanent gang bonding at a temperature of 200 degree celsius. This enables the scaling of the interconnect pitch of the integrated circuit from the average of 40 (micrometers) μm to 6μm.

The consortium achieved the highest throughput bonding – five times faster than the conventional solder-assisted thermo-compression bonding technique – making the flip-chip bonding of thin (20μm) through-silicon via (TSV) dies possible without damaging the chip.

These technological breakthroughs will allow device manufacturers to better integrate 3D chipsets such as complementary metal-oxide semiconductor (CMOS) image sensors, signal processors, logic and memory, and memory stacks. They will also increase the overall throughput by 400 to 500 per cent and lower the manufacturing cost by approximately 40 per cent.

The CoW Consortium II (please refer to Annex A for list of consortium members) will further develop the Cu-Cu diffusion bonding technology for energy-efficient and highly reliable devices. This technology will be applied in the development of 3D memory stack and 2.5D integration of a field-programmable gate array (FPGA) and memory on TSV-less interposer. It aims to achieve these by demonstrating a low-temperature Cu-Cu bonding with narrow-gap (3 to 5μm) flip- chip bonding, where the narrow gap is filled with optimised pre-applied under-fill.

Prior to the Cost-Effective Interposer Consortium, IME’s 2.5D Through-Silicon Interposer (TSI) Consortium successfully demonstrated an end-to-end design- process-assembly-packaging flow for large area (39 mm by 27 mm) TSI with dense multi-level Cu interconnects. FPGA and Dynamic Random Access Memory (DRAM) ICs were integrated for high-performance and power-efficient systems. The consortium also developed a 2.5D TSI process design kit (PDK) and electronic design automation (EDA) flow for fabless companies to design TSI, and subsequently perform wafer fabrication, assembly and packaging at IME’s 300mm wafer fabrication facility. These achievements afford companies across the value chain a lower cost of entry, and seamless design-to-manufacturing flow for 2.5D TSI technology. IME worked closely with Foundry, OSAT, Materials, Equipment, EDA, Fabless partners to capture their design and manufacturing requirements, and overcome challenges associated with the volume production of 2.5D TSI.

The Cost-Effective Interposer Consortium (please refer to Annex B for list of consortium members) will address the high manufacturing costs of interposers. It will address the capability limitations in silicon interposers for FPGA and graphic processing unit (GPU) IC designs for 2.5D and 3D IC packaging. IME and its partners will integrate value-added analog and power management unit (PMU) to the silicon interposer and develop an interposer which will not require TSV processing; hence reducing the cost of silicon interposers by up to 50 per cent.

Prof. Dim-Lee Kwong, Executive Director of IME said, “The outstanding results of phase 1 of our past consortia bring us to a new milestone in advanced chip packaging. They will play a foundational role in meeting challenging requirements for highly integrated mobile applications and connected devices. Moving forward, I am confident that IME’s close collaboration with our partners will continue to take our advanced packaging technologies and solutions to greater heights, and spur the mass adoption of cost-effective high performance systems.”

Leveraging significant presence in TSV markets, ALLVIA, Inc. has expanded its capacity into glass and quartz via manufacturing to accommodate customer requests in via-fill technology from silicon interposers to glass and quartz interposers. This will enable next-generation semiconductor 2D and 2.5 D packaging solutions using ultra-thin glass and quartz.

ALLVIA will manufacture ultra-thin glass and quartz interposers using its facility fully equipped for high volume manufacturing of TSV interposers to commercialize the widespread use of interposers. The company will expand its intellectual property from silicon to glass in hole drilling and filling methodologies to fabricate its interposers.

ALLVIA will apply its proprietary technology to fill the high-aspect-ratio via holes with copper plating. ALLVIA’s processes and its production line can produce all types of interposers to achieve the next generation in high-density semiconductor packaging. These 2D and 2.5D interposers are needed to form the electrical connections between a silicon chip and PCBs.

Sergey Savastiouk, CEO, commented:  “Our expansion allows us to solve two problems. First, ALLVIA becomes more flexible with customer requests and, second, ALLVIA can produce more wafers with better quality using state-of-the-art for copper plating, chemical mechanical polishing, deep via thin film deposition.”