Category Archives: 3D Integration

Ultratech, Inc., a supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HBLEDs), as well as atomic layer deposition (ALD) systems, today announced that it has received a multiple-system, follow-on order from a leading semiconductor manufacturer for its advanced packaging AP300 lithography systems. The AP300 systems will be utilized for high-volume, fan-out wafer-level packaging (FOWLP) applications used to manufacture leading-edge chips.  Ultratech will begin shipping the additional systems in the second quarter of this year to the customer’s facility in Asia.

Ultratech General Manager and Vice President of Lithography Products Rezwan Lateef stated, “Fan-out technologies continue to be regarded as the optimal solution for the highly-demanding mobile and wireless markets. While traditional 3D techniques, such as TSV, are still too expensive for industry-wide adoption, FOWLP is being leveraged as a cost-effective packaging solution that delivers excellent performance and a small form factor. Ultratech’s application-specific options for FOWLP lithography provide superior results to meet the challenges of fan-out wafer processing, such as die surface-to-mold non-planarity, die misalignment and wafer warpage. This follow-on order further confirms our technology leadership and the value proposition of our AP300 systems over full-field 1X scanners and reduction steppers. As we continue to build on our relationship with this valued customer, we look forward to supporting their aggressive technology roadmap which includes the utilization of interposers for high-end processors.”

Ultratech’s AP300 family of lithography steppers

The AP300 family of lithography systems is built on Ultratech’s customizable Unity Platform, delivering superior overlay, resolution and side wall profile performance and enabling highly-automated and cost-effective manufacturing. These systems are particularly well suited for copper pillar, fan-out, through-silicon via (TSV) and silicon interposer applications. In addition, the platform has numerous application-specific product features to enable next-generation packaging techniques, such as Ultratech’s award winning dual-side alignment (DSA) system, utilized around the world in volume production.

Power transistors—the $12 billion growth engine in the $21 billion discrete semiconductor market—have faced a choppy uphill climb since surging in the 2010 recovery from the 2008 2009 economic recession. Worldwide revenues for power transistors continue to increase by a compound annual growth rate (CAGR) of about 4%, but sales in the largest discretes product category have fallen in three out of the last five years because of ongoing economic uncertainty and quick cancellation of purchase orders by systems makers whenever they see signs of demand weakening for end-use electronic products, says IC Insights’ 2016 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

After dropping 7% in 2015 to $12.3 billion, power transistor sales are expected to stabilize and begin a modest recovery in 2016, growing by a little over 1% to $12.4 billion, according to the latest edition of IC Insights’ annual O-S-D Report, which contains a detailed five-year forecast of sales, unit shipments, and average selling prices (ASPs) for more than 30 individual product types and device categories in optoelectronics, sensors/actuators, and discretes. The 360-page report shows power transistor sales slowly regaining strength in the next few years, rising 3% in 2017 to $12.8 billion followed by 5% growth in 2018 to about $13.5 billion, which will match the current annual peak set in 2011 (Figure 1).

Between 2015 and 2020, power transistor sales are projected to grow by a CAGR of 3.9% to $14.8 billion in the final year of the 2016 O-S-D Report’s forecast.  The annual growth rate in the second half of this decade essentially matches the CAGR of 4.0% recorded in the last 10 years (2005-2015), but IC Insights anticipates much less volatility in the power transistor market because worldwide demand will continue to climb for greater energy efficiency in data center computers, industrial systems, home appliances, battery-operated portable electronics, automobiles, and the explosion of connections to the Internet of Things (IoT).  Worldwide shipments of power transistors are now forecast to rise by a CAGR of 6.5%, reaching 71.1 billion units in 2020 compared to about 52.0 billion in 2015.

power transistors

Among the power transistor product categories, sales growth is expected to be the strongest in high voltage field-effect transistors (FETs) and insulated-gate bipolar transistor (IGBT) modules during the second half of this decade. The 2016 O-S-D Report shows sales of high-voltage (over 200V) FETs growing by a CAGR of 4.7% to $2.4 billion in 2020 while IGBT modules are expected to increase by an annual rate of 4.0% to $3.2 billion in five years.  Other projected 2015-2020 CAGR growth rates for power transistor product categories are: 3.7% for low-voltage FETs (under 200V) to $5.6 billion; 3.8% for discrete IGBT transistors to $1.1 billion; and 3.1% for bipolar junction transistors to $886 million in 2020.

By Paula Doe, SEMI

Emerging opportunities for advanced packaging solutions for heterogeneous integration include a lot more than logic, memory and sensors. There’s also the challenges of packaging integrated photonics, flexible electronics, and high-voltage, high-temperature wide-bandgap power devices. Speakers from the National Network for Manufacturing Innovation Institutes targeting these new growth markets will update the SEMICON West 2016 audience on their efforts to cut the time and cost of moving from R&D to volume production for U.S. companies by supporting development of key technologies, U.S.-based facilities for fabrication and packaging, and education of the workforce.

ap forum 2016-1

Integrating silicon with optics

The new American Institute for Manufacturing Integrated Photonics (AIM Photonics) is ramping up its program to spur development of U.S. technology and manufacturing capability for integrated photonics, for next-generation high performance computing, telecommunications, and sensors. In the packaging space, first steps will be a university-industry effort to develop passive fiber-to-silicon assembly technology and automated test equipment, with a manufacturing facility targeted for 2017.

“We’re focusing on packaging, assembly and test since it accounts for most of the cost of integrated photonics,” says CEO Michael Liehr, who will update on the plans to facilitate U.S. manufacturing in this emerging sector in the Packaging Photonics session at SEMICON West on July 12.

Attaching an optical fiber of 120µm diameter to a waveguide of only several thousand angstroms remains a major challenge, typically requiring active alignment.  Volume production will need a passive alignment solution, which will require some combination of major improvement in precision of current placement tools (such as with image recognition) with some way to make the coupling more fault tolerant ─ such as by using an interposer to bridge the gap. Tool makers will need standard package interfaces to make common, not custom equipment. The institute will also work on the packaging issues of integrating the laser with the waveguides and other optical features on silicon.

“Key elements are also missing for test,” Liehr notes. “The in-line part is missing. No one has put together a commercially available system that includes the prober, the optical detection, and the coupler needed.”  The institute is putting together a university and industry team to develop solutions, and then will equip a facility to do the test, assembly and packaging of these photonic integrated circuits.

AIM Photonics also targets a Process Design Kit (PDK) design kit by the end of the year for its multi-project photonic wafers run in its front-end fab. Besides data center and telecommunications applications of integrated photonics, AIM Photonics is working with companies on phased arrays and optical sensors for healthcare and defense applications. The organization is a public-private venture, funded by the U.S. Department of Defense, the States of New York, Massachusetts, California, Arizona, and university and industry members.

Integrating silicon die into flexible, conformable electronics systems

Another emerging “packaging” opportunity is integrating silicon intelligence into  flexible, stretchable products. “People have been talking for decades now about a purely printed solution, but printed transistors do not have enough mobility for the needed performance, and in a switching application will burn out in about a day” notes Jason Marsh, Director of Technology at NextFlex, the Manufacturing Innovation Institute for Flexible, Hybrid Electronics, who will talk about this effort at the SEMICON program on flexible packaging July 14. “But there is real demand for flexible, conformable products for medical wearable and implantable devices and for IoT edge devices.”  The collaborative program aims to develop the manufacturing technology to enable these products, by integrating silicon die into flexible, stretchable environments.

This will require the development of new processes for bridging directly from ~100µm-scale printed electronic circuits to 50µm-scale PCB artwork to much finer die-level bond-pad pitch, eliminating the usual intervening steps ─ of wirebond/flip chip, package, interposer, circuit board, connector ─ all at low temperature and with good signal integrity. Potential approaches could include flip chip with an anisotropic conductor connection, or alternatively, printing the traces directly on bigger pond pads. The institute aims to develop the basic building blocks of the technology and put together a U.S. supply chain that companies can then use to develop and manufacture their own products. NextFlex is building a facility in San Jose for the technology, which members can use to develop prototypes and build their pilot products.

Building this new manufacturing supply chain means re-thinking the traditional food chain of circuit board, packaging and assembly. “We may need to do things in different order, with die attach to the substrate before circuitization, and may need big arrays on big substrates, with new process tools to handle them,” suggests Marsh. “Package and assembly suppliers will need to understand more of the full end-to-end process, with assembly companies understanding packaging, and packaging companies understanding interposers.” The project aims to help bring these suppliers together, and also to help develop the necessary technical expertise in the workforce in the U.S. “The goal is to accelerate the speed of development from some 5-6 years to 1-2 years,” says Marsh.

The program is funded by $75 million from the U.S. government, and $96 million from the City of San Jose, and other corporate, academic, and government partners.

Building a U.S. ecosystem for wide bandgap power semiconductor manufacturing

PowerAmerica, the Next Generation Power Electronics Manufacturing Innovation Institute, aims to build the U.S. ecosystem for manufacturing wide bandgap power semiconductors, by supporting R&D, production facilities, and workforce development to accelerate the adoption of these smaller, lighter and more energy efficient power systems, and to make it easier for new and small U.S. companies to develop products.

“It’s about driving down cost and validating the reliability of SiC and GaN for demanding power electronics applications. The physics are clear. Wide bandgap semiconductors can offer very high-power densities and higher performance with a lower cost bill of materials. We are rapidly approaching the tipping point where market demand and production volume will bring the price of wide bandgap devices down to match silicon in $/Amp,” says John Muth, PowerAmerica’s deputy director, who will update on the effort in the power packaging program at SEMICON West on July 12.

Taking full advantage of the physical properties of wide bandgap semiconductors for high performance will require highly optimized packages that can handle high voltages while minimizing inductance and efficiently remove heat, with more reliable materials for interconnections, die attach, and baseplate/substrates, and better cooling solutions. One result of the packaging projects to date are the low inductance, high performance power modules recently announced by Wolfspeed.

PowerAmerica activities across the supply chain range from the 6-inch SiC foundry at X-Fab in Lubbock, Texas, now being used by five members, to products under development by end users across in transportation, renewable energy, motor drives, data centers, and the power grid, at members such as ABB, Agile Switch, Atom Power, John Deere, Navitas, Lockheed-Martin, and Toshiba.

The institute has recently also started to invite unsolicited proposals that solve a technical problem to help grow and strengthen the supply chain or to accelerate adoption of SiC or GaN into new products. All projects have 1:1 cost sharing, and require a clear path to market. Other efforts include aggressive demonstrations of wide bandgap semiconductor performance by universities, industry-led road mapping activities, and curriculum development at member universities, and tutorials and short courses to bring industry engineers quickly up to speed in GaN and SiC technology.

The five-year $146 million program is funded by $70 million from DOE and another $76 million from cost matching from its members and the state of North Carolina.

To learn more about SEMICON West 2016, visit the Schedule-at-a-Glance and learn about the eight forums.

Correction: The first draft of this article stated in error that Jason Marsh’s talk would take place on July 12. Jason Marsh will speak on flexible packaging at SEMICON West on July 14.

Papers that address the theme “Inflections for a Smart Society” are highlighted.

The 2016 Symposium on VLSI Technology is part of a premiere international conference that defines the pace, progress and evolution of micro-electronics, scheduled from June 13-16, 2016 in Honolulu, Hawaii and held in conjunction with the Symposium on VLSI Circuits (June 14-17, 2016). The Symposia’s overall theme “Inflections for a Smart Society,” reflects the industry’s transition point as “smart” system level applications help to transform the industry.

Samsung Electronics will present a 10nm logic technology developed using 3rd generation Si FinFETs for low power, high performance applications, demonstrating a speed improvement of 27% with a 40% reduction in power compared to 14nm process, achieved with multi-threshold voltage devices and reduced contact resistance (FIGURE 1). Overcoming process challenges such as multiple patterning, high aspect ratio etching, niche gate replace- ments, and advanced isolation, the authors demonstrated yield analysis of a 0.04μm2 SRAM with 128Mb cell size and observed a static noise margin of 190mV at 0.75V.

Screen Shot 2017-04-21 at 11.23.22 AM

TSMC will demonstrate a fully functional 32Mb 6-T high density SRAM with smallest reported size of sub-0.03μm2 using bulk CMOS FinFETs scaled beyond the 10nm node (FIGURE 2). This presentation also reports improved transistor performance and electrostatic control through process and CET optimization of scaled FinFETs with competitive performance: DIBL of <45mV/V, sub-threshold swing of <65mV/decade, and static noise margin of ~90mV for the high density SRAM operated at 0.45V.

Screen Shot 2017-04-21 at 11.23.27 AM

IBM and GLOBALFOUNDRIES developed the fundamental and disruptive enhancement of transistor mobility needed to continue expected power and performance scaling at 10nm and beyond, with the introduction of high mobility SiGe channel (20%Ge) into the PFETs to achieve 35% hole mobility increase, and thus ~17% PFET Ieff enhancement. The presentation will demonstrate for the first time10nm FinFET CMOS technology featuring SiGe channel PFETs with superior NBTi reliability and defect control.

TSMC will present a systematic study of the material properties, dimension effects and device characteristics of its In0.53Ga0.47As FinFETs, manufactured on 300mm Si substrates that demonstrate high performance with good uniformity across the wafer. High electron mobility III-V semiconductors are one potential path for continuing Moore’s Law to meet the high performance and low power requirements of future logic applications. Creating high quality hetero-epitaxial of III-V material on large scale Si platforms with good HK/III-V interfaces are critical hurdles to overcome for fabricating HP devices capable of replacing Si FF as scaling continues beyond 7nm.

Significantly, the devices fabricated on 300mm Si show similar characteristics in SS and Ion when benchmarked with equivalent devices fabricated on lattice-matched InP substrates. The current drive of the III-V FinFETs is Ion=44.1uA per fin for a fin-height of 70nm and a fin-width of 25nm. These results are among the highest values reported for In0.53Ga0.47As FinFETs.

Researchers at IBM will demonstrate for the first time high Ge content (HGC) SiGe FinFETs in a replacement mode high-k and metal gate (RMG) process flow with an aggressive equivalent oxide thickness (EOT) scaling down to 0.7nm. IBM’s first of its kind HGC SiGe pMOS FinFETs exhibits high mobility, record-low RMG long channel SS=66mV/dec and good short channel behavior down to Lg=21nm.

The devices are characterized down to 4nm fin widths with excellent mobility (μeff=220cm2/V-s) and reliability at 0.7nm. A 10-year lifetime target is achieved for sub-10nm FinFET widths.
This work demonstrates best mobility values compared to state-of-the-art FinFETs, ultra thin body Si or Ge alternatives, as well as to strained SiGe quantum well options, showing that high performance SiGe FinFETs are feasibile at these aggressive dimensions, with results that outperform all previously reported data.

A team from imec reports on vertically stacked gate- all-around (GAA) n- and p-MOSFETs of 8nm diameter with nanowire stacking and replacement metal gate (RMG) processing, which is relevant for continuing scaling beyond sub-10nm technology (FIGURE 3). Stacking nanowire GAA devices is a promising path to maximize current drive per footprint. Fabricated by adapting a RMG FinFET process, these devices represent an evolutionary approach to extend the learning achieved with FinFET manufacturing. The nanowires exhibit excellent short channel characteristics (SS=65mV/dec, DIBL=42mV/V for Lg=24nm) at performance levels comparable to FinFET devices. The parasitic channel below the nanowires is suppressed by a groundplane doping technique prior to nanowire specific processing.

Screen Shot 2017-04-21 at 11.23.35 AM

Intel’s corporate research group shows performance, area, and energy efficiency are improved by novel tunnel FET (TFET) library circuits, redesign of logic at low-VDD and CMOS/TFET heterogeneous logic. The TFET/CMOS logic with low-overhead level-shifters improves performance 50% while reducing energy 42% for non-critical perfor- mance logic. Performance and power are benchmarked by design synthesis using industry test cases, libraries and interconnect.

TDK Headway Technologies returns to the VLSI Symposium to present advances in writing speed of their perpendicular spin-transfer torque magnetic memory (pSTT-MRAM), which can be reduced to a pulse width of 750ps without compromising functionality and data retention. The switching of the full 8MB array with 80nm devices can be achieved with 3ns pulses without use of error-correcting code (ECC), with the array level data retention showing a 10-year lifetime at 1ppm at 125oC.

They demonstrate sub-ns switching of pSTT-MRAM over a large temperature range after optimization of the magnetic tunnel junction (MTJ) stack, with single devices switched reliably using write pulse length down to 750ps while preserving functionality and data retention @125oC.
This pSTT-MRAM with improved writing speed is a viable candidate for replacement of LCC cache for advanced technology nodes, as well as a possible replacement for non-volatile memory.
A novel perpendicular magnetic tunnel junction (MTJ) is demonstrated by Toshiba with a high speed cache memory operation around 1ns, low power switching less than sub-100μA and size scalability of write current down to 16nm diameter MTJ. This novel MTJ is suited for embedded NVRAM solutions for sub-20nm high-perfor- mance CMOS SoC technology.

Macronix and IBM investigate methods of reducing programming power in phase change memories (PCM) for new storage class memory (SCM) applications. The researchers demonstrate a new low power phase change memory using inter-granular switching (IGS), a novel 3D network of crystallites with phase change confined to grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalco- genide glass is amorphized or crystallized to achieve high or low resistance, they propose a multi-grained structure where the phase change occurs only in the inter-grain regions. By localizing the phase- change to the inter-grain area, the reset power is substantially reduced to 20μA, as well as the thermal disturbance to the neighboring bits, with set speed and cycling endurance also enhanced.

CEA Leti and STMicroelectronics demonstrate for the first time a full 3D VLSI CMOS-over- CMOS integration, CoolCubeTM, on 300mm wafers, with the top level CMOS devices fabricated using low temperature (less than 650°C) processes. A functional 3D inverter with either PMOS over NMOS or NMOS over PMOS is demonstrated to achieve compatible performance with state-of-the- art high performance FDSOI devices. Furthermore, the Leti/STM work demonstrates the integration feasibility of CoolCubeTM by transferring a high quality Si layer over the 28nm devices with W-M1 and then returning to the front end of the line for processing the top CMOS devices.

For the first time, researchers at Stanford and National Nano Device Laboratories have developed a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, integrated with FinFET selector (FIGURE 4). The four-layer 3D RRAM is a versatile computing unit for (a) brain- inspired computing and (b) in-memory computing. Uniform memory performance across four layers is obtained (±0.8V switching, 106 endurance, 104s @125°C). The 3D architecture with dense and balanced neuron-synapse connections provides 55% energy delay product (EDP) savings and 74% VDD reduction (enhanced robustness) as compared with conventional 2D architecture.

Screen Shot 2017-04-21 at 11.23.39 AM

BY ED KORCZYNSKI, Sr. Technical Editor

CEA-Leti in France has been developing monolithic transistor stacking based on laser re-crystallization of active silicon in upper layers called “CoolCube” (TM). Leading mobile chip supplier Qualcomm has been working with Leti on CoolCube R&D since late 2013 and based on preliminary results have opted to continue collaborating with the goal of building a complete ecosystem that takes the technology from design to fabrication.

“The Qualcomm Technologies and Leti teams have demon- strated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.” As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs to accelerate adoption.

Olivier Faynot, micro-electronic component section manager of CEA-Leti, in an exclusive interview with Solid State Technology and SemiMD explained, “Today we have a strong focus on CMOS over CMOS integration, and this is the primary integration that we are pushing. What we see today is the integration of NMOS over PMOS is interesting and suitable for new material incorporation such as III-V and germanium.”

Table: Critical thermal budget steps summary in a planar FDSOI integration and CoolCube process for top FET in 3DVLSI. (Source: VLSI Symposium 2015)

The Table shows that CMOS over CMOS integration has met transistor performance goals with low-temperature processes, such that the top transistors have at least 90% of the performance compared to the bottom. Faynot says that recent results for transistors are meeting specification, while there is still work to be done on inter-tier metal connec- tions. For advanced ICs there is a lot of interconnect routing congestion around the contacts and the metal-1 level, so inter- tier connection (formerly termed the more generic “local inter- connect”) levels are needed to route some gates at the bottom level for connection to the top level.

“The main focus now is on the thermal budget for the integration of the inter-tier level,” explained Faynot. “To do this, we are not just working on the processing but also working closely with the designers. For example, depending on the material chosen for the metal inter-tier there will be different limits on the metal link lengths.” Tungsten is relatively more stable than copper, but with higher electrical resistance for inherently lower limits on line lengths. Additional details on

such process-design co-dependencies will be disclosed during the 2016 VLSI Technology Symposium, chaired by Raj Jammy.

When the industry decides to integrate III-V and Ge alternate-channel materials in CMOS, the different processing conditions for each should make NMOS over PMOS CoolCube a relatively easy performance extension.

“Three-fives and germanium are basically materials with low thermal budgets, so they would be most compatible with CoolCube processing,” reminded Faynot. “To me, this kind of technology would be very interesting for mobile applications, because it would achieve a circuit where the length of the wires would be shortened. We would expect to save in area, and have less of a trade-off between power- consumption and speed.”

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological devel- opment in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”

BY DR. PHIL GARROU, Contributing Editor

Earlier this year, a Taipei Times headline read “New packaging may spur TSMC growth” adding that despite its weak revenue growth guidance for this quarter, TSMC, might see stronger growth from next quarter thanks to its InFO (integrated fan out) packaging technology (see FIGURE).

The Times reports that InFO could help TSMC beat rival Samsung and win more A10 application processor orders from Apple, because the technology offers “…lower costs, higher speed and thinner form factor when compared to conventional flip chip packaging.” TSMC is preparing a complete InFO portfolio aimed at different package sizes and applications. In a conference call with investors in April, TSMC CEO C.C. Wei stated that they have almost completed equipment installation and expect to complete customer product qualification shortly. They plan to ship volume production shortly. Estimates are that the revenue contri- bution from InFO packaging could total US$300 million this year.

Screen Shot 2017-04-21 at 11.00.21 AM

I have previously reported that TSMC had purchased a facility in Longtan, Taiwan (from Qualcomm for $85MM) and was turning it into a facility devoted to the manufac- turing of integrated fan-out wafer-level packaging (InFO- WLP) technology.

Apple is expected to unveil its new iPhone in the second half of this year. Daiwa Capital Markets analysts estimates that Apple’s order split for A9 processors (last generation) was 45% for TSMC and 55% for Samsung, but projects TSMC could take more than 50% of the A10 processor business, due in part to the superior packaging technology now being offered by TSMC. Other smartphone chip vendors are reportedly looking at adopting TSMC InFO packaging technology in the near future.

Screen Shot 2017-04-21 at 11.00.25 AM

I have also previously reported that TSMC lost the chance for making Apple A3 processors to Samsung because it lacked the capability to package and test the chips.

YSIC (Yuanta Securities Investment Consulting) claims the InFO technology is at least 20 percent cheaper than flip chip packaging. YSIC notes that “… it is becoming more difficult to solely rely on front-end tech node migration to drive better performance and cost,” a statement that should be very familiar to readers of this column.

In 2014, I discussed TSMCs announced ambition of becoming a major player in full back-end packaging services with their plans to ramp IC packaging revenues to US $1 billion in 2015 and $2B in 2016 Based on this roadmap, TSMC would become the 3rd leading packaging company in Taiwan by 2016, trailing only ASE and SPIL.

Driven by a strong semiconductor market outlook and aggressive investment in advanced packaging capability fueled by strong government support, advanced packaging revenue in China is expected to reach US$ 4.6 billion in 2020, against US$ 2.2 billion in 2015, announces Yole Développement (Yole). This market is showing an impressive 16% CAGR during this period. China has the world’s largest population, and its economy will continue to grow at a high pace: the economists predict a 6% growth, reaching around US$16 trillion by 2020. Also, an increase in per capita income (more purchasing power) will ensure China remains a dominant market in the coming years. Today, no business can afford to ignore China.

advpackaging_china_waferforecastyole_june2016_373x280

Under this context, the “More than Moore” market research and strategy consulting company, Yole explores the advanced packaging industry in China and details, in its latest advanced packaging report entitled “Status & Prospects for the Advanced Packaging Industry in China”, the status of this industry, its market drivers and key market data and technology trends. Yole’s analysts propose a clear vision of the Chinese government commitment within the advanced packaging industry in China and point out the huge China’s IC investments fund. Business opportunities, technical challenges and more are also part of Yole’s market & technology analysis.

China commands a significant market for key electronic products. In fact, over half of all key electronic products are consumed in China. In 2014, the Chinese smartphone, LCD, notebook/tablet, and wearable markets were around 81%, 63%, 71%, and 47% of the global market, respectively. The global IC market will grow by a CAGR of 4% from 2014 – 2020, while the Chinese IC market will grow by 7% over the same period. According to Yole, the Chinese IC market is expected to reach about US$149 billion by 2020, around 40% of the total IC market.

“There is a huge gap between China’s IC consumption and its manufacturing,” commented Santosh Kumar, Senior Technology & Market Analyst at Yole. And he details: “In 2015, China produced only 12.5% roughly of the IC it consumes, and the gap between IC consumption and production is about US$91 billion. Currently, IC is China’s #1 import commodity, exceeding oil.”

China considers the IC industry to be a key strategic sector. The Chinese government is making a significant effort through funding and a national IC policy, with an aggressive growth strategy to make China an IC design and manufacturing hub. The goal by 2030 is to become the global leader in all primary IC industrial supply chain segments.

The Chinese government has employed a multi-pronged strategy to support domestic IC industry development in order to achieve the goal of becoming the global leader in all primary IC industrial supply chain segments by 2030. Over the last few decades the Chinese government has supported the domestic IC industry, but with limited success. One key reason for failure was the bureaucratic approach to resource allocation, which was by nature inefficient. This time around, the government is adopting a market-based approach where funding is available for investment in the form of equity investments rather than subsidies in invested companies. The goal is to generate return on investment while simultaneously aligning with government policy.

Out of more than 200 firms, there are 128 companies having significant advanced packaging & assembly (A&P) operations in China. Yole’s analysts identified around 147 plants all over China, mostly based in Jiangsu (43), Guangdong (30) and Shanghai (22) regions. In this part of the globe, more than 50% of A&P plants belongs to IDMs . A number of Taiwan-HQ OSAT plants are concentrated in Jiangsu, especially in the Suzhou Industry Park. Indeed global OSATs such as Amkor Technology and SPIL are investing in advanced packaging capability of their own Chinese operations: China (Shanghai) operation is the Amkor’s second-largest factory by revenue. The advanced packaging market growth is led by JCET/STATSChipPAC, Huatian, NFME & China WLCSP. And the Chinese advanced packaging market is offering a wide range of platforms including:

  •  Flip-chip technology is the largest advanced packaging market segment in China reaching US$ 1,8 billion in 2015. The Flip-chip market is covering bumping and assembly steps. “We see a huge ramping of bumping capacity in China, especially by Chinese players with 12” Cu pillar process,” comments Santosh Kumar from Yole. “This growth is mainly supported by the Flip-chip industry in China showing a 16% CAGR between 2015 and 2020”. Flip-chip platform is followed by WLCSP technology with US$ 343 million in 2015 as well.
•  Fan-out and 2.5/3D platforms are only emerging in China and will have less than 1% market share by 2020.

Under its latest advanced packaging report, Yole’s advanced packaging team points out the key market drivers of this industry. They list:
•  Long-term growth in China IC industry
•  Aggressive mergers & acquisitions
•  Numerous Chinese government initiatives
•  Investments led by global OSATs
This analysis also gives an overview of China’s semiconductor ecosystem and discusses in detail the country’s advanced packaging market.

Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented gate-all-around (GAA) n- and p-MOSFET devices made of vertically stacked horizontal silicon (Si) nanowires (NWs) with a diameter of only 8nm. The devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices.

GAA devices architectures offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In addition, horizontal NWs are a natural extension of RMG finFETs, in contrast to vertical NWs which require more disruptive technology changes. Furthermore, stacking of NWs maximizes the drive current per footprint. Imec successfully combined these three aspects, and, for the first time, demonstrated vertically stacked horizontal Si NWs at scaled dimensions: 8-nm-diameter wires, 45-nm lateral pitch, and 20-nm vertical separation.

Compared to the conventional bulk FinFET flow, imec implemented two major differences in the process flow. First, shallow trench isolation (STI) densification at 750°C resulted to preserve sharp silicon-germanium (SiGe)/Si interfaces, which is essential for well-controlled Si NW release. Second, a low-complexity ground plane doping scheme was applied, suppressing the bottom parasitic channel.

“By demonstrating stacked nanowires with solid electrostatic control, at scaled dimensions, and using an industry-relevant RMG process on bulk silicon substrates, imec has achieved breakthrough results that can pave the way to realizing sub-10nm technology nodes,” stated Dan Mocuta, Director Logic Device and Integration at imec. “The upcoming research phase will focus on achieving even denser pitches and on leveraging this knowledge to develop gate-all-around lateral nanowire CMOS devices.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs

Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented junction-less gate-all-around (GAA) nanowire (NW) FETs built in lateral and vertical configurations. With their simplified processing, improved reliability, reduced low frequency noise and lower IOFF values, they are an attractive option for advanced logic, low power circuits and analog/RF applications. Moreover, they enable a simpler path for considerable SRAM scaling via the stacking of vertical devices.

GAA-NWFETs -with the gate fully wrapped around the device body for optimum electrostatics control- are considered one of the most promising candidates for enabling (sub-)5nm CMOS scaling. Moreover, junction-less devices offer great process simplicity as they do not require junctions.

Previously, at the 2015 VLSI and IEDM conferences, imec demonstrated the superior reliability behavior of these devices and their potential for low power circuits. At today’s VLSI symposium, imec thoroughly evaluated key control knobs for junction-less devices operation, namely controlling the NW doping vs. NW size to achieve optimum performance. The feasibility of these devices for analog/RF applications was also studied, concluding them to be a viable option with reported similar speeds and voltage gains as compared to inversion-mode NWFETs.

Imec also addressed the variability of junction-less GAA-NWFETs, showing that whereas the VT mismatch increased with increasing nanowire doping for NMOS devices, less impact was observed for PMOS devices and at smaller nanowire dimensions.

Additionally, the junction-less concept was demonstrated in vertical devices integrated on the same 300mm Si platform, also used for lateral devices. Low IOFF and IGvalues and good electrostatics were achieved over a wide range of vertical nanowire arrays.

Lastly, taking advantage of the junction-less devices process simplicity, Imec further explored their potential by proposing a novel SRAM cell design with two vertically stacked junction-less vertical NWFETs with the same channel doping, thus enabling reduction of the SRAM area per bit by 39%.

“Imec’s work has contributed to an increased and more in-depth understanding of junction-less GAA-NWFETs,” stated Dan Mocuta, Director Logic Device and Integration at imec. “Our thorough evaluation highlighted the excellent performance of junction-less lateral and vertical nanowire devices for beyond 5nm logic devices. Moreover, junction-less devices appeared as a viable option for analog/RF applications, whereas stacked junction-less vertical nanowire FETs could significantly reduce SRAM area.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

Today, SEMI announced that the latest packaging solutions will be the topic of an in-depth session at the SEMICON West 2016 Advanced Packaging Forum – and on display on the exhibition floor. Rapidly changing technologies and accelerated product life cycles are driving the need for new assembly and packaging solutions suited for next-generation products such as Internet of Things (IoT) devices and wearables. To meet these packaging needs, semiconductor technologies with smaller form factors, lower power consumption, and flexible designs are increasingly in demand.

Advanced Packaging Forum 

Six complimentary packaging sessions are offered at the Advanced Packaging Forum at SEMICON West’s TechXPOT North stage. Pre-registration is required. Sessions explore what’s ahead in the world of packaging and assembly. The three-day forum will explore the challenges posed by new and emerging devices and offer solutions capable of enabling them. Technical sessions include:

  • SiP Next 1: Processor – Memory/Analog Integration
  • SiP Next 2:  IoT & Smart Things – SiP Integration
  • Sensing the Future: Enabling Applications for a Smarter World
  • Packaging Developments for Flexible, Hybrid Electronics
  • Packaging Power: Enabling a Variety of Applications and Efficiency
  • Packaging Photonics for Speed & Bandwidth

Sessions feature speakers from Cisco, Mentor Graphics, Texas Instruments, and more.  Attendees will learn about the latest in electronic packaging, thermal management, additive manufacturing, simulation, and reliability assessment; system optimization and differentiation through heterogeneous integration and SiP; sensor technologies for monitoring and analyzing complex data streams; and other advanced developments.

Packaging and Assembly Equipment Exhibitors

This year’s SEMICON West exposition also features packaging solutions on the show floor. Attendees can view more than sixty new products from some 200 exhibitors.

The industry is seeing dramatic changes and SEMICON West 2016 has expanded its technical programming by nearly 50 percent to help attendees get a clear view of the road ahead. To learn more about SEMICON West 2016’s eight new forums (Extended Supply Chain, Advanced Manufacturing, Advanced Packaging, Test, Silicon Innovation, Flexible Hybrid Electronics, and World of IoT), visit www.semiconwest.org.