Category Archives: 3D Integration

Semiconductor Research Corporation (SRC), today announced that SK hynix, a global leader in producing semiconductors including DRAM and NAND Flash memory, has signed an agreement to join SRC’s research consortium. SK hynix will participate in multiple SRC research initiatives including; Global Research Collaboration (GRC) and the New Science Team (NST) project.

GRC, a worldwide research program with 17 industrial sponsors is comprised of nine design and process technology disciplines. SK hynix will participate in SRC’s Nanomanufacturing Materials and Processes and Logic & Memory Devices research programs that focus on new device structures, memory alternatives, materials, and processes.

The NST project, a consortium consisting of 12 industrial sponsors and three government agencies is a 5-year, $300 million SRC initiative launched this January. NST consists of two complementary research programs: JUMP (Joint University Microelectronics Program) and nCORE (nanoelectronics Computing Research), which will advance new technologies focused on high- performance, energy-efficient microelectronics for communications, computing and storage needs for 2025 and beyond.

“The entire SRC team joins me in welcoming SK hynix to our distinguished membership of industry leaders from around the world”, said Ken Hansen, President and CEO of SRC. “SK hynix has an impressive history that showcases how ingenuity and innovative thinking can advance technology at a progressive pace. We look forward to a long, successful relationship with SK hynix as we push the limits of imagination and innovation.”

“SK hynix’s fundamental objective to surpass technological boundaries through propelling innovation has brought us to this association with SRC”, said Jinkook Kim, Head of R&D at SK hynix. “We recognize the significant impact that collaborative research programs such as those underway at SRC have in moving our industry forward. Strategic partnerships in research and development will help drive the Fourth Industrial Revolution with AI and autonomous vehicles leading the way.”

Today’s announcement is significant as the top 5 global semiconductor companies are now members of SRC. SK hynix represents the 8th non-U.S. headquartered company to join SRC as it seeks to expand its global presence. Industry sponsors are invited to explore the possibilities at SRC.

Renesas Electronics Corporation (TSE:6723, “Renesas”), a supplier of advanced semiconductor solutions, today announced that it has resolved at the Meeting of Board of Directors held on October 31, 2018 to consolidate its wholly-owned subsidiary Renesas Semiconductor Package & Test Solutions Co, Ltd. (“Renesas Semiconductor Package & Test Solutions”) through an absorption-type merger (“Merger”).Certain disclosure items and details have been omitted due to the Merger being an absorption-type merger of a wholly-owned subsidiary.

Purpose of Merger

With an aim to build a business structure that can generate consistent profitability, Renesas reorganized its domestic manufacturing subsidiaries and business units in April 2014 to simplify and boost the efficiency of its organization and these efforts have steadily delivered tangible results. Nevertheless, Renesas must build a flexible production system based on quick decision-making to be able to respond to the rapid changes in the semiconductor industry. Renesas therefore decided to consolidate Renesas Semiconductor Package & Test Solutions, which is responsible overall for the back-end production business, effective January 1, 2019, to further simplify the organization and decision-making process within the semiconductor production business and enable rapid and consistent decision-making. The Merger will enable Renesas to build a manufacturing structure optimized for responding to changes in the business environment and accelerate further growth.

3D NAND is poised to become the dominant NAND flash technology and promises both enhanced performance and capacity. The Innodisk 3D NAND solid state drive (SSD) series is designed to fulfill the more stringent requirements for ruggedness and endurance seen in the industrial market.

The series uses pure industrial-grade Toshiba 3D TLC NAND flash with a rated P/E cycle number of 3000, ensuring solid longevity, while the fully in-house designed firmware is geared towards industrial usage. The SSDs uses direct write, and avoids using SLC cache which eventually causes an SSD performance drop and bloated P/E cycle numbers. Furthermore, the firmware can be customized to a large degree to suit any specialized requirement.

The series includes two product lines: the DRAM-less 3TE7 and the 3TG6-P with integrated DRAM using a Marvell controller. The product lines are available in capacities up to 1TB and 2TB respectively. They can both be fitted with Innodisk’s trio of power stabilizing technologies iCell™, iPower Guard™ and iData Guard™ to further strengthen data integrity in areas susceptible to power fluctuations.

The 3D NAND SSDs also use End-to-End Power Path Protection that ensures error correction at every data transfer point with the host and within the drives themselves. For more sensitive data, drives that utilize AES encryption are available with in-house designed software for easier deployment and management.

pSemiTM Corporation (formerly Peregrine Semiconductor), a Murata company focused on semiconductor integration, announces volume production of the PE43508 digital step attenuator (DSA). This mmWave product is the world’s first single-chip silicon-on-insulator (SOI) DSA to support the entire 9 kHz to 55 GHz frequency range. Ideal for 5G test and measurement applications, the PE43508 exemplifies pSemi’s high-performance capabilities at mmWave frequencies. The 55 GHz DSA maintains a monotonic response across the entire frequency range and features low insertion loss, low attenuation error and good return loss.

“At the IMS 2018 exhibition in June, we introduced the newest product in the pSemi high-frequency portfolio—a mmWave digital step attenuator,” says Jim Cable, CEO at pSemi. “As we announce volume production, I am excited to share that we are extending the operating frequency range of the PE43508 to 55 GHz. After additional testing, we concluded the original 50 GHz DSA name was selling this impressive product short. The PE43508 delivers exceptional performance beyond 50 GHz, further supporting pSemi’s claim that RF SOI can deliver a high-performing and reliable solution at high frequencies. It also demonstrates pSemi’s superior engineering talents and process capabilities in mmWave design.”

The 55 GHz DSA joins pSemi’s high-frequency portfolio which includes a 40 GHz switch (PE42524) and two 60 GHz switches (PE42525 and PE426525) based on the same UltraCMOS® technology platform. These monolithic ICs are ideal for applications, such as test and measurement and 5G wireless infrastructure, and can be used in more traditional high-frequency applications, such as very small aperture satellite terminals.

Features, Packaging, Pricing and Availability
The PE43508 is a 6-bit, 50-ohm DSA that offers wideband support from 9 kHz to 55 GHz. The PE43508 covers a 31.5 dB attenuation range in 0.5 dB and 1 dB steps, and it is capable of maintaining 0.5 dB and 1 dB monotonicity through 55 GHz. The PE43508 also delivers glitch-safe attenuation state transitions, meaning no increased power spike during a state transition.

The PE43508 has an extended temperature range from −40°C to +105°C, an HBM ESD rating of 1 kV and an easy-to-use digital control interface supporting both serial addressable and parallel programming. The DSA supports 1.8 V control signals and has an optional VSS_EXT bypass mode.

Offered as a flip-chip die, volume-production parts, evaluation kits and samples are available now. For 1K-quantity orders, each PE43508 is $50 USD.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $122.7 billion during the third quarter of 2018, an increase of 4.1 percent over the previous quarter and 13.8 percent more than the third quarter of 2017. Global sales for the month of September 2018 reached $40.9 billion, an uptick of 2.0 percent over last month’s total and 13.8 percent more than sales from June 2017. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Three-quarters of the way through 2018, the global semiconductor industry is on pace to post its highest-ever annual sales, comfortably topping last year’s record total of $412 billion,” said John Neuffer, president and CEO, Semiconductor Industry Association. “While year-to-year growth has tapered in recent months, September marked the global industry’s highest-ever monthly sales, and Q3 was its top-grossing quarter on record. Year-to-year sales in September were up across every major product category and regional market, with sales into China and the Americas continuing to lead the way.”

Regionally, sales increased compared to September 2017 in China (26.3 percent), the Americas (15.1 percent), Europe (8.8 percent), Japan (7.2 percent), and Asia Pacific/All Other (2.4 percent). Sales were up compared to last month in the Americas (6.0 percent), China (1.8 percent), and Europe (1.2 percent), but down slightly in Asia Pacific/All Other (-0.1 percent) and Japan (-0.6 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

September 2018
Billions
Month-to-Month Sales
Market Last Month Current Month % Change
Americas 8.68 9.20 6.0%
Europe 3.53 3.57 1.2%
Japan 3.39 3.37 -0.6%
China 14.10 14.35 1.8%
Asia Pacific/All Other 10.43 10.42 -0.1%
Total 40.12 40.91 2.0%
Year-to-Year Sales
Market Last Year Current Month % Change
Americas 7.99 9.20 15.1%
Europe 3.28 3.57 8.8%
Japan 3.14 3.37 7.2%
China 11.36 14.35 26.3%
Asia Pacific/All Other 10.18 10.42 2.4%
Total 35.95 40.91 13.8%
Three-Month-Moving Average Sales
Market Apr/May/Jun Jul/Aug/Sept % Change
Americas 8.34 9.20 10.2%
Europe 3.67 3.57 -2.7%
Japan 3.39 3.37 -0.8%
China 13.59 14.35 5.6%
Asia Pacific/All Other 10.32 10.42 1.0%
Total 39.31 40.91 4.1%

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom and analog/mixed-signal (AMS) IC design tools have achieved certification for Samsung Foundry’s 7nm Low Power Plus (7LPP) process technology. This certification ensures Cadence and Samsung Foundry mutual customers of a highly automated circuit design, layout, signoff and verification flow with full extreme ultraviolet lithography (EUV) support. This certification complements the earlier announced certification of the Cadence® full-flow digital and signoff tools on Samsung 7LPP process technology.

The Cadence custom and AMS flow includes the Virtuoso® Analog Design Environment (ADE), Virtuoso Schematic Editor, Virtuoso Layout Suite with its Advanced-Node Platform, Virtuoso Space-Based Router, Spectre® Circuit Simulator, Voltus™-Fi Custom Power Integrity Solution, Quantus™ Extraction Solution, Physical Verification System, Litho Physical Analyzer, Cadence CMP Predictor and LDE Electrical Analyzer. These tools can be used throughout the complete custom AMS flow, including:

  • Custom layout design: An advanced, electro-migration and parasitic-aware environment that includes device and module generation, automated placement and routing, layout editing, and dynamic DRC checking with Virtuoso Integrated PVS DRC, interactive PVS metal fill, in-design DFM flows for LDE, process hotspot repair (PHR), pattern analysis and optimization, and chemical mechanical polishing (CMP) check, as well as support for correct-by-design multiple patterning flow.
  • Post-layout parasitic simulation and IR drop (IREM) analysis and integrated signoff: Including parasitic extraction, design rule checks, layout versus schematic checks, dummy metal fill and programmable electrical rule checks (PERC).
  • AMS design: Digital standard cell placement, pin optimization and automated space-based routing.

“In close collaboration with Samsung, we have delivered a certified, integrated flow for custom and AMS design at 7LPP technology based on our industry-leading Virtuoso and Spectre platforms,” said Wilbur Luo, Cadence vice president, product management, analog/custom marketing. “Samsung customers can now take advantage of the most advanced features for circuit design, performance and reliability verification, and automated layout, block and chip integration for custom and digitally controlled analog designs.”

“By working closely with Cadence, we can provide our customers the most advanced FinFET performance for their custom and AMS chip designs,” said Ryan Lee, vice president of Foundry Marketing at Samsung Electronics. “Cadence helps us offer our customers the best power, performance and area for their leading-edge designs.”

“2017 was an unprecedented year for semiconductor industry,” commented Santosh Kumar, Director of Packaging, Assembly and Substrates at Yole Korea, part of Yole Développement (Yole). “The market grow by 21.6% year-to-year to reach record of almost US$412 billion.”

Under this dynamic context, the advanced packaging industry is playing a key role, offering huge opportunities of innovation for the companies involved. According to Yole’s analyst, Santosh Kumar, the advanced packaging market should reach about US$ 39 billion in 2023.

The market research and strategy consulting company Yole, releases this month, its famous report, Status of the Advanced Packaging Industry. Santosh Kumar, with the help of the advanced packaging team at Yole, proposes today an impressive 2018 edition with key market trends, the description of technology evolution, a detailed analysis of the competitive landscape.

For the 1st time, this technology & market report includes a specific section dedicated to the advanced packaging technologies in the new semiconductor era. It offers a short term and long term outlook, with detailed roadmaps. It also details the impact of front-end scaling on advanced packaging. In addition Yole’s team points out the competitive landscape, with disruption and opportunities, detailed supply chain, production splits by manufacturers.

“This report is part of our key advanced packaging technology & market analyses,” asserts Emilie Jolivet, Director, Semiconductor & Software at Yole. “Thanks to this report, we built a strong reputation and became step by step one of the major consulting companies in this area.”

To highlight results of this new advanced packaging report, Yole combines the release of this report with the relevant interview of a key advanced packaging player, Amkor Technology. OSATs clearly play a significant role in the evolution of the industry and Ron Huemoeller, Corporate Vice President, Head of WWRD & Technology Strategy and Christopher A. Chaney, IRC, Vice President, Investor Relations, both at Amkor Technology agreed to share their vision with @Micronews readers: More.

Between 2017 and 2023, the total packaging market’s revenue will grow at 5.2% CAGR . In parallel, over the same period, the advanced packaging market will grow at 7% CAGR. On the other hand, the traditional packaging market will grow at a lower CAGR of 3.3%.

Of the different advanced packaging platforms, 3D TSV and fan-out will grow at rates of 29% and 15%, respectively. Flip-chip, which constitutes the majority of the advanced packaging market, will grow at CAGR of almost 7%. Meanwhile, fan-in WLP will grow at a 7% CAGR from 2017 – 2023, mainly led by mobile.

“Advanced packages will continue their important role of addressing high-end logic and memory in computing and telecom, with further penetration in analog and RF in high-end consumer/mobile segments,” analyses Santosh Kumar from Yole. All of this while eyeing opportunities in the growing automotive and industrial segments.

What’s happened in 2017? According to Yole, two advanced packaging roadmaps are foreseen:
•  Scaling: going to sub10 nm nodes
•  And functional: staying above 20nm nodes.

In parallel, the semiconductor industry is developing products on both of them. Under this favorable context, advanced semiconductor packaging is seen as a way to increase the value of a semiconductor product, adding functionality, maintaining/increasing performance while lowering cost.
Both roadmaps hold more multi-die heterogeneous integration including SiP and higher levels of package customization in the future. A variety of multi-die packaging is developing in both high and low end, for consumer, performance and specialized applications. Heterogeneous integration has created opportunities for both the substrate and WLP based SiP.

2017 also show the merger of 3 competitive areas that will continue to develop: PCB vs. substrate, substrate vs. Fan-Out and Fan-Out vs. 2.5D/3D.

It will be difficult to repeat 2017 performances and Yole’s Semiconductor & Software team went further in its investigation this year again, to propose you today a comprehensive analysis of this evolution. Lot of questions are still pending and the Status of the Advanced Packaging industry will give you a deep understanding of the megatrends impacting this industry, the related business opportunities and technical innovations. A detailed description of this report is available on i-micronews.com, advanced packaging reports section.

Silvaco welcomed Dr. Babak Taheri as CTO and Executive Vice President of Products. He brings three decades of engineering and leadership experience, with a track record of transforming and scaling global technology platforms. This new position at Silvaco is designed to drive innovation and project execution while increasing the synergy between Silvaco’s products and services across the company.

Dr. Taheri will be taking Silvaco’s advanced positions in FinFET and beyond nodes, novel materials, emerging memory and advanced display technologies, to the next level. He is also tasked with extending Silvaco’s market leadership in analog mixed signal, custom IC design and power devices. Furthermore, Dr. Taheri’s vast expertise in IP Products will accelerate Silvaco’s IP business growth.

Dr. Taheri said, “Silvaco has tremendous potential and I look forward leading Silvaco technologies as their CTO and EVP of products. My focus will be on TCAD, EDA, IP products, IP security, and related services. Silvaco has an impressive history of innovative solutions. I am excited about the opportunity to help bring the next level of innovation for products and services while deepening relationships with our customers and partners. Silvaco has a compelling combination of ground-breaking software solutions, global reach, and talented employees that form a strong foundation for industry leadership and success.”

Earlier in his career, Dr. Taheri has served as VP/GM of the Sensor Solutions Division at Freescale Semiconductor (now NXP). He also held VP/GM roles at Cypress Semiconductor and Invensense (now TDK), as well as key roles at SRI International and Apple.

David Dutton, CEO of Silvaco, welcomes Babak to the Team: “Babak Taheri is joining at the perfect time in Silvaco’s growth as a technology company in the demanding semiconductor industry,” said Dutton. “Babak understands our products and how to make them work together in a cohesive solution for the changing needs of our customers. I am looking forward to our partnership in growing Silvaco’s leadership in the industry.”

Babak has a Ph.D. in EECS and Neurosciences from UC Davis, a 30-year career spanning Engineering, R&D, Corporate IP Development/Management, MEMS/Sensors/Actuator Products, Memory Products and more, including 20 Published articles and 28 patents to his name. Silvaco welcomes Babak Taheri to its Executive Team to help drive Silvaco’s Vision, Mission and strategies.

Samsung Electronics Co., Ltd. today announced several groundbreaking additions to its comprehensive semiconductor ecosystem that encompass next-generation technologies in foundry as well as NAND flash, SSD (solid state drive) and DRAM. Together, these developments mark a giant step forward for Samsung’s semiconductor business.

Unveiled at its annual Samsung Tech Day include:

  • 7nm EUV process node from Samsung’s Foundry Business, providing significant strides forward in power, performance and area.
  • SmartSSD, a field programmable gate array (FPGA) SSD, that will offer accelerated data processing and the ability to bypass server CPU limits.
  • QLC-SSD for enterprise and datacenters that offer 33-percent more storage per cell than TLC-SSD, consolidating of storage footprints and improving total cost of ownership (TCO).
  • 256-gigabyte (GB) 3DS (3-dimensional stacking) RDIMM (registered dual in-line memory module), based on 10nm-class 16-gigabit (Gb) DDR4 DRAM that will double current maximum capacity to deliver higher performance and lower power consumption.

“Samsung’s technology leadership and product breadth are unparalleled,” said JS Choi, President, Samsung Semiconductor, Inc. “Bringing 7nm EUV into production is an incredible achievement. Also, the announcements of SmartSSD and 256GB 3DS RDIMM represent performance and capacity breakthroughs that will continue to push compute boundaries. Together, these additions to Samsung’s comprehensive technology ecosystem will power the next generation of datacenters, high-performance computing (HPC), enterprise, artificial intelligence (AI) and emerging applications.”

Advanced Foundry Technology

Initial wafer production of Samsung’s 7nm LPP (Low Power Plus) EUV process node represents a major milestone in semiconductor fabrication. The 7LPP EUV process technology provides great advances, including a respective maximum of 40-percent area reduction, 50-percent dynamic power reduction and 20-percent performance increase over 10nm processes. The 7LPP process represents a clear demonstration of the foundry business’ technology roadmap evolution, providing Samsung’s customers a direct path forward to 3nm.

Powering Server-less Computing

Samsung enables the most advanced providers of server-less computing through products including the new SmartSSD, quad-level cell (QLC)-SSD, 256GB 3DS RDIMM as well as High Bandwidth Memory (HBM) 2 Aquabolt. By accelerating data processing, bypassing server CPU limits and reducing power demands, these products will enable datacenter operators to continue to scale at faster speeds while containing costs.

Samsung’s industry-leading flash memory products for future datacenters will also include Key Value (KV)-SSD and Z-SSD. KV-SSD eliminates block storage inefficiency, reducing latency and allowing datacenter performance to scale evenly when CPU architectures max out. The company’s next-generation Z-SSD will be the fastest flash memory ever introduced, with dual port high availability, ultra-low latency and a U.2 form factor, designed to meet the emerging needs of enterprise clients. Z-SSD will also feature a PCIe Gen 4 interface with a blazing-fast 12-gigabytes-per-second (GB/s) sequential read, which is 20 times faster than today’s SATA SSD drives.

Accelerating Application Learning

A range of revolutionary Samsung solutions will enable the development of upcoming machine learning and AI technologies. The Tech Day AI display highlighted astounding data transfer speeds of 16Gb GDDR6 (64GB/s), ultra-low latency of Z-SSD and industry-leading performance of Aquabolt, which is the highest of any DRAM-based memory solution currently in the market. Together, these solutions help Samsung’s enterprise and datacenter clients open new doors to application learning and create the next wave of AI advancements.

Streamlining Data Flow

Samsung’s new solutions will enable not just faster speeds and higher performance but also improved efficiency for its enterprise clients. Enterprise products on display at Tech Day included D1Y 8Gb DDR4 Server DRAM, which incorporates the most advanced DRAM process, resulting in lower power usage. Samsung’s 256GB 3DS RDIMM also helps to improve enterprise performance and enables memory-intensive servers capable up to 16-terabytes (TB).

Additionally, Samsung’s dual-port x4 PCIe Gen 4 32TB SSD offers 10GB/s performance. Samsung’s 1Tb QLC-SSD presents a cutting-edge storage option for enterprise clients with competitive efficiency when compared to hard disk drives (HDD), while KV-SSD allows server performance to scale even as CPU architectures max out, also providing a competitive TCO, write amplification factor (WAF) improvement and scalability.

Breaking Performance Barriers

With their leading-edge specs, Samsung’s QLC-SSD, Z-SSD and 8GB Aquabolt help high-performance computing clients blast through performance barriers and reach new heights. The 8GB Aquabolt provides the fastest data transmission speed and highest performance of any DRAM-based memory solution on the market today at 307GB/s per HBM cube. QLC-SSD and Z-SSD, both powerful on their own, are also offered in a tiered storage solution that results in a 53-percent increase in overall system performance.

Enabling Future Innovation

Emerging tech requires the most innovative and flexible components. Samsung’s SmartSSD will increase speed and efficiency, and lower operating costs by pushing intelligence to where data lives. Movement of data for processing has traditionally caused increased latency and energy consumption while reducing efficiency. Samsung’s new SmartSSDs will overcome these issues by incorporating an FPGA accelerator into the SSD unit. This allows for faster data processing through bypassing server CPU limits. As a result, SmartSSDs will have higher processing performance, improved time-to-insight, more virtual machines (VM), scalable performance, better de-duplication and compression, lower power usage and fewer CPUs per system.

Unparalleled Product Ecosystem

Samsung’s comprehensive product portfolio with state-of-the-art solutions set new standards for data processing speed, capacity, bandwidth and energy conservation. By leveraging such solutions, data centers, enterprise companies, hyper-scalers and emerging tech platforms are able to configure product solutions based on their requirements and develop exciting new tech offerings such as 5G, AI, enterprise and hyperscale data centers, automotive, networking and beyond.

Samsung will continue to push boundaries in tomorrow’s semiconductor technologies through innovations such as its sixth-generation V-NAND built on a single structure, or with ‘1-stack technology,’ and sub-10nm DRAM with EUV for super-high density and performance.

Experts across the industry, including Apple co-founder, Steve Wozniak, were invited at Samsung Tech Day to address the advancements and challenges in today’s semiconductor market, and offer insights for the future of semiconductors. More than 400 customers, partners and industry influencers attended the event.

MagnaChip Semiconductor Corporation (“MagnaChip”) (NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor platform solutions, today announced the introduction of a new High-Voltage Super Junction MOSFET with a 900V breakdown voltage and low total gate charge (Qg) (“”90R1K4P”). The device with two package types, I-PAK and D-PAK, will sample to customers in November 2018 and will be manufactured in high volume in early first quarter of next year.

90R1K4P features the maximum peak voltage of 950V and a breakdown voltage as high as 900V, which enables enhanced system stability and reliability. It is well-suited for high-voltage applications such as:

  • an auxiliary power supply for industrial smart metering, which uses a three-phase input power to alternate current electric power generation, transmission, and distribution.
  • the lighting of flyback topology in both AC/DCand DC/DC high-speed switching converters.
  • a power supply for lighting equipment due to its characteristics of high stability that help prevent an unstable system condition that could lead to outages.

90R1K4P increases its switching speed due to its low total gate charge (Qg), which reduces heat generation in the system, keeps power loss down and improves energy efficiency. It also enables smaller form factors than the High-Voltage Planar MOSFET, since the die size of 90R1K4P is more than 50% smaller under the same condition of conduction loss.

To enable the use of 90R1K4P product in small form factors, MagnaChip will house the device in a small I-PAK package type under the code MMIS90R1K4P. As a result of the die size reduction and choice of packaging, this new MOSFET has the potential to be adopted in a wide range of applications.

Moreover, to ensure 90R1K4P product can be adopted for applications where space is at a premium, the company also can mount the Super Junction MOSFET into the slim SMD (Surface-Mount Devices) package type, D-PAK. It will be available under the code MMD90R1K4P.

“MagnaChip’s High-Voltage Super Junction MOSFET with a high breakdown voltage and a low total gate charge (Qg) will provide customers with high system reliability and energy efficiency,” said YJ Kim, CEO of MagnaChip. “We will continue to develop products based on the newly launched High-Voltage Super Junction MOSFET and extend our product portfolio with a diverse line of Super Junction MOSFETs with improved performance.”