Category Archives: 3D Integration

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $25.8 billion for the month of April 2016, a decrease of 1.0 percent from last month’s total of $26.1 billion and 6.2 percent lower than the April 2015 total of $27.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects decreased annual semiconductor sales in 2016, followed by slight market growth in 2017 and 2018.

“Global semiconductor sales decreased marginally in April, continuing a recent trend of market sluggishness driven by soft demand and a range of macroeconomic headwinds,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Despite a cumulative decrease across all product categories, year-to-year sales of microprocessors and analog products increased modestly, perhaps foreshadowing stronger sales ahead. The latest industry forecast suggests global sales may indeed rebound somewhat in the second half of 2016, but still fall short of last year’s total. The global market is projected to grow slightly in 2017 and 2018.”

Regionally, year-to-year sales increased in Japan (2.2 percent) and China (0.3 percent), but decreased in Asia Pacific/All Other (-8.2 percent), Europe (-8.6 percent), and the Americas (-14.8 percent). Compared with last month, sales were up slightly Japan(0.2 percent) and Asia Pacific/All Other (0.1 percent), but down in Europe (-0.8 percent), China (-1.8 percent), and the Americas (-2.2 percent).

Additionally, SIA today endorsed the WSTS Spring 2016 global semiconductor sales forecast, which projects the industry’s worldwide sales will be $327.2 billion in 2016, a 2.4 percent decrease from the 2015 sales total. WSTS projects year-to-year decreases across all regional markets for 2016: Europe (-0.1 percent), Asia Pacific (-1.2 percent), Japan (-1.7 percent), and the Americas (-7.3 percent). On the positive side, WSTS predicts growth in 2016 for several semiconductor product categories, including discretes, analog, and MCU products.

Beyond 2016, the semiconductor market is expected to grow at a modest pace across all regions. WSTS forecasts 2.0 percent growth globally for 2017 ($333.7 billion in total sales) and 2.2 percent growth for 2018 ($340.9 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

April 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

4.89

4.78

-2.2%

Europe

2.66

2.64

-0.8%

Japan

2.59

2.60

0.2%

China

7.93

7.79

-1.8%

Asia Pacific/All Other

8.02

8.03

0.1%

Total

26.09

25.84

-1.0%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.61

4.78

-14.8%

Europe

2.89

2.64

-8.6%

Japan

2.54

2.60

2.2%

China

7.77

7.79

0.3%

Asia Pacific/All Other

8.74

8.03

-8.2%

Total

27.56

25.84

-6.2%

Three-Month-Moving Average Sales

Market

Nov/Dec/Jan

Feb/Mar/Apr

% Change

Americas

5.41

4.78

-11.7%

Europe

2.70

2.64

-2.4%

Japan

2.49

2.60

4.3%

China

8.42

7.79

-7.4%

Asia Pacific/All Other

7.87

8.03

2.0%

Total

26.89

25.84

-3.9%

Media Contact 

Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

By Dr. Phil Garrou, Contributing Editor

Dongkai ShangguanDr. Dongkai Shangguan is currently the Chief Marketing Officer of STATS ChipPAC. Previously, Dongkai served as the founding CEO of the National Center for Advanced Packaging Co., Ltd. (“NCAP China”), worked for 10 years at Ford Motor Company in various technical and management functions, and for 11 years at Flextronics as Corporate Vice President of Global Advanced Technology.

SST: In 2015, STATS ChipPAC was acquired by JCET (Jiangsu Changjiang Electronics Technology Co., Ltd.) and organized as a business unit. Can you describe some of the personnel changes that have taken place?

DS: Following the acquisition, STATS ChipPAC became a business unit under the JCET Group with the same organizational structure as what we had prior to the completion of the deal. Dr. Han Byung Joon (BJ) was appointed to be Co-President and Chief Executive Officer with Tan Lay Koon. Dr. Han had served as our Chief Technology Officer since 1999. He and Lay Koon had worked very closely over the years and together led the company through the first three months following the acquisition. After the initial transition period, Dr. Han became the President and CEO for the company. Reporting directly to JCET Group Chairman Wang XinChao, Dr. Han has full responsibility for the business results of STATS ChipPAC. He also serves as Chairman of the Technology Strategy Council for the JCET Group.

In August of last year, there were two additional executive appointments. Woo Kwek Kiong (KK) was appointed Senior Vice President and Chief Financial Officer for the Company. Prior to joining us, KK was Chief Financial Officer at Advanpack Solutions Pte Ltd and ASTI Holdings Limited. Il Kwon (IK) Shim was promoted to Senior Vice President and Chief Technology Officer. IK has been with STATS ChipPAC since 2000 and prior to his promotion served as Head of Research and Development.

In December, Cindy Palar was appointed as Managing Director of STATS ChipPAC Singapore (SCS), where our FlexLineTM manufacturing is located. Cindy has been with the Company since 1999 and has held a number of senior management positions in Strategic Marketing, Pricing, Product Line Management and Demand/Capacity Planning.

JCET chose a light integration strategy for the acquisition in order to keep the focus on our customers and minimize any disruptions with our service and support. The organizational structure and operating systems for STATS ChipPAC have remained the same as before the acquisition, providing a smooth transition following the deal completion. 

SST: We know that JCET is the largest semiconductor packaging and test provider in China through JCAP (Jiangyin Changdian Advanced Packaging Co., Ltd. ) a subsidiary of JCET which provides wafer bump (solder bump, gold bump, pillar bump), Wafer Level Chip Scale Packaging, assembly and test. Can you differentiate between what JCET SCP and JCET JCAP will offer the customer as divisions of JCET?

DS: JCET has extremely solid credentials in turnkey wirebond packaging, servicing a broad range of applications with very good relationship with a large number of customers, particularly in China. JCET focuses primarily on leaded wirebond and flip chip packaging including assembly of discrete packages.

JCAP provides turnkey services including wafer bump, probe and assembly. JCAP is a leader in advanced wafer bump technology (solder bump, gold bump, copper pillar bump) and Wafer Level Chip Scale Packaging (WLCSP).

STATS ChipPAC, with the strongest IP portfolio in the OSAT industry for many years, clearly brings very strong advanced packaging technologies to the JCET Group, particularly in Fan-out Wafer Level Packaging (FOWLP), laminate-based Flip Chip, package-on-package (PoP), and System-in-Package (SiP) capabilities. STATS ChipPAC will continue to be the FOWLP and SiP center of competency for the JCET Group, and all laminate based flip chip activities are being consolidated into STATS ChipPAC factories.

As a combined Group, the JCET Group is now able to address a much broader total available market (TAM). While each JCET Business Unit has its area of expertise, we are already seeing benefits of cross-selling services to our customers, particularly in China.

SST:. Will the SCP product focus change any in the coming years? Can you share any packaging roadmaps?

DS: No, the merger does not change STATS ChipPAC’s focus or roadmap at all. Our focus for the coming years continues to be on expanding our SiP and FOWLP business, in addition to our core turnkey wirebond, flip chip and PoP packaging business areas. STATS ChipPAC is firmly committed to our industry leading eWLB technology as supported by our eWLB line expansion occurring throughout this year. While we will continue to develop advanced 2.5D and 3D FOWLP package designs, we will be implementing further process optimizations, such as panel manufacturing, which will drive significantly better capital intensity and a lower unit cost for larger body sizes.

SST: Have/will SCP manufacturing facilities in Singapore moved/move to China?

DS: There is currently no plan for any relocation. Our STATS ChipPAC Singapore (SCS) facility remains the hub of the JCET Group’s effort in FOWLP as well as being our largest Test site. SCS is an important location for several Tier 1 customers who prefer having Singapore as part of their supply chain for regional diversity and other commercial reasons.

SST: What is JCET relationship to SMIC? We noticed with interest that SMIC recently increased its ownership position to 14.25% making it the single largest owner of JCET.

DS: JCET has entered into asset purchase transaction whereby it will acquire the remaining shareholding in STATS ChipPAC from the National Integrated Circuit Fund and SMIC. Concurrent to the asset purchase transaction, JCET has entered into a subscription agreement with SMIC whereby SMIC will subscribe for approximately 150 million JCET shares for a consideration of about US$400 million. After the proposed transaction, SMIC will have a 14.25% stake in JCET Group, resulting in JCET owning 100% of STATS ChipPAC. This transaction will strengthen the equity base of JCET with stronger shareholders, and create better operational synergies. These transactions have no significant impact to STATS ChipPAC’s organizational structure or management team, and will not impact our service to our customers.

SST: China’s government policy “National Guidelines for Development and Promotion of the IC Industry,” which was released in June of 2014 calls for expansion and vertical integration of the domestic semiconductor value chain with domestic sales revenue targets of $56B by 2020. How does packaging fit into these overall goals?

DS: The Chinese government correctly identifies packaging and test as critical parts of the overall semiconductor ecosystem and, therefore, packaging is an integral part of these goals. As the largest OSAT in China, the JCET Group is uniquely positioned to participate in and capitalize on the emergence and growth of the Chinese semiconductor ecosystem. With the addition of the advanced packaging technologies from STATS ChipPAC, the JCET Group is well positioned to help enable this growth.

SST: What new products or technologies would you like to share with our readers?

DS: We are very proud to have passed a significant milestone for 1B units shipped for our industry leading eWLB FOWLP product. The eWLB platform has an incredible amount of traction now and the technology roadmap around this platform is resonating with an increasingly diverse range of customers, from its traditional base in mobile communications into areas such as Advanced Driver Assistance Systems (ADAS) in automobiles and bio-processors in the wearables market. Furthermore, as a platform for system integration, enabled by finer L/S and multiple RDL’s, eWLB SiP in various configurations (such as multi-die with passives, PoP, 2.5D, etc) has a tremendous future.

SiP capabilities are incredibly important to those customers driving miniaturization as well as integration and modularization of functionality. This represents a major new source of TAM for the OSAT industry. We feel we are extremely well positioned in this area, as we have developed comprehensive capabilities, including design and simulation, advanced packaging technologies, high density SMT component placement, advanced molding for complex topographies, conformal shielding, and system level test, for a wide variety of SiPs/modules in multiple market segments. Depending on the application requirements and product complexity, we have developed various SiP configurations ranging from conventional 2D modules with multiple active and passive components, interconnected through flip chip, wire bonding, and SMT, to more complex modules such as Package-in-Package (PiP), eWLB Package-on-Package (eWLB PoP), 2.5D and 3D solutions.

We anticipate that our strength in these areas coupled with our unique position in the highest growth region, China, will propel our growth well beyond the industry average going forward.

Communication and computer systems are forecast to be two of the three largest system applications for IC sales in every global region—Americas, Europe, Japan, and Asia-Pacific—this year, according to data presented in the upcoming Update to the 2016 edition of IC Insights’ IC Market Drivers, A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits. Communications applications are expected to capture nearly 43% of IC sales in Asia-Pacific and 39% of the revenue in the Americas region this year. Communications and computer applications are forecast to tie as the largest end-use markets in Japan while in Europe, communications apps are forecast to trail computer applications with 23.5% of ICs sales (Figure 1).

Figure 1

Figure 1

Consumer systems are forecast to be the third-largest end-use category for ICs in the Americas and Asia-Pacific regions in 2016. Automotive is expected to be the second-largest system application for ICs in Europe, which has been a bastion for automotive electronics systems development. Each of Europe’s three largest IC manufacturers—Infineon, ST, and NXP—is annually ranked among the top suppliers of automotive ICs. In addition, the automotive segment is forecast to edge ahead of the consumer segment in Japan in 2016 to become the third-largest end-use market for ICs in that country.

Collectively, communications, computers, and consumer systems are projected to account for 86.4% of IC sales in the Americas this year (an increase of half a percentage point from 2015) and 89.5% in Asia-Pacific (a decrease of half a percentage point from 2015). This year, communications, computer, and automotive applications are forecast to represent 73.5% of IC sales in Japan and 78.8% of IC sales in Europe, the same percentage as in 2015.

For more than three decades, computer applications were the largest market for IC sales but that changed in 2013 when the global communications IC market took over the top spot due to steady strong growth in smartphones and weakening demand for desktop and notebook personal computers. Figure 2 shows that globally, communications systems are now forecast to represent 39.3% of the $291.3 billion IC market in 2016 compared to 34.7% for computers, and 10.7% for consumer, which has gradually been losing marketshare for several years. IC sales to the automotive market are forecast to represent only about 7.4% of the total IC sales this year but from 2015-2019, this segment is projected to rise by a compound average growth rate (CAGR) of 8.0%, fastest among all the end-use applications.

Figure 2

Figure 2

Additional details on end-use markets for ICs are included in the 2016 edition of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.

Tessera Technologies, Inc. announced today that it and certain of its subsidiaries filed legal proceedings for patent infringement in both domestic and international jurisdictions against Broadcom and, in some cases, against certain of Broadcom’s customers and distributors.

The proceedings are in the United States International Trade Commission, the U.S. District Court for the District of Delaware, and courts in Germany and the Netherlands, alleging infringement of a total of eight patents.

Tessera first reached out to Broadcom several years ago to explore technical collaboration on semiconductor technology development, and subsequently to discuss licensing Tessera’s intellectual property. Following a series of in-depth licensing discussions, the parties were unable to reach a licensing arrangement.

“Today’s actions were not taken lightly and are made only after years of effort to reach a fair and equitable resolution without litigation,” said Tom Lacey, CEO of Tessera. “At this point, we believe that litigation is necessary to defend our intellectual property rights. As we have said in connection with other legal matters, we remain willing to negotiate a resolution that fairly compensates Tessera and its shareholders for our valuable intellectual property. However, we are also fully prepared to proceed through the entirety of the legal process, and we remain very confident in our ability to achieve a positive outcome.”

Broadcom is not an existing Tessera customer, and as such the proceedings announced today do not impact Tessera’s second quarter revenue or earnings per share guidance or 2016 full-year revenue guidance. The company expects 2016 litigation expense will remain within its current target operating model based on anticipated case activity for the remainder of the year.

Tessera researches and develops semiconductor and imaging technology that is used in billions of electronic devices. Tessera has a portfolio of over 4,000 patent assets protecting its technologies that it licenses to its customers. The company develops computational imaging and photography, as well as semiconductor packaging and interconnects.

GLOBALFOUNDRIES today announced a next-generation radio-frequency (RF) silicon solution for its Silicon Germanium (SiGe) high-performance technology portfolio. The technology is optimized for customers who need improved performance solutions for automotive radar, satellite communications, 5G millimeter-wave base stations and other wireless and wireline communication network applications.

GLOBALFOUNDRIES’ SiGe 8XP technology is the latest extension to the company’s 130nm high-performance SiGe family and enables customers to develop RF solutions that deliver even faster data throughput, over greater distances, while consuming less power. The advanced technology offers an improved heterojunction bipolar transistor (HBT) performance with lower noise figure, higher signal integrity, and up to a 25 percent increase in maximum oscillation frequency (fMAX) to 340GHz compared to its predecessor, SiGe 8HP.

The complexity and performance demands of high bandwidth communication systems operating in the mmWave frequency bands have created the need for higher performance silicon solutions. This creates opportunities for high-performance SiGe solutions in the RF front end of 5G smartphones and other mmWave phased array consumer applications in addition to the current applications that depend on SiGe for high performance, such as the communications infrastructure base stations, backhaul, satellite and fiber optic networks.

“5G networks promise to bring a new level of innovation to RF SOC design to support high bandwidth data delivery and meet the demands for increased data rates and low latency applications,” said Dr. Bami Bastani, senior vice president of GLOBALFOUNDRIES RF business unit. “GLOBALFOUNDRIES’ SiGe 8HP and 8XP technologies offer an outstanding balance of performance, power, and efficiency that enable customers to develop differentiated RF solutions in next-generation mobile and infrastructure hardware.”

“GLOBALFOUNDRIES’ SiGe technology leadership and comprehensive PDKs enable our designers to develop performance-optimized, differentiated millimeter wave solutions quickly,” said Robert Donahue, Anokiwave CEO. “Utilizing SiGe 8XP allows us to take performance to even higher levels in future-ready mmWave solutions designed to help providers stay ahead of the demands for reliable connectivity, from anywhere, while handling exploding volumes of mobile data traffic.”

With tomorrow’s 5G deployments poised to drive a proliferation of base stations with smaller cell areas, SiGe 8HP and 8XP are designed to help offer a balance of value, power output, efficiency, low noise, and linearity at microwave and millimeter-wave frequencies for differentiated RF solutions in next-generation mobile infrastructure hardware and smartphone RF front ends. GLOBALFOUNDRIES’ SiGe 8HP and 8XP high-performance offerings enable chip designers to integrate significant digital and RF functionality while exploiting a more economical silicon technology base compared to gallium arsenide (GaAs) and higher performance than CMOS.

In addition to high performance transistors for efficient operation at mmWave frequencies, SiGe8HP and 8XP introduce technology innovations that can reduce the die size and enable area-efficient solutions. A new Cu metallization feature provides improved current carrying capabilities with five times the current density at a 100C, or up to 25 degrees C higher operating temperature at the same current density compared to standard Cu lines. In addition, GLOBALFOUNDRIES’ through-silicon-via (TSV) interconnect technology is available.

Synopsys, Inc. today announced that the company’s Custom Compiler tool has been enabled by Samsung for 14 nanometer (nm) LPP and LPC FinFET production. The process delivers high performance for compute-intensive designs and lower power consumption for mobile applications. Custom Compiler is a custom design solution from Synopsys that was announced on March 30th of this year. Custom Compiler support is provided through a jointly developed interoperable process design kit (iPDK)-format design kit. Unified with Synopsys’ circuit simulation, physical verification and digital implementation tools, Custom Compiler provides Samsung 14nm LPP and LPC process users with a comprehensive custom design solution.

“Samsung support for Custom Compiler is very important to our mutual customers,” said Bijan Kiani, vice president of product marketing at Synopsys. “Through close collaboration, the two companies were able to deliver a design kit and set of tool features that enable Custom Compiler’s visually-assisted automation flow for Samsung Foundry customers.”

Custom Compiler shortens the time it takes to complete custom design tasks from days to hours—especially for FinFET process nodes. Its visually-assisted automation leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup. Custom Compiler’s visually-assisted automation provides four types of assistants: Layout, In-Design, Template and Co-Design. Layout Assistants speed layout with user-guided automation of device placement and routing. In-Design Assistants reduce design iterations by catching physical and electrical errors before signoff verification. Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Co-Design Assistants combine the IC Compiler place-and-route tool and Custom Compiler into a unified solution for custom and digital implementation. Custom Compiler is based on the industry standard OpenAccess database. It provides an open environment spanning schematics, simulation analysis and layout. Unified with Synopsys’ circuit simulation, physical verification and digital implementation tools, Custom Compiler provides a comprehensive custom design solution.

IC Insights will release its May Update to the 2016 McClean Report later this month.  This Update includes a discussion of the 1Q16 semiconductor industry market results, an update of the capital spending forecast by company, a review of the IC market by electronic system type, and a look at the top-25 1Q16 semiconductor suppliers (the top 20 1Q16 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 1Q16 is shown in Figure 1.  It includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies. If the three pure-play foundries were excluded from the top-20 ranking, U.S.-based IDM ON Semiconductor ($817 million), China-based fabless supplier HiSilicon ($810 million), and Japan-based IDM Sharp ($800 million) would have been ranked in the 18th, 19th, and 20th positions, respectively.

IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

In total, the top-20 semiconductor companies’ sales declined by 6% in 1Q16/1Q15, one point less than the total worldwide semiconductor industry decline of 7%.  Although, in total, the top-20 1Q16 semiconductor companies registered a moderate 6% drop, there were seven companies that displayed a double-digit 1Q16/1Q15 decline and three that registered a ≥25% fall (with memory giants Micron and SK Hynix posting the worst results).  Half of the top-20 companies had sales of at least $2.0 billion in 1Q16.  As shown, it took $832 million in quarterly sales just to make it into the 1Q16 top-20 semiconductor supplier list.

There was one new entrant into the top-20 ranking in 1Q16—U.S.-based fabless supplier AMD.  AMD had a particularly rough 1Q16 and saw its sales drop 19% year-over-year to $832 million, which was about half the $1,589 million in sales the company logged just over two years ago in 4Q13.  Although AMD did not have a good 1Q16, Japan-based Sharp, the only company that fell from the top-20 ranking, faired even worse with its 1Q16/1Q15 sales plunging by 30%!

In order to allow for more useful year-over-year comparisons, acquired/merged semiconductor company sales results were combined for both 1Q15 and 1Q16, regardless of when the acquisition or merger occurred.  For example, although Intel’s acquisition of Altera did not close until late December of 2015, Altera’s 1Q15 sales ($435 million) were added to Intel’s 1Q15 sales ($11,632 million) to come up with the $12,067 million shown in Figure 1 for Intel’s 1Q15 sales.  The same method was used to calculate the 1Q15 sales for Broadcom Ltd. (Avago/Broadcom), NXP (NXP/Freescale), and GlobalFoundries (GlobalFoundries/IBM).

Apple is an anomaly in the top-20 ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers. Apple’s custom ARM-based SoC processors had a “sales value” of $1,390 million in 1Q16, up 10% from $1,260 million in 1Q15.  Apple’s MPUs have been used in 13 iPhone handset designs since 2007 and a dozen iPad tablet models since 2010 as well as in iPod portable media players, smartwatches, and Apple TV units.  Apple’s custom processors—such as the 64-bit A9 used in iPhone 6s and 6s Plus handsets introduced in September 2015 and the new iPhone 6SE launched in March 2016—are made by pure-play foundry TSMC and IDM foundry Samsung.

Intel remained firmly in control of the number one spot in 1Q16.  In fact, it increased its lead over Samsung’s semiconductor sales from 29% in 1Q15 to 40% in 1Q16.  The biggest moves in the ranking were made by the new Broadcom Ltd. (Avago/Broadcom) and Nvidia, each of which jumped up three positions in 1Q16 as compared to 1Q15.

As would be expected, given the possible acquisitions and mergers that could/will occur this year (e.g., Microchip/Atmel), as well as any new ones that may develop, the top-20 semiconductor ranking is likely to undergo a significant amount of upheaval over the next few years as the semiconductor industry continues along its path to maturity.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has received multiple orders for its GEMINI FB XT automated fusion wafer bonders from multiple leading device manufacturers. The GEMINI FB XT offers wafer-to-wafer alignment accuracy, customizable pre- and post-processing configurations with faster handling and improved process flows that increase throughput by up to 50 percent compared to the previous-generation platform, as well as integrated metrology to maximize yields and productivity in high-volume manufacturing (HVM). These latest orders for the GEMINI FB XT system will support several leading-edge HVM applications, including 3D stacked image sensors, memory stacking, and die partitioning for next-generation 3D system-on-chip (SoC) devices.

GEMINI FB XT Automated Production Fusion Bonding System

GEMINI FB XT Automated Production Fusion Bonding System

Vertical stacking of devices has become an increasingly viable approach to driving continuous improvements in device density and performance without the need for increasingly costly and complex lithography processing. Wafer-to-wafer bonding is an essential process step to enable 3D stacked devices. However, tight alignment and overlay accuracy between the wafers is required to achieve good electrical contact between the interconnected devices on the bonded wafers, as well as to minimize the interconnect area at the bond interface so that more space can be made available on the wafer for producing devices.

“These latest orders for our GEMINI FB XT system from multiple leading manufacturers reflect the fact that our most advanced fusion bonding platform meets critical production requirements for a variety of 3D chip stacking applications, and further demonstrates our leadership in fusion bonding,” stated Hermann Waltl, executive sales and customer support director at EV Group. “Unparalleled wafer-to-wafer alignment accuracy supports IC manufacturers’ efforts to move wafer stacking upstream from back-end-of-line (BEOL) and mid-end-of-line (MEOL) applications to front-end-of-line (FEOL) processing where they can integrate more functionality into their product at the wafer level and further drive down manufacturing costs. The GEMINI FB XT has proven to fulfill the most stringent compatibility requirements and standards of front-end fabs. It also combines the capabilities necessary to bring new bonding technologies, like hybrid bonding for CMOS image sensors, into high-volume production. It is a true testament to our Triple-i philosophy of invent, innovate and implement.”

Leveraging EVG’s XT Frame platform and an equipment front-end module (EFEM), the GEMINI FB XT automated production fusion bonding system is optimized for ultra-high throughput and productivity. It incorporates EVG’s proprietary SmartView NT face-to-face aligner to achieve wafer-to-wafer overlay alignment accuracy below 200 nm (3 sigma), which leads the industry in performance and is essential to enabling 3D integration. In addition, the system can accommodate up to six pre-and post-processing modules for surface preparation, conditioning and metrology steps―such as wafer cleaning, plasma activation, alignment verification, debonding (allowing pre-bonded wafers to be separated automatically and re-processed if necessary) and thermo-compression bonding. This enables the GEMINI FB XT to support fully automated and integrated wafer loading, alignment, bonding and unloading of bonded wafers in HVM environments.

STATS ChipPAC Pte. Ltd., a provider of advanced semiconductor packaging and test services, announced today that it has shipped over one billion fan-out wafer level packages (FOWLP), also known in the industry as embedded Wafer Level Ball Grid Array (eWLB). FOWLP or eWLB is an advanced packaging technology platform that provides ultra-high density interconnection, superior electrical performance and the ability to integrate multiple heterogeneous dies in a cost effective, low-profile semiconductor package.

As the industry was beginning to learn about eWLB in 2008, STATS ChipPAC immediately recognized the significant potential, value and scalability of eWLB and designated it as a key technology for the company.  Within a year, STATS ChipPAC had ramped eWLB to high volume production and was driving a number of technology and manufacturing initiatives in this new packaging approach. STATS ChipPAC has led the industry in eWLB manufacturing capabilities, capacity and technology innovations, particularly in 2.5D and 3D package designs.  STATS ChipPAC became the first company in the semiconductor industry to implement significantly larger than 300mm eWLB wafer manufacturing capabilities and has a strong portfolio of innovative eWLB packages, including small die, large die, multi-die, multi-layer, Package-on-Package (PoP) and System-in-Package (SiP) architectures.

“We differentiated STATS ChipPAC by our unwavering commitment to eWLB technology over the years, beginning with our vision of how this scalable packaging platform can be leveraged to drive performance and size advantages for our customers’ applications.   Over the years we have made significant capital investments and process enhancements to fulfill our vision and raise the bar on manufacturing efficiency and productivity in the industry, adding further value for our customers,” said Dr. Han Byung Joon, President and Chief Executive Officer, STATS ChipPAC. “Although we have achieved multiple milestones with eWLB through the years, shipping over one billion eWLB packages is a testament to the ever expanding customer adoption in the industry and success which we knew was possible with this game changing technology.”

The exceptional success of eWLB in the mobile market, particularly in baseband processors, connectivity devices, Codec devices, RF transceivers and power management integrated circuits (PMICs), is a reflection of the ongoing pressure semiconductor companies face in cost effectively achieving higher input/output (I/O), higher bandwidths and lower power consumption in the smallest possible form factor. STATS ChipPAC has driven a number of eWLB technology achievements such as dense vertical interconnections as high as 500 – 1,000 I/O, very fine line width and spacing down to 2um/2um and ultra thin package profiles below 0.3mm (including solderball) for single packages and below 0.6mm for a stacked PoP with proven warpage control.

With the ability to partition silicon and embed passive devices and vertical interconnects (known as eBar) into a design, eWLB is a powerful integration technology for 2.5D and 3D PoP or SiP solutions for a wide range of new and emerging applications. The compelling performance, size and cost advantages of eWLB are accelerating the adoption of this advanced technology into new markets such as the Internet of Things (IoT) and wearable electronics, Micro-Electro-Mechanical Systems (MEMS) and automotive applications. Examples of new eWLB applications are Advanced Driver Assistance Systems (ADAS) in automobiles and bio-processors in the wearables market.