Category Archives: 3D Integration

Startups and small electronics companies spent $78.3 billion on semiconductors in 2014, representing 23 percent of the total market, compelling semiconductor companies to revisit their sales strategy to focus on the large number of smaller organizations than relying on big deals from large customers, research firm Gartner said.

Gartner estimates that there are more than 165,000 companies that buy semiconductor chips around the world: The top 10 spend nearly 40 percent of the total semiconductor revenue; the top 11 to 100 spend about 30 percent; and the remainder spend 30 percent.

Despite the top 10 accounting for such a large percentage of the market, some of the largest customers have decreased orders in the past five years, challenging the semiconductor vendors that mainly supplied to them.

While Samsung and Apple have significantly increased orders in the same period due to success in the smartphone market, semiconductor vendors are concerned about the risk of relying on large customers such as these.

“The industry has seen some fairly significant disruption in recent years, which has highlighted the risks associated with semiconductor vendors putting all of their focus on a limited number of large customers, when small companies offer highly profitable and stable growth,” said Masatsune Yamaji, Principal Research Analyst at Gartner. “To overcome the risk, some semiconductor vendors have tried to increase their business with small customers, while others are also realizing that they should adjust their strategies to do this.”

China is the fastest-growing among the major small-customer regions, with spending by these organizations on semiconductors growing from US$7.5 billion in 2007 to US$14.9 billion in 2014; growth in the smartphone and media tablet markets has been strong. In the Americas, EMEA and Japan, revenue from each customer is small, but the total market size of small customers is big due to the large number of such customers.

Gartner maintains that the number of customers will significantly increase after 2017, due to future growth of the electronics market and the increase in the number of Internet of Things solutions. It is anticipated that the maker movement, which creates and markets products that are recreated and assembled using unused, discarded or broken products from computer-related devices, will drive the foundation of startups and growth of small customers.

According to Gartner, big deals are not confined to large organizations, with many successful vendors having success in the small-customer market by leveraging distributors. Limited sales resources can be compensated for by aligning with good sales partners. Strong adherence to direct sales restricts the opportunities with small customers, especially among general-purpose semiconductor vendors. In fact, semiconductor distributors earn a large part of their revenue from general-purpose semiconductors.

“Semiconductor vendors should focus more on the high-tier customers and outsource sales activities with small customers to distributors,” said Yamaji. “Distributors can bring various products to market at the same time, so this outsourcing will reduce the load, not just for semiconductor vendors, but also for customers. Some distributors offer end-of-life product delivery services, so vendors should partner with these distributors to help small customers avoid having to order excessive loads.”

Gartner recommends that vendors need to evaluate how much revenue can be expected, compared with the large customers. The importance of the small customers for each vendor differs by its product type and its target sales region, so vendors need to have their own unique goals in the small-customer market.

“Before jumping in, semiconductor vendors also need to be aware of the risks associated with the small-company market, which is prone to shrinking when the macro economy weakens,” said Yamaji. “Revenue can also shrink even faster than large customers in many cases, so it is important to be aware of risk levels regarding any revenue decline. Vendors can reduce the risks by diversifying their customer base, which can spread the liability to allow for lost orders.”

North America-based manufacturers of semiconductor equipment posted $1.59 billion in orders worldwide in July 2015 (three-month average basis) and a book-to-bill ratio of 1.02, according to the July EMDS Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.02 means that $102 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in July 2015 was $1.59 billion. The bookings figure is 5.1 percent higher than the final June 2015 level of $1.52 billion, and is 12.5 percent higher than the July 2014 order level of $1.42 billion.

The three-month average of worldwide billings in July 2015 was $1.56 billion. The billings figure is 0.3 percent higher than the final June 2015 level of $1.55 billion, and is 18.2 percent higher than the July 2014 billings level of $1.32 billion.

“Year-to-date, the bookings and billings reported in the SEMI North American equipment book-to-bill report indicate a solid year for the industry,” said SEMI president and CEO Denny McGuirk. “The outlook for the remainder of the year is somewhat clouded, but we see investments in 3D NAND and advanced packaging as drivers.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
February 2015 

$1,280.1

$1,313.7

1.03
March 2015 

$1,265.6

$1,392.7

1.10
April 2015 

$1,515.3

$1,573.7

1.04
May 2015 

$1,557.3

$1,546.2

0.99
June 2015 (final)

$1,554.9

$1,517.4

0.98
July 2015 (prelim)

$1,559.3

$1,594.3

1.02

Source: SEMI (www.semi.org), August 2015

By Taylor Sholler, SEMI

With trade policy dominating headlines in recent weeks, all eyes were on Maui in the waning days of August as trade ministers from twelve nations convened for perhaps the final time to finalize the Trans-Pacific Partnership (TPP).  Such a pact between Pacific Rim economies would account for 40 percent of the world’s GDP.  However, last-minute hurdles on dairy, autos, and drug provisions proved to be the negotiators’ undoing and ministers left Hawaii with the promise of at least one more round of exhaustive deliberations in the fall.

Such is the pathway for a multilateral agreement like the TPP.  By all accounts, significant progress has been made but getting 12 countries to concur on a high-standard agreement to reduce both tariffs and non-tariff barriers has been arduous to say the least.  The business community remains optimistic nonetheless and will continue to support TPP conclusion— key for the U.S. SEM industries which export 80% of their products— later this year.

Conversely, a sector-specific trade agreement is a bit more straightforward and industry welcomed news just a week earlier that an agreement-in-principle was reached on the expansion of the Information Technology Agreement (ITA).  Originally agreed to in 1996, the ITA fosters free trade in tech and has sorely needed an update to account for the vast progress made through industrial innovation.  While this effort was not without its own obstacles, World Trade Organization (WTO) members came to an agreement in Geneva on July 24th to cut tariffs on more than 200 ICT products after more than three years of negotiations.

This deal between more than 50 nations is seen a major victory for the global economy and the semiconductor equipment and materials industries in particular. SEM-related items account of more than a dozen of the products on the expansion list, including machines and apparatus to manufacture boules, wafers, semiconductor devices and flat panel displays among other products of interest to SEMI members.

WTO trade ministers will now take the list back to their respective capitals for domestic consultations.  By November 1st, participating members must submit a draft schedule detailing their plans for national implementation.  The process should culminate during the WTO’s 10th Ministerial Conference in Nairobi in December 2015, with tariff elimination slated to begin July 2016.

The expanded agreement represents 97 percent of world trade in information technology products—an estimated $1.3 billion annual market.  However, the deal also contains a commitment to work to tackle non-tariff barriers in the IT sector, and to keep the list of products covered under review to determine whether further expansion may be needed to reflect future technological developments.

In what was already been a successful year for trade liberalization, negotiators should soon celebrate implementation of the largest WTO-driven tariff elimination deal in 19 years.  The process has breathed fresh life into the promise of sectoral trade pacts driven by market demand and targeted negotiations.  SEMI has worked closely with ITA negotiators throughout the process to ensure the inclusion of SEM items in the expanded list and this is something we hope to replicate in other market opening accords like the Environmental Goods Agreement as well.

The semiconductor supply chain is comprised of the most innovation and technologically advanced products in the world and trade agreements like the ITA play an exceedingly helpful role in the advancement of our industry.  WTO Director-General Roberto Azevedo and trade negotiators around the world should be commended for their persistence on this important expansion effort. SEMI will continue to support the great work happening in Geneva and elsewhere to remove barriers to trade and improve business operations for our members.

For a complete list of items included in the expanded ITA, please visit:  https://ustr.gov/sites/default/files/ITA-expansion-product-list-2015.pdf

For those with trade-specific questions or concerns, SEMI maintains a dedicated international policy staff, led by Jonathan Davis, Global Vice President of Advocacy ([email protected]).

The Semiconductor Industry Association (SIA) announced former Defense Secretary Leon Panetta will deliver the keynote address at the upcoming SIA Award Dinner, taking place on Thursday, Dec. 3 in San Jose, Calif. Mr. Panetta, who has also served as CIA director, White House chief of staff, director of the Office of Management and Budget (OMB), and as a member of Congress, will offer insight on how the strength of U.S. technology, and a vibrant U.S. semiconductor industry in particular, are critical to our country’s standing in the world and to our economy and national security.

“Leon Panetta is one of America’s most respected leaders and experts on foreign policy,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The semiconductor industry is a global industry with global challenges. We must ensure smart government policies are in place here at home so our industry can remain strong, and we must work closely with counterparts overseas to ensure we can play on a level playing field in the global markets. Given Mr. Panetta’s extensive and diverse experiences on the domestic and international stages, we very much look forward to his keen perspectives on these matters as we welcome him as the keynote presenter at this year’s SIA Award Dinner.”

Mr. Panetta has dedicated much of his life to public service. He served as the 23rd defense secretary from July 2011 to February 2013. Before joining the Department of Defense, Mr. Panetta served as the director of the CIA from February 2009 to June 2011. Previously, he spent 10 years co-directing with his wife, Sylvia, the Leon & Sylvia Panetta Institute for Public Policy, based at California State University, Monterey Bay. The Institute is a nonpartisan, not-for-profit center that seeks to instill the virtues and values of public service in young men and women.

From July 1994 to January 1997, Mr. Panetta served as chief of staff to President Bill Clinton. Prior to that, he was director of OMB, a position that built on his years of work on the House Budget Committee. Mr. Panetta represented California’s 16th (now 17th) congressional district from 1977 to 1993, rising to House Budget Committee chairman during his final four years in Congress. He holds a Bachelor of Arts degree in political science and a law degree, both from Santa Clara University.

The SIA Award Dinner also will feature the presentation of the semiconductor industry’s highest honor, the Robert N. Noyce Award.

By Jeongdong Choe, PhD., TechInsights

A few years ago, some of the semiconductor process and device analysts thought 2D planar NAND Flash would soon be coming to an end due to the scaling limits, especially around the 20nm or sub-20nm generation. Do we still think the 2D NAND Flash technologies have hit the scaling wall? According to TechInsights’ deep-dive analysis on current and future NAND Flash technologies, although 3D V-NAND architecture could help with the scaling limit, we believe the 2D MLC and TLC NAND Flash technologies remain strong and cost effective for 14nm, 12nm and even for single-digit nanometer node.

When it comes to 3D NAND technology, Samsung has been developing and mass-producing 32-tier V-NAND architecture (for technical analysis related to the Samsung 3D V-NAND click here) with MLC and TLC for their 850 PRO and 850 EVO since 2014, although, this is not the final goal for Samsung due to a relatively low yield, process complexity and bit-cost viewpoints. More 3D Flash products may appear at the end of this year, or early in 2016, as major NAND players such as Toshiba, SanDisk, Micron, Intel, and SK-Hynix bring out their 3D products with 24-tier, 32-tier or 48-tier FG (floating gate)/CTF (charge-trap-flash) architecture (Figure 1).

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

Figure 1. 2D and 3D NAND Technology Roadmap (Source: TechInsights Nand Roadmap, download here)

However, the ultimate target for 3D NAND is 128-tier or at least 64-tier structure from the bit-cost viewpoints. In that case, the aspect ratio of Si-channel and common source contacts would be over 80:1, which is a strong burden for process integration engineers. In addition, the uniformity of the 64-tier or 128-tier NAND cell characteristics in a NAND string and their endurance/retention/reliability properties during program/erase operation would be another big challenge for the vertical NAND string architecture.

The scaling limits for 10 nm-class and sub-10 nm 2D planar NAND structures include patterning technology including QPT (Quadruple Patterning Technology), cell-to-cell interference such as cross-talk, poly-Si gap-filling process for control gate (CG), self-aligned STI (SA-STI) for isolation patterning, self-aligned process (SAP) for CG/FG, interconnection methodology including pad layout/design, inter-poly dielectric (IPD) layer engineering, and cell transistor channel/source-drain (S/D) engineering. According to TechInsights’ detailed structural analysis and comparison of 15nm and 16nm NAND flash devices (so called 1Y NAND technology node) such as Samsung 16nm, Toshiba 15nm, Micron 16nm and SK-Hynix 16nm products, we may expect that at least two more next generation 2D planar NAND products having 12nm and less than 12 nm technology would be developed and released from major players near future. As for NAND memory density and die size, Toshiba/SanDisk 15nm TLC products have 1.28 Gb/mm2 which is double from other MLC products although Samsung 32-tier 3D V-NAND TLC products have 1.87 Gb/mm2 (Figure 2).

Fig 2

Figure 2. Comparison of NAND memory density for each product (Source: TechInsights)

For patterning the three finest lines of the NAND cell structure such as active/STI, gate/wordline (CG/FG) and bitline (usually, metal-2 lines), a quadruple patterning technology (QPT) seems to be very mature for each of the major NAND players. They use their own QPT integration on three critical layers with three or four masks, SOH etching and two-step self-align reverse patterning (SARP) process. Although the critical dimensions have a little skew on every four patterns, they have successfully developed QPT integration with less than 1nm CD (Critical Dimension) and it could be extended into 10nm and even single-digit nanometer NAND products. Fortunately and thanks to state-of-the-art anisotropic plasma etching and ALD/CVD technology, uniformly repeated 8nm patterns would be possible for NAND cell array. Figure 3 shows a comparison of DPT/QPT patterns for each product.

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Figure 3. Comparison of DPT and QPT patterns for each product (Source: TechInsights)

Micron uses a 3.3nm thin-FG poly-Si storage node to decrease cell-to-cell interference, while other manufacturers introduce an air-gap process for active, gate wordline (FG/CG) and bitline (metal-2) for thick-FG structure. Especially, the air-gap process has been developed and applied on the channel region of active patterns and FG/CG pillars help decrease the cross-talk.

For an IPD (Inter-Poly Dielectric) or a barrier layer between CG and FG, a multi-layer stacked with thin oxide (O) and nitride (N) layers such as ONO or NONON structure has been used for mid-10 nm class NAND devices, while Micron uses a high-k dielectrics such as HfO/SiO/HfO/Nitrided-SiO which is the same as their 20 nm NAND products. Micron successfully integrated IPD/FG/Tunnel-oxide and decreased FG thickness from 5 nm to 3.3 nm with high-k IPD. It might be further reduced to 10ish nm NAND products by optimizing IPD/FG quantum well structure for their unique thin-FG architecture. A 6 nm tunnel oxide (SiO) is used on Micron, Toshiba/SanDisk and SK-Hynix, while Samsung uses nitrogen-doped oxide in its top and bottom portion.

Triple-row staggered bitline contacts (BC) are used on Toshiba/SanDisk for the first time which is an excellent choice to make things smooth for cell layout and process integration although NAND string overhead is increased from 13% to 19%. Other players still use double-row staggered BC layouts on their 15nm/16nm NAND products (Figure 4).

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Figure 4. Double- and triple-row staggered bitline contacts (Source: TechInsights)

Other barriers to extend 2D planar NAND to 10nm such as CG poly fill-ability, anisotropic etching for SA-FG/STI and CG/FG, cell transistor S/D engineering and leaning effect during the process integration are still there. Nevertheless, major players and their equipment vendors will successfully develop and integrate the 10 nm 2D NAND architecture in a few years.

I believe most of the major NAND players have their own matured process integration capability with assistance from ECC and circuit/layout optimization. 2D NAND technology will be further scaled down to 12nm, 10nm, or even 8ish nm which is more cost-effective than 3D V-NAND for near future NAND products.

HeadshotJeongdong Choe has more than 20 years of experience on semiconductor process and device integration including NAND Flash, DRAM, logic and advanced memory devices at Samsung and SK-Hynix. He works at TechInsights as a consulting engineer especially focusing on memory and logic process integration.

Scientists at Rice University have created a solid-state memory technology that allows for high-density storage with a minimum incidence of computer errors.

The memories are based on tantalum oxide, a common insulator in electronics. Applying voltage to a 250-nanometer-thick sandwich of graphene, tantalum, nanoporous tantalum oxide and platinum creates addressable bits where the layers meet. Control voltages that shift oxygen ions and vacancies switch the bits between ones and zeroes.

The discovery by the Rice lab of chemist James Tour could allow for crossbar array memories that store up to 162 gigabits, much higher than other oxide-based memory systems under investigation by scientists. (Eight bits equal one byte; a 162-gigabit unit would store about 20 gigabytes of information.)

A schematic shows the layered structure of tantalum oxide, multilayer graphene and platinum used for a new type of memory developed at Rice University. The memory device overcomes crosstalk problems that cause read errors in other devices. Credit: Tour Group/Rice University

Details appear online in the American Chemical Society journal Nano Letters.

Like the Tour lab’s previous discovery of silicon oxide memories, the new devices require only two electrodes per circuit, making them simpler than present-day flash memories that use three. “But this is a new way to make ultradense, nonvolatile computer memory,” Tour said.

Nonvolatile memories hold their data even when the power is off, unlike volatile random-access computer memories that lose their contents when the machine is shut down.

Modern memory chips have many requirements: They have to read and write data at high speed and hold as much as possible. They must also be durable and show good retention of that data while using minimal power.

Tour said Rice’s new design, which requires 100 times less energy than present devices, has the potential to hit all the marks.

“This tantalum memory is based on two-terminal systems, so it’s all set for 3-D memory stacks,” he said. “And it doesn’t even need diodes or selectors, making it one of the easiest ultradense memories to construct. This will be a real competitor for the growing memory demands in high-definition video storage and server arrays.”

The layered structure consists of tantalum, nanoporous tantalum oxide and multilayer graphene between two platinum electrodes. In making the material, the researchers found the tantalum oxide gradually loses oxygen ions, changing from an oxygen-rich, nanoporous semiconductor at the top to oxygen-poor at the bottom. Where the oxygen disappears completely, it becomes pure tantalum, a metal.

The researchers determined three related factors give the memories their unique switching ability.

First, the control voltage mediates how electrons pass through a boundary that can flip from an ohmic (current flows in both directions) to a Schottky (current flows one way) contact and back.

Second, the boundary’s location can change based on oxygen vacancies. These are “holes” in atomic arrays where oxygen ions should exist, but don’t. The voltage-controlled movement of oxygen vacancies shifts the boundary from the tantalum/tantalum oxide interface to the tantalum oxide/graphene interface. “The exchange of contact barriers causes the bipolar switching,” said Gunuk Wang, lead author of the study and a former postdoctoral researcher at Rice.

Third, the flow of current draws oxygen ions from the tantalum oxide nanopores and stabilizes them. These negatively charged ions produce an electric field that effectively serves as a diode to hinder error-causing crosstalk. While researchers already knew the potential value of tantalum oxide for memories, such arrays have been limited to about a kilobyte because denser memories suffer from crosstalk that allows bits to be misread.

The graphene does double duty as a barrier that keeps platinum from migrating into the tantalum oxide and causing a short circuit.

Tour said tantalum oxide memories can be fabricated at room temperature. He noted the control voltage that writes and rewrites the bits is adjustable, which allows a wide range of switching characteristics.

Wang said the remaining hurdles to commercialization include the fabrication of a dense enough crossbar device to address individual bits and a way to control the size of the nanopores.

Toshiba America Electronic Components, Inc. today launched its first 16-megapixel (MP) CMOS image sensors: T4KC3 and T4KC3-121, which includes phase detection auto-focus (PDAF). Designed for use in smartphones and tablets, the backside-illuminated (BSI) chips are among the world’s smallest class of CMOS image sensors, and achieve both high-performance image capture and low power consumption.

The functional range of the new sensors supports users in capturing beautiful images and movies. The T4KC3-121 is the first Toshiba sensor to feature PDAF technology, which makes it easier for mobile devices to capture both still and moving objects. This approach to AF technology, also used in single-lens reflex (SLR) cameras, takes an incoming image and splits it between two pixels, allowing the camera to figure out exactly how out-of-focus a subject is, and then immediately hone in and track movement.

“Mobile device manufacturers are constantly striving to design and build the most powerful, power-efficient devices in the smallest possible form factors,” said Andrew Burt, vice president of the Image Sensor Business Unit, System LSI Group at TAEC. “To support this objective, both new 16MP CMOS sensors are housed in a small module (both area and height) and use Toshiba’s new low-power circuit design method to lengthen battery life when the smartphone or tablet is being used in video mode.”

Image brightness in both new sensors is boosted by up to 4x by Toshiba’s Bright Mode technology, which enables HD video capture at 240fps equivalent. They also support high dynamic range (HDR) to capture natural images of scenes with a high contrast ratio, ending the problem of over- and underexposed images.

The T4KC3 and T4KC3-121 achieve output speeds of up to 30fps at full 16MP-resolution (4624 x 3472pixels) with power consumption figures of just 240mW or lower. Full-HD outputs of 1920 x 1080 pixels are supported at frame rates of up to 60fps, and HD outputs (1280 x 720 pixels) are supported at 120fps in normal mode and 240fps in Bright Mode.

The new sensors have an optical size of 1/2.78 inch and pixel pitch of 1.12 micrometer BSI. Additionally, they incorporate16Kbit one time programmable memory that can store lens shading correction data for four conditions at maximum, such as indoors and outdoors, daylight and sunset. Settings can be switched by one simple command.

Toshiba Corporation today announced the development of the world’s first 16-die (max.) stacked NAND flash memory utilizing Through Silicon Via (TSV) technology. The prototype will be shown at Flash Memory Summit 2015, to be held from August 11 to 13 in Santa Clara, USA.

16-die Stacked NAND Flash Memory with TSV Technology (Photo: Businesswire)

16-die Stacked NAND Flash Memory with TSV Technology (Photo: Business Wire)

The prior art of stacked NAND flash memories are connected together with wire bonding in a package. TSV technology instead utilizes the vertical electrodes and vias to pass through the silicon dies for the connection. This enables high speed data input and output, and reduces power consumption.

Toshiba’s TSV technology achieves an I/O data rate of over 1Gbps which is higher than any other NAND flash memories with a low voltage supply: 1.8V to the core circuits and 1.2V to the I/O circuits and approximately 50%*2 power reduction of write operations, read operations, and I/O data transfers.

NAND Flash Memory with TSV Technology (Graphic: Business Wire)

NAND Flash Memory with TSV Technology (Graphic: Business Wire)

This new NAND flash memory provides the ideal solution for low latency, high bandwidth and high IOPS/Watt in flash storage applications, including high-end enterprise SSD.

A part of this applied technology was developed by the New Energy and Industrial Technology Development Organization (NEDO).

STATS ChipPAC Ltd., a provider of advanced semiconductor packaging and test services, announced today the promotion and appointment of Dr. Han Byung Joon  as Co-President and Chief Executive Officer for the Company, together with Mr Tan Lay Koon.

Mr. Tan Lay Koon and Dr. BJ Han will both report to the Board and be jointly responsible for the management, strategy and performance of the Company.

“I am pleased that Dr BJ Han will be serving as Co-President and Chief Executive Officer with Mr Tan Lay Koon. Dr BJ Han is an experienced and effective leader who has served as our Chief Technology Officer and Head of Global Sales and Advanced Technology Marketing. I look forward to his continued contribution and leadership with Mr Tan Lay Koon,” said Mr Wang XinChao, Chairman of the Board, STATS ChipPAC.

Dr. BJ Han has been the Company’s Chief Technology Officer since 1999. He is also responsible for Advanced Technology Marketing and is the Head of Global Sales for the Company. Prior to joining us, Dr. Han worked at Anam Semiconductor, AT&T Bell Labs and IBM. He received his Doctorate from Columbia University and attended Harvard Business School’s Executive Advanced Management Program.

System Plus Consulting, sister company of Yole Développement (Yole), released this month its new reverse costing report, Samsung 3D TSV stacked DDR4 DRAM. In August 2014, Samsung announced the mass production of the first analyzed 3D TSV technology based DDR4 modules for enterprise servers. According to Samsung, this new module, because of its high density and high performance will play a key role in supporting the enterprise servers’ development and cloud-based applications, as well as further diversification of data center solutions.

Reverse costing analysis from System Plus Consulting includes a physical analysis at the module, package, DRAM die and cross-section level, the dedicated manufacturing process flow (TSV & bumping manufacturing step – Flip-chip & stacking process – package assembly unit) and a detailed cost analysis per process step.

According to Yole, 3D TSV technology is expected to reach $4.8B billion in revenues by 2019, mainly driven by 3D stacked DRAM and followed by 3D Logic/Memory and Wide I/O (Source: 3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Business Update, October 2014). With 40 percent share in the DRAM market, Samsung is by far the number 1 player. By introducing 3D TSV stacking in their latest 64Gb DDR4, Samsung allows this technology to enter in the main stream.
Samsung portfolio of DDR4-based modules using 20nm-class process technology includes registered dual in line memory modules (RDIMMs) and load-reduced DIMMs (LRDIMMs). These memory modules are available with initial speeds up to 2400 Mbps, increasing to the Joint Electron Devices Engineering Council (JEDEC)-defined 3200 Mbps.

This registered dual Inline memory module (RDIMM) includes 36 DDR4 DRAM chips (ref. K4AAG045WD), each of which consists of four 4Gb DDR4 DRAM dies (Ref. K4A4G085WD). The chips are manufactured using Samsung’s 20nm process technology and 3D TSV via-middle package technology.

As a result, the new 64Gb TSV module performs twice as fast as a 64Gb module that uses wire bonding packaging, while consuming approximately half the power.

“On the process side, Samsung used a temporary bonding approach using adhesive glue material and copper via-filled using bottom up filling,” detailed Romain Fraux, Project Manager, MEMS Devices, IC’s and Advanced Packaging at System Plus Consulting. And he adds: “At System Plus Consulting, we paid particular attention in identifying all technical choices made by Samsung on process and equipment (wafer bonding, DRIE via etching, via filling, bumping, underfill).”

System Plus Consulting has published more than 100 reverse costing reports on advanced packaging, MEMS and more.

“Reverse Costing is the process of disassembling a device to identify manufacturing technology and calculate cost”, explains Michel Allain, CEO of System Plus Consulting. Since 1993 the company has analyzed hundreds of integrated circuits, modules, electronic boards and systems for the benefit of large corporations in the semiconductor, automotive and telecom, consumer and energy sectors.