Category Archives: 3D Integration

CEA-Leti will host a workshop on major trends in Fully Depleted Silicon-on-Insulator process and design technologies in connection with the 17th annual LetiDays Grenoble, June 24-25.

The June 22-23 FDSOICE workshop, which will be on the MINATEC campus, brings together experts from academia, semiconductor companies, system-design houses and the EDA industry to present a vision of the strategic directions and state-of-the-art in FD-SOI IC design. Specific topics cover the FD-SOI food chain: applications, process roadmaps and manufacturing technologies, energy-efficient architectures and power management, circuit-design techniques, body-bias techniques, modeling, characterization and design enablement.

In addition to keynotes by Thomas Skotniki from STMicroelectronics and Prof. Boris Murmann from Stanford University, the workshop’s 30 presentations will cover the whole knowledge chain and the market value chain from academia and industry. Highlights of the presentations include:

  • ST, GLOBALFOUNDRIES and Samsung will cover FD-SOI manufacturing offers
  • Ciena, ST and NXP will discuss products based on FD-SOI chips
  • Cadence, Synopsys, Mentor Graphics, sureCore, eSilicon and Tiempo will explain their offers for FD-SOI in terms of IP and EDA tools
  • Prominent professors from world-class universities (ETH Zurich, University of Bologna, University of Kyoto, University of California, Berkeley) will present their innovations to design with FD-SOI
  • Leti will present state-of-the-art research in FD-SOI and facilities available to partners willing to start design with FD-SOI

Visit LetiDays Grenoble registration details and other information about the conference on June 24-25, and associated workshops and seminars on June 22, 23 and 26.

SK Hynix Inc. announced today that it is shipping mass production volumes of 1st generation High Bandwidth Memory (HBM1) based on SK hynix’s advanced 20nm-class DRAM process technology. HBM1 represents a groundbreaking leap in performance by enabling a 1,024 bit wide memory interface to achieve 128GB/second performance while reducing power by 50% over traditional GDDR5 DRAM solutions.

HBM1 utilizes through-silicon-via technology and microbumps to interconnect 4 DRAM die and 1 base die to achieve 1GB DRAM density per device. High Bandwidth Memory is designed to be assembled onto interposers allowing high speed memory interconnect to GPUs, CPUs, ASICs and FPGAs.

In addition to the mass production announcement, SK Hynix is pleased to recognize AMD as a key partner in enabling HBM1 technology. AMD announced the Radeon R9 Fury X, the world’s first graphics card with HBM technology in Los Angeles on June 16th. The AMD Radeon R9 Fury X graphics card utilizes 4GB HBM1 to achieve up to 512GB/second memory bandwidth performance while reducing memory subsystem power by up to 85%.

“AMD has pioneered the adoption of HBM1 technology in graphics applications achieving unprecedented memory bandwidth while reducing memory subsystem power” said Joe Macri, AMD Corporate Vice President and Product CTO, “Integrating AMD’s Graphics Processing Unit and HBM1 on a single 2.5D silicon interposer represents a major step forward in high performance graphics applications.”

“High Bandwidth Memory technology is the first JEDEC standard memory targeted for interposer system-in-package applications, effectively breaking down the memory wall barrier through tight integration of DRAM and high performance processors” said Kevin Widmer, SK Hynix America Vice President of Technical Marketing, “The performance requirements of emerging graphics, computing and networking applications are driving the demand for High Bandwidth Memory.”

SK Hynix is well positioned to support customer demand for High Bandwidth Memory as part of a broad portfolio of DRAM, NAND and SSD solutions. The 1.2V 1GB HBM1 device is available now in production quantities.

Related news: 

3D NAND, MRAM, RRAM: Emerging opportunities and challenges for the changing memory market

By Paula Doe, SEMI

As if scaling to 7nm geometries and going vertical with FinFETs, TSVs and other emerging technologies wasn’t challenge enough, the emerging market for connected smart devices will bring more changes to the semiconductor sector. And then there’s 3D printing looming in the wings.

Sometime between 2009 and 2010, there was a point of inflection, where the number of connected devices began outnumbering the planet’s human population. And these aren’t just laptops, mobile phones, and tablets – they also include sensors and everyday objects that were previously unconnected, says Tony Shakib, Cisco Systems VP IoE Vertical Solutions, who will talk about the impact of these changes on the chip industry at SEMICON West this summer in San Francisco.  Connected “things” may reach 25 to 50 billion by the year 2020, he projects. These connections of people, process, data and things will create opportunities for new revenue streams, new options for competitive advantage, and new operating models to drive both efficiency and value, potentially driving massive gains in efficiency, business growth, and quality of life, he suggests. “But as we connect the unconnected, this will require that we think differently about business strategy and IT, analytics, security, and more.”

Source: Cisco

Source: Cisco

Chip makers will need to provide easy-to-use IoT security for startups

One big change: some 50 percent of Internet of Things (IoT) solutions by 2017 will probably come from startups, according to Gartner’s projections.  “Whatever the exact percentage, the increased role of new and small players in the IoT edge devices will be a fundamental paradigm shift from the big companies that have conventionally dominated the electronics industry, says Gowri Chindalore, head of Technology and Business Strategy for Microcontrollers business group at Freescale, who will speak on the issue at SEMICON West’s “Monetizing the IoT: Opportunities and Challenges” session.  “And these startups’ knowledge of security is often very low.  So as IC makers we need to make it easy for them to do.” He suggests the best solution is to offer on-chip security features, such as secure storage, cryptographic accelerators, and tamper resistance mechanisms, and supplement them with a software dashboard that makes it easy for the systems maker to set up and enable the desired features appropriate for the application.  Though the encryption technology is very complex, by using library programs and selling in volume, the actual cost can probably be reduced to a few cents per chip.

Security for the internet will also improve markedly within several years as passwords are replaced by personal transmitters that automatically send secure codes to websites at log on. Similarly, local aggregator devices at the edge for all the IoT devices in the house or the factory will serve as the security gateway to screen users or devices by transmitted codes or biometric sensors. “We need proliferation of these security features into even all the benign IoT gadgets in the house to protect the network, but consumers will be willing to pay the small extra cost for security — especially after a few more highly publicized instances of hacking,” he notes.

Designers combining more IP blocks face challenges in reliability and verification

The key challenge across the board from the design side for successful IoT devices will be figuring out how to combine the right component capabilities of sensors and memory and processing and connectivity and size and power for a compelling application, and then making the right tradeoffs in the architecture to make it all work, explains Steve Carlson, VP marketing, Cadence Design Systems, another speaker at SEMICON West. “IP blocks will be especially useful for smaller companies to add functions without necessarily having the in house expertise,” he notes.  But combining the blocks will challenge many users by dramatically new issues of isolating noisy analog parts from the digital as they add RF and sensors that they haven’t had to deal with before, and all at near-threshold and ultralow power.  That will mean more issues with variation and reliability, and verification will increasingly need to include both hardware blocks and software together, so emulation will become more critical, he notes.

Fabs may need to deal with more diverse processes, but may improve productivity

“The IoT will drive demand for more IC manufacturing across a wide range of technologies, from the most advanced logic process to high voltage devices and MEMS, all with diverse requirements,” says Peter Huang, VP Field Technical Support, TSMC North America, another speaker. He notes that MEMS and other emerging devices, ranging from micro-lenses for machine vision to batteries to power wireless sensors, will require some unique tools and processes, and will be less easily scalable than CMOS.  Material handling and the need for isolated lines will create additional challenges. “Heterogeneous integration will require 2.5D packaging for both form factor and cost,” he suggests. “And the real challenge will be high volume manufacturing and IP interface at the package level.”

Though manufacturing equipment is already highly automated and interconnected, the availability of hundreds of low-cost, connected sensors may bring opportunities to increase tool automation and productivity, he adds.

IoT graphic 2

Compact integration of multiple chip and sensor technologies for IoT devices will demand more sophisticated system- in-package technology.  The new Apple Watch has 30 components in its core S1 SiP, all packed on to a 26mm x 28mm motherboard and overmolded with a conventional IC packaging resin compound. (from Chipworks)

Progress on technology for 3D printing of tooling and components

Then there’s the disruptive potential for 3D printing some of the tooling and components all along the supply chain to speed time to market, allow more customization, reduce weight and simplify dealing with legacy parts — if the process can meet the required quality and cost. Phillip Trinidad, president of service provider Proto Café, who has worked with semiconductor sector players,  argues that progress in optimizing designs now means additive manufacturing is increasingly becoming suitable not just for prototyping, but also for production of specialty parts in performance plastics.

In addition, there’s recent progress in 3D printing for challenging metal industrial parts, which will be addressed at SEMICON West “Factory of the Future: Disruptive Technologies from IoT to 3D Printing — Impact on the Semiconductor Manufacturing Sector” session. Ryan Dehoff, lead for Metal Additive Manufacture at Oakridge National Laboratory, will provide an update on the current state of the art for printing in metal, while Wayne King, director of the Initiative for Accelerated Certification of Additive Manufactured Metals, will talk about the progress on speeding qualification of the additive metal parts by modeling and inline process monitoring and control.

Along with the regular coverage of next-generation scaling technology, SEMICON West 2015 will also address the impact of the Internet of Things and 3D printing on manufacturing technology across the semiconductor supply chain, as well as related developments in MEMS, emerging non-volatile memory technology, and automotive and biomedical applications. Please visit www.semiconwest.org.

Europe’s leading nanoelectronics institutes, Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, have entered a €4.7 million collaborative open-access project called ASCENT (Access to European Nanoelectronics Network). The project will mobilize European research capabilities at an unprecedented level and create a unique research infrastructure that will elevate Europe’s nanoelectronics R&D and manufacturing community.

ASCENT opens the doors to the world’s most advanced nanoelectronics infrastructures in Europe. Tyndall National Institute in Ireland, CEA-Leti in France and imec in Belgium, leading European nanoelectronics institutes, have entered into a collaborative open-access project called ASCENT (Access to European Nanoelectronics Network), to mobilise European research capabilities like never before.

The €4.7 million project will make the unique research infrastructure of three of Europe’s premier research centres available to the nanoelectronics modelling-and-characterisation research community.

ASCENT will share best scientific and technological practices, form a knowledge-innovation hub, train new researchers in advanced methodologies and establish a first-class research network of advanced technology designers, modellers and manufacturers in Europe. All this will strengthen Europe’s knowledge in the integral area of nanoelectronics research.

The three partners will provide researchers access to advanced device data, test chips and characterisation equipment.  This access programme will enable the research community to explore exciting new developments in industry and meet the challenges created in an ever-evolving and demanding digital world.

The partners’ respective facilities are truly world-class, representing over €2 billion of combined research infrastructure with unique credentials in advanced semiconductor processing, nanofabrication, heterogeneous and 3D integration, electrical characterisation and atomistic and TCAD modelling. This is the first time that access to these devices and test structures will become available anywhere in the world.

The project will engage industry directly through an ‘Industry Innovation Committee’ and will feed back the results of the open research to device manufacturers, giving them crucial information to improve the next generation of electronic devices.

Speaking on behalf of project coordinator, Tyndall National Institute, CEO Dr. Kieran Drain said: “We are delighted to coordinate the ASCENT programme and to be partners with world-leading institutes CEA-Leti and imec. Tyndall has a great track record in running successful collaborative open-access programmes, delivering real economic and societal impact. ASCENT has the capacity to change the paradigm of European research through unprecedented access to cutting-edge technologies. We are confident that ASCENT will ensure that Europe remains at the forefront of global nanoelectronics development.”

“The ASCENT project is an efficient, strategic way to open the complementary infrastructure and expertise of Tyndall, Leti and imec to a broad range of researchers from Europe’s nanoelectronics modelling-and-characterisation sectors,” said Leti CEO Marie–Noëlle Semeria. “Collaborative projects like this, that bring together diverse, dedicated and talented people, have synergistic affects that benefit everyone involved, while addressing pressing technological challenges.”

“In the frame of the ASCENT project, three of Europe’s leading research institutes – Tyndall, imec and Leti – join forces in supporting the EU research and academic community, SMEs and industry by providing access to test structures and electrical data of state-of-the-art semiconductor technologies,” stated Luc Van den hove, CEO of imec. “This will enable them to explore exciting new opportunities in the ‘More Moore’ as well as the ‘More than Moore’ domains, and will allow them to participate and compete effectively on the global stage for the development of advanced nano-electronics.”

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under Grant Agreement No. 65384.

Integrated Silicon Solution, Inc. today announced that it has finalized a definitive agreement to be acquired by Cypress Semiconductor Corporation for $20.25 per share in cash. The definitive terms and conditions of a merger agreement detailing the current Cypress offer have been fully negotiated, and the merger agreement is subject only to execution by the parties.

The ISSI Board of Directors has determined in good faith (after consultation with its financial advisor and outside legal counsel), taking into account all relevant legal, financial and regulatory aspects of the current Cypress offer and the likelihood of consummation of such transaction, that the current Cypress offer would be more favorable from a financial point of view to the ISSI stockholders than the merger under the Uphill Agreement and that the failure to enter into a definitive agreement with Cypress on the terms in the current Cypress offer would reasonably be expected to be inconsistent with its fiduciary duties under Delaware Law.

As required by the terms of the Uphill Agreement, ISSI has notified Uphill of the determination by the ISSI Board and provided Uphill with copies of the proposed transaction documents relevant to the current Cypress offer.  In this notice, Uphill was informed that the ISSI Board is prepared to approve or recommend the Cypress offer and terminate the Uphill Agreement to enter into a definitive agreement with Cypress unless Uphill delivers within four days a written, binding and irrevocable offer to modify the terms of the Uphill Agreement in a manner such that the ISSI Board, shall have determined in good faith, after considering the terms of such offer, that the Cypress offer no longer constitutes a Superior Proposal (as defined in the Uphill Agreement). This four day period will expire at 5:00 p.m. Pacific Time on Sunday, June 14, 2015.  ISSI and its representatives are prepared to negotiate in good faith with Uphill and its representatives regarding any modifications to the terms of the transaction contemplated under the Uphill Agreement, such that the current Cypress offer would no longer constitute a Superior Proposal.

As a result of the foregoing, the ISSI special meeting of stockholders that was scheduled for June 12, 2015 at 2:00 p.m., local time, will not occur until at least June 19, 2015.

The ISSI Board of Directors is not withholding, withdrawing, qualifying, amending or modifying its recommendation with respect to the Uphill Agreement and the merger with Uphill, is not proposing to do so, and is not making any recommendation with respect to the current Cypress offer at this time.

ISSI is a fabless semiconductor company that designs and markets high performance integrated circuits

UPDATE:15 December 2015: Minor changes made to reflect correct ARM product nomenclature.

By Jeff Dorsch, Contributing Editor

Those 16-nanometer chips with FinFETs? Yesterday’s news. Taiwan Semiconductor Manufacturing wants you to know that they’re ready, willing, and able to help you design chips with 10-nanometer features.

The foundry presented Monday morning with its long-time partners, ARM Holdings and Synopsys, on its preparations for the 10nm process node.

20150608_072835 (640x360)

“The N10 design ecosystem is ready for customer design starts,” said Willy Chen, TSMC’s deputy director of Design & Technology Platform. He noted that TSMC has been collaborating with Synopsys for 15 years, while ARM and TSMC together offer “the most advanced ARM processor cores in the most advanced TSMC technology.”

Rob Aitken of ARM added, “10-nanometer enablement needs an ecosystem,” which the three companies are prepared to provide. He said ARM has “some cool things under development to make chip design faster,” without elaborating.

Haroon Gahur, principal design engineer at ARM, began the program by describing attributes of the ARM Cortex-A72 processor design, which he said consumes 75% less energy than previous ARM cores.

Joe Walston of Synopsys said ARM used the DC Graphical, IC Compiler I, and IC Compiler II tools from Synopsys in developing Cortex-A72, with signoff performed by PrimeTime SI. ARM’s Gahur noted that IC Compiler II provided a significant runtime advantage over its predecessor, IC Compiler I, by completing its run in five hours, compared with about 24 hours for IC Compiler I.

The program also featured Denny Liu, deputy general manager of Design Technology at MediaTek, who spoke of his company’s involvement with Synopsys and TSMC. He detailed MediaTek’s Helio X20, introduced last month, which is a tri-cluster mobile processor with 10 cores. MediaTek also employed IC Compiler II in designing the chip.

For all the 10nm talk, TSMC is hitting its stride with the N16FF+ process. Synopsys and TSMC announced Monday that the IC Compiler II place-and-route tool is certified for the foundry’s 16nm FinFET Plus process.

“The 16FF+ design flow is here,” TSMC’s Chen said.

The program finished with a presentation by Henry Sheng, group director of research and development at Synopsys, who noted that 90 percent of FinFET tapeouts are done with Synopsys place-and-route tools. Touting his company’s “healthy working relationship with TSMC,” Sheng said that emerging process nodes present a number of challenges, specifically new yield and manufacturing rules, process scaling, and new FinFET devices. Of FinFETs, he said, “These things are electrically different.”

Separately, Synopsys announced Sunday that it has agreed to acquire Atrenta, without disclosing financial terms. The transaction is expected to close this summer.

CEA-Leti announced today during the Design Automation Conference that seven partners have joined its new FD-SOI IC development program, Silicon Impulse, launched to provide a comprehensive IC technology platform that offers IC design, advanced intellectual property, emulator and test services along with industrial multi-project wafer (MPW) shuttles.

The collaborative design platform for advanced processes includes a network of design services and facilities focused on accelerating development of products for today’s and tomorrow’s devices that require low-power use. These include energy-efficient computing systems, Ultra-Low-Power (ULP) Internet of Things (IoT) devices and robust and reliable applications in harsh environments. The platform leverages the competencies and expertise of the CEA-Leti and CEA-List institutes and Leti’s industrial partners, which comprise a wide spectrum of technical and application knowledge.

Silicon Impulse partners are major industrial players in the semiconductor ecosystem, world-class research centers and technology providers. Based on this strong foundation, Silicon Impulse will significantly reduce development time and speed industrialization, thus putting innovative companies at the cutting edge of energy-efficient system development and implementation. It will do this through a network of FD-SOI experts and access to a strong industrial supply chain.

Silicon Impulse partners:

CEA-Leti (coordinator)

CEA-List

STMicroelectronics

Dolphin Integration

 CMP

Mentor Graphics

Cortus

Presto Engineering

 

In addition, CEA-Leti is planning to use its research & development license from ARM to demonstrate various energy-efficient processor implementations in FD-SOI for its IoT development platform. The FD-SOI ecosystem also includes Synopsys, with its rich portfolio of proven DesignWare IP products and EDA tools for the FD-SOI design community. Silicon Impulse is in discussion with Synopsys to join the program in order to further extend the program’s reach.

Launched by Leti in 2015, Silicon Impulse is designed to help innovative companies deal with the challenge of switching to new technologies and markets by augmenting both their knowledge of the supply chain and their skills to master the entire design process from ideas to products. To that end, Silicon Impulse will provide technical expertise, knowhow and access to advanced industrial, energy-efficient solutions to get innovators up to speed on the ecosystem of energy-efficient products by facilitating access to FD-SOI technology and manufacturing facilities.

“Leti has always concentrated on research that helps our partners adopt technology to become more competitive in their markets. Now with Silicon Impulse we provide a new service in collaboration with our industrial partners to help companies evaluate, design, prototype and launch new products,” said Marie-Noëlle Semeria, CEO of Leti. “From that foundation, Silicon Impulse will leverage the existing ecosystem to bring the full value chain from research, design solutions and industrialization services to high value-added products. This combination will concentrate through a single entry point all the necessary expertise and competencies to provide innovative companies from any sector with a one-stop-shop opportunity to build leading-edge, energy-efficient systems.”

As electronic devices become increasingly integrated into everyday activities, designing for energy efficiency becomes more important than ever for all mainstream sectors of industry. Embedded systems and particularly the IoT are key enablers in the market, and new entrants (startups, SMEs, large companies) drive innovation. By enabling integration of advanced processes – 28nm FD-SOI technology today – into IoT design and helping companies develop innovative products more rapidly, Silicon Impulse will foster leading-edge technologies and facilitate their adoption for manufacturing.

With the program’s flexible format, Silicon Impulse’s involvement can be limited to architectural consulting or extended to developing and delivering the whole system or anything in between. It can help innovators with their projects from concept through production hand-off. Companies can receive architectural advice and have their products shaped from a very high level, including a feasibility study and recommendations on how to implement the system. Leti and its partners also can provide unique IP and/or technology components such as foundation IP or more complex system level IP blocks, RF, NVM, N/MEMS, 3D components and any other advanced technology to shape a unique and advanced, yet manufacturable, product. At another level, Leti and List could provide embedded software to complete the whole product.

One key goal of the Silicon Impulse platform is to provide and ease silicon access. MPW shuttles are provided to open the doors to a wider set of users and projects. The goal is to enable innovators to test their ideas, especially mixed-signal, analog or RF technologies or any new IP that would require silicon validation in FD-SOI. This also provides an affordable platform for startups and other small companies to build their prototypes and run small volumes until they receive financing and/or demonstrate market traction to build their own mask set. The first 28nm FD-SOI MPW is planned for February 2016 to be processed at STMicroelectronics’ site in Crolles, which is near Grenoble.

Imec researchers have developed a novel technique – termed conductive atomic force microscopy tomography (or scalpel C-AFM) – that enables a three-dimensional characterization of emerging logic and memory devices.

BY UMBERTO CELANO, imec, Leuven, Belgium

Umberto Celano, using the novel scalpel C-AFM tool.

Umberto Celano, using the novel scalpel C-AFM tool.

With the introduction of three-dimensional devices (such as FinFETs) and stackable architectures (such as vertical NAND Flash memories), there is a growing need for 3D characterization techniques. These techniques should not only be capable of probing in three dimensions and examining the topological properties. They should also enable an analysis of the electrical properties of the 3D nano-sized volumes.

A shining example illustrating the need for this technique are conductive bridging random access memory (or CBRAM) devices. These devices belong to the emerging class of resistive RAM (or RRAM) memories which exhibit a fast operation, low power consumption, high endurance and high scalability. They are currently seen as a candidate memory technology for application in storage class memories and embedded non-volatile memories. Their operation basically relies on the formation of a highly conductive path, the conductive filament, in a poorly conductive medium. But the formation of this filament in an integrated device has so far never been observed with the techniques available today. A full 3D characterization of the conductive filament would considerably enhance our understanding of the filament growth dynamics and the underlying physical mechanisms. And it would enable a further optimization of the memory device.

Scalpel C-AFM, extending the 2D capabilities of C-AFM

A well-known characterization technique for advanced logic and memory devices is scanning probe microscopy (or SPM), where a sharp tip slides on a flat surface.

The 2D-maps of electrical properties provided by this technique have for many years enabled the understanding and development of advanced planar technologies at the nanoscale. SPM comes in several flavors, such as scanning tunnel microscopy (STM), atomic force microscopy (AFM), and a whole range of secondary analysis modes such as conductive AFM (or C-AFM). C-AFM is based on contact-mode AFM using a (biased) conductive tip. The topography is measured in contact-mode, while the current flowing between the biased sample and the tip is recorded simultaneously.

Researchers at imec have now evolved the C-AFM technique into a 3D characterization tool, suited to probe very confined volumes at the nanoscale. The new method consists in collecting the C-AFM images of the sample at different depths. The sectioning is induced by a controlled material removal. This is done by applying a strong pressure (GPa) between the (biased) conductive-diamond tip and the sample during the C-AFM scan. This way, sub-nm vertical removal rates are obtained. Since the diamond tip acts as a scalpel, the new method is referred to as scalpel C-AFM. The technique can be used for a wide variety of materials, and can be extended to other contact-mode AFM methods such as scanning spreading resistance microscopy.

Case: CBRAM memory devices

The imec researchers have used the scalpel C-AFM technique for studying the conductive filament formation in CBRAM memory devices. In these devices, an abrupt change in electrical resistance occurs when the device is subjected to a voltage pulse. The different resistance states are induced by the formation or dissolution of a highly conductive filament into a poorly conductive medium.

The heart of the CBRAM memory cell is a thin dielectric (e.g., Al2O3) that is sandwiched between the active electrode (Cu or Ag) and an inert counter electrode (e.g., TiN). When a positive voltage is applied to the active electrode, a field-assisted injection and transport of cations begins. This leads to the creation of the conductive filament inside the Al2O3 oxide layer. The presence of this filament dramatically lowers the resistance of the device, leaving it in a low resistive state (LRS). The conductive filament can be dissolved by applying a negative voltage to the active electrode and thus restoring a high resistance state (HRS). The two different resistance states are used as the logic values 1 or 0 for data storage applications. The overall performance of the device is highly related to the properties of the conductive filament, which has so far not been observed in 3D on scaled devices.

Observation of the conductive filament

The memory device under investigation is a Cu/5nm Al2O3/TiN-based memory, integrated in a one-transistor-one-resistor configuration. The device is placed at the cross-point between the bottom and top electrode. The scalpel C-AFM technique was applied to memory devices programmed in both the low and high resistive state. An in-house fabricated conductive- diamond tip was used for probing and removing the material.

By using the scalpel C-AFM technique, the researchers were able to observe, for the first time ever, the conductive filament formation which is responsible for the resistive switching behavior in CBRAM devices (FIGURE 1). The observed conductive filament, embedded in the Al2O3 oxide, shows a conical shape: it shrinks moving from the active electrode (Cu) towards the inert electrode (TiN). The low resistive state is created when the conductive filament eventually shorts the two electrodes.

Filaments 1-1 Filaments 1-2

 

FIGURE 1. CBRAM device: Cross-section transmission electron microscopy (TEM) image of the CBRAM memory device (left) and the device stack (middle), and AFM image of the cross-point area (right).

The experiments suggest that the dynamics of the conduction filament growth are limited by the mobility of the Cu cations in the electrolyte (FIGURE 2). When the bias is reversed, a Joule-heating assisted electro-chemical reaction is responsible for the rupture of the conductive filament (the high resistive state).

The study also demonstrates the close correlation between the programming current, the physical volume of the conductive filament and the resistance. A larger programming current induces a larger physical volume and a lower resistance value of the conductive filament. Hence, by controlling the programming current, the resistance can be modulated. This opens the possibility of creating multiple resistance sates in one single memory cell, which can considerably enhance the memory density of non-volatile CBRAM devices.

Scalpel C-AFM will rapidly find applications in other emerging technologies as well. At imec, the technique is currently being used for investigating vertical NAND Flash memory devices and oxide-based RRAM memory devices.

FIGURE 2. filament growth model: Illustration of the eletrochemical processes during resistive switching. (1) First, the Cu oxidizes and Cu+ ions are injected in the Al2O3. Second, the high electric field might lead
to the formation of oxygen vacancies in the dielectric layers (white balls in the cartoon). (2) The slow
migration of Cu+ ions in the switching layer implies
that a reduction reaction occurs before the Cu+ reaches the inert-electrode. (3) The conductive filament (CF) growth continues and the CF eventually shorts the two electrodes thereby creating the low resistive state. (4) When the bias is reversed, a Joule-heating assisted electrochemical reaction is responsible for the rupture of the CF in the point of max power dissipation, that is, CF constriction.

FIGURE 2. filament growth model: Illustration of the eletrochemical processes during resistive switching. (1) First, the Cu oxidizes and Cu+ ions are injected in the Al2O3. Second, the high electric field might lead
to the formation of oxygen vacancies in the dielectric layers (white balls in the cartoon). (2) The slow
migration of Cu+ ions in the switching layer implies
that a reduction reaction occurs before the Cu+ reaches the inert-electrode. (3) The conductive filament (CF) growth continues and the CF eventually shorts the two electrodes thereby creating the low resistive state. (4) When the bias is reversed, a Joule-heating assisted electrochemical reaction is responsible for the rupture of the CF in the point of max power dissipation, that is, CF constriction.

Suggested additional reading

‘Three-dimensional observation of the conductive filament in nanoscaled resistive memory devices’, U. Celano et al., Nano Letters, 2014. http://pubs.acs.org/ doi/abs/10.1021/nl500049g.

‘The memory roadmap, a paradigm shift from 2D to 3D’, interview with imec’s Jan Van Houdt in imec magazine, March issue. http://magazine.imec.be/ data/57/reader/reader.html#preferred/1/package/57/ pub/63/page/4.

UMBERTO CELANO is PhD student in the Material and Component Analysis (MCA) group at imec, Leuven, Belgium.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced it has reached a critical milestone in providing a design infrastructure for its 14-nanometer (nm) FinFET process technology.

Together with key ecosystem partners Cadence Design Systems, Mentor Graphics, and Synopsys, GLOBALFOUNDRIES has developed new digital design flows for register-transfer level (RTL) to graphic design database system (GDS) implementation. Integrated with a technology-proven process design kit (PDK) and early-access standard cell libraries, the flows create a digital design “starter kit” that provides designers with a built-in test case for out-of-the-box physical implementation testing and analysis of performance, power and area.

“GLOBALFOUNDRIES is committed to providing our customers with advanced technology platforms that include the comprehensive design infrastructure required to optimize design productivity and cycle time,” said Rick Mahoney, senior vice president of design enablement at GLOBALFOUNDRIES. “To ensure our design ecosystem delivers the highest quality experience with our 14nm FinFET technology, GLOBALFOUNDRIES has collaborated with our EDA partners to complement our in-house global design capabilities and accelerate time-to-volume of designs on complex technologies like 14nm FinFET.”

GLOBALFOUNDRIES’ digital design flows have been optimized to solve the challenges associated with the critical design rules of the 14nm technology node and includes newly introduced features such as implant-aware placement and double-patterning aware routing, In-Design DRC™ fixing and yield improvement, local/random variability aware timing, 3D FinFET extraction, and color-aware LVS/DRC sign-off.

The Synopsys-based Design Enablement Starter Kit leverages broad capabilities of its Galaxy Design Platform to deliver signed-off GLOBALFOUNDRIES’ 14LPP FinFET designs with optimized performance, power and area. Synopsys’ Design Compiler Graphical synthesis, coupled with its Formality equivalence checking solution, streamlines the flow by providing physical guidance and results that closely correlate with physical implementation. For FinFET implementation, Synopsys’ IC Compiler, IC Compiler II and IC Validator solutions provide implant- and double-patterning-aware placement and routing with In-Design color-aware physical verification. Synopsys’ StarRC extraction provides double-patterning support, with modeling for color-aware and 3-D extraction essential for 14nm designs. In addition, the industry-standard Synopsys PrimeTime sign-off solution for accurate delay calculation, timing analysis and advanced waveform propagation accurately accounts for FinFET impacts such as ultra-low voltage, increased Miller effect and resistivity, and process variation.

To enable customers to achieve the benefits of GLOBALFOUNDRIES’ 14LPP node at the design level, GLOBALFOUNDRIES and Cadence have worked together to create a digital flow for a complete RTL-to-GDSII FinFET solution. The digital flow integrates and optimizes Cadence’s front-end, back-end, physical verification, and DFM solutions for 14LPP technology. For front-end design, Cadence’s RTL Compiler synthesis flow is fine-tuned with the 14LPP library. For physical implementation, both Encounter Digital Implementation System (EDI) and Innovus Implementation System provide color-aware double-patterning technology for correct-by-construction placement and routing, and customized settings for the 14LPP design rules and library to optimize power, performance and area (PPA). In-design PVS DRC fixing and in-design litho hot-spot fixing are both available to designers to reduce design iterations and ease design closure. For signoff, the flow features fully integrated Quantus QRC Parasitic Extraction and Tempus Timing Signoff solutions. Integration within both EDI and Innovus allows Quantus and Tempus to bring advanced process modeling earlier in the P&R flow for better timing convergence and time-to-tapeout. Encounter Conformal Equivalence Checker is embedded in multiple stages in the implementation flow. Voltus power and EMIR analysis, standalone Physical Verification System physical verification and Litho Physical Analyzer litho hot-spot check are also embedded in the reference flow. The reference flow provides a guided approach to Cadence’s tool suite and the GLOBALFOUNDRIES 14LPP process to ensure designers hit the maximum PPA envelope with minimum ramp-up time.

As with production tape-outs at prior nodes, the starter kit uses the Mentor Graphics Calibre tool suite for sign-off. In the case of the 14nm starter kit, the Calibre nmDRC and Calibre MultiPatterning products are used for layer decomposition, DRC verification and metal filling, while the Calibre nmLVS product is used for logic verification.

GLOBALFOUNDRIES 14nm FinFET technology is among the most advanced in the industry. The 3D FinFET devices offers the perfect answer to growing market needs, with best-in-class intrinsic performance boost over 28nm technology and a superior power footprint compared to any predecessors. These leading edge devices also provide a true cost advantage due to superior power, performance and area scaling.

GLOBALFOUNDRIES is yielding on its 14nm technology and is on schedule to support multiple product tape-outs and volume ramp in 2015.

Through GLOBALFOUNDRIES’ design partnership ecosystem, designers have access to a broad spectrum of services such as system design, embedded software design, SoC design and verification, and physical implementation. These include design flows for electronic design automation (EDA); silicon-proven IP building blocks, such as libraries; and simulation and verification design kits, i.e., process design kits (PDK) and technology files.

SEMI this week announced the SEMICON West 2015 test and packaging program agendas. In addition to over 650 exhibitors, SEMICON West will feature more than 180 total hours of programs — including free technical, applications and business events as well as exclusive programs. Discounted registration for SEMICON West 2015 ends June 5.

Exclusive programs include the three-day Semiconductor Technology Symposium (STS), a comprehensive technology and business conference, addressing the key issues driving the future of semiconductor manufacturing and markets. This year, STS programs on Packaging and Test include:

  • The Very Big Picture, the Future of Semiconductor Packaging Technology (July 14) — with speakers from 3MTS, AMD, Oracle, and more; plus a panel discussion on “Value vs. Cost”
  • Packaging: Digital Health and Semiconductor Technology (July 14) — with speakers from Cisco, Medicustek, GE Global Research Center, Medtronic, and more
  • Test Vision 2020: The Road to the Future of Test  (July 15-16) — with keynote from Kaivan Karimi, VP at Atmel, Inc. plus speakers Brad Shaffer of IHS and Thomas Burger of AMS. Sessions include: Wireless Test in the IoT Era; Unique Test Flows for New Cost Challenges; and Advanced Packaging, Advanced Test Challenges. Panel sessions will discuss “How Secure is your Test Data, Really?” and “What Does RF Test Look like in Five Years? Future Solutions for Lowering the Cost of Transceiver Tests”

In addition, two packaging and test sessions will be offered as part of the TechXPOT program on the exhibition floor (free to exposition attendees):

  • Automating Semiconductor Test Productivity (July 14) — a panel of experts from the semiconductor test community, including representatives from TI, STMicro and ASE,  will discuss challenges and opportunities for automating test operations to maximize productivity
  • Auto Utopia: Gearing up Semiconductor to Turns Dreams to Reality (July 15) — with speakers from ASE, Gartner, PRIME Research, ASE Singapore, and more (session partner: MEPTEC)

Other key segments at SEMICON West 2015 include:

  • Global Business Outlook
  • Semiconductor Fabrication, Equipment and Materials
  • The Internet of Things
  • MEMS
  • Flexible Hybrid Electronics
  • Sustainable Manufacturing
  • Next-Generation Products

SEMICON West (www.semiconwest.org) continues to feature a full set of complimentary programs, including keynote addresses, executive panels, technical and business sessions.  The Tuesday Keynote Panel features imec, Qualcomm, and Stanford University tackling the issue of “Scaling the Walls of sub-14nm Manufacturing.” Doug Davis, senior VP and GM, IoT Group at Intel, will present the Wednesday Keynote.

To view a SEMICON West 2015 “schedule at-a-glance,” click here.  Discounted pricing is available through June 5.  Early-bird pricing for the Semiconductor Technology Symposium (STS), Test Vision 2020, and Sustainable Manufacturing Forum (SMF) also applies through June 5.  Register now to save: www.semiconwest.org/Participate/RegisterNow