Category Archives: 3D Integration

NXP Semiconductors and Stora Enso have entered into joint development of intelligent packaging solutions. The development will focus on integrating RFID (Radio frequency identification) into packages for consumer engagement and supply chain purposes. The collaboration will also focus on brand protection and the development of tamper evidence applications. These solutions will benefit both consumers and brand owners.

By using NXP RFID technology such as near field communication (NFC) and ultra-high frequency (UHF), Stora Enso smart packages can be easily tracked and traced through the entire supply chain providing full end-to-end transparency. The integrated technology is also able to detect if the smart package has been tampered with en route to the consumer and, once in the hands of the consumer, can provide additional information and interaction through (the tap of) an NFC-enabled smart phone. This visibility and insight is critical for brands and major manufacturers to ensure their products are being shipped and handled correctly. For consumers the benefits are two-fold; the smart packaging can verify the authenticity of the product and also provide care, usage and other important information via the NFC-enabled tag.

“The co-operation with NXP offers substantial business opportunities for Stora Enso. We have already worked on several concept cases with customers and partners within intelligent packaging. The co-operation with NXP will enable us to bring this development closer to market and provide faster scalability in intelligent paper and board solutions,” says Karl-Henrik Sundström, CEO, Stora Enso.

“Our RFID technology in combination with Stora Enso’s packaging solutions creates additional value to both consumers and brand owners by providing information and insights along the complete supply chain,” said Ruediger Stroh EVP & GM Security & Connectivity, NXP Semiconductors. “The ability of the RFID tag to detect when a package has been compromised and also provide additional product information via NFC truly enables a unique, smart, engaging brand experience and is another example of how security can be broadly implemented to protect our everyday lives.”

United Microelectronics Corporation, a global semiconductor foundry, today unveiled its UMC Auto technology platform to target IC companies designing chips for automotive applications. UMC Auto is a comprehensive platform that consists of a broad portfolio of automotive AEC-Q100 qualified technology solutions ranging from 0.5um to 28nm nodes, backed by robust manufacturing processes that comply with rigorous ISO TS-16949 automotive quality standards for all UMC fabs. In addition, UMC is selectively developing certified design models, IP, and Foundry Design Kits specific to the UMC Auto platform in order to fulfill the increasing pace of evolvement of the auto industry supply chain, helping chip designers capture new market opportunities as Internet of Things (IoT) and increased use of sensors permeate into auto applications.

“With the rapid rise in silicon content within each new vehicle, many believe the automotive IC sector will experience the highest CAGR compared with other semiconductor segments,” said Po Wen Yen, CEO of UMC. “UMC has a successful history as an automotive IC supplier, being the first foundry to receive ISO 22301 certification for our business continuity management system and implementing a comprehensive “Automotive Service Package” that incorporates zero-defect practices within our manufacturing procedures. We look forward to enabling more customers to realize the opportunities within the automotive IC market through our innovative UMC Auto solutions platform.”

UMC is currently producing various key electronic components used in vehicles, including Advanced Driver Assistance Systems (ADAS), safety, body control, infotainment and under-hood applications. These ICs manufactured at UMC have been widely adopted by the world’s most well-known carmakers in Japan, Europe, Asia and the United States.

UMC’s auto IC manufacturing lines meet or exceed the automotive industry’s most stringent quality and reliability criteria, including the highest rated AEC-Q100 Grade-0 certification for its fab manufacturing. UMC was also the first foundry in Taiwan to provide IC manufacturing services that comply with ISO 15408 Common Criteria, joining the 1 percent of all companies and products worldwide to be certified ISO 15408 EAL6 or above. This security qualification signifies UMC’s ability to provide rigorous security protection during the manufacturing process, which is required by the majority of IC products deployed in sensitive applications that need to be highly secure such as automotive sensors for door locks, navigation, etc.

During the IEEE IITC conference in Grenoble, the nanoelectronics research center imec and Lam Research Corporation today presented a novel bottom-up prefill technique for vias and contacts. The technique, based on Electroless Deposition (ELD) of Cobalt (Co) is a highly selective method resulting in void-free filling of via and contact holes. Potentially increasing the circuit performance, it is a promising path to scaling advanced interconnects and enabling future logic and DRAM nodes at the 7nm node and below.

As logic and memory nodes scale, performance of these advanced interconnects is negatively impacted by increasing interconnect resistance. Furthermore, voids that occur in heavily scaled vias severely impact yield. imec’s industrial affiliation program on advanced interconnects is exploring novel metallization methods to solve these issues. One way to solve the problem is to identify integration and metallization alternatives that provide resistance benefits over conventional technology without compromising reliability and yield. Together with Lam Research, a Co ELD technique was demonstrated as a feasible method for highly selective bottom-up contact fill and via prefill with Cobalt (Co) as an alternative metal to Copper (Cu). Moreover, the high selectivity of the ELD process, at lower cost compared to Chemical Vapor Deposition (CVD), intrinsically ensures a good metal-to-metal interface and paves the way to void-free via filling and increased yield. Trench fill yield and line resistance may also benefit from the de-coupling of line and via aspect ratios, permitting the design of each for optimum Resistance/Capacitance (RC). Therefore, Co prefill ELD has the potential to enable future scaling of advanced logic and memory technologies.

Figure: Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5)

Figure: Co ELD on Palladium/Tungsten (Pd/W) for different timed stops to yield an (i) under fill, (ii) potential ideal stop or an (iii) overburden in 28nm holes (Aspect Ratio (AR) 4.5)

The results were achieved in cooperation with imec’s key partners as part of its core CMOS programs: GlobalFoundries, Intel, Samsung, SK hynix, Sony, TSMC, Amkor, Micron, Utac, Qualcomm, Altera, Fujitsu, Panasonic, and Xilinx.

Semiconductor Research Corporation (SRC) announced today that Ken Hansen has been appointed SRC’s new President and Chief Executive Officer (CEO), effective June 1.

Hansen’s professional experience includes serving as Vice President and Chief Technology Officer (CTO) at Freescale Semiconductor since 2009. Hansen replaces retiring SRC President and CEO Larry Sumney who guided the organization for more than 30 years since its inception in 1982. SRC’s many accolades over the years include being the recipient of the National Medal of Technology in 2007.

“SRC under Larry Sumney’s leadership has made an indelible impact on the advancement of technology during the past three decades, and we congratulate Larry on his retirement and salute him for his contributions to the semiconductor industry,” said Mike Mayberry, Intel Corporate Vice President and Director of Components Research who is SRC Board Chairman. “We also welcome Ken Hansen to his new role guiding SRC, and we look forward to Ken’s leadership helping SRC reach new heights in an era where basic research and development is as critical as ever.”

Prior to his CTO role at Freescale, Hansen led research and development teams for more than 30 years in multiple senior technology and management positions at Freescale and Motorola. Hansen holds Bachelor and Master of Science degrees in Electrical Engineering from the University of Illinois where he has been recognized as an ECE (Department of Electrical and Computer Engineering) Distinguished Alumni.

In his new role at SRC, Hansen intends to build on the consortium’s mission of driving focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry.

“SRC also has an opportunity to strengthen its core by recruiting new members to gain more leverage to fund industry wide solutions for some of the challenging technology roadblocks that are ahead of us,” said Hansen.

“The model that SRC has developed is unmatched in the industry and has proven to be extremely significant. The industry would not be where it is today without the contributions of SRC under the leadership and vision of Larry Sumney,” Hansen continued.

Meanwhile, Sumney’s decorated career began in 1962 at the Naval Research Laboratory. He later directed various other research programs at Naval Electronics Systems Command and the Office of the Undersecretary of Defense — including the Department of Defense’s major technology initiative, Very High Speed ICs (VHSIC) —before agreeing to lead SRC following its formation by the Semiconductor Industry Association.

Under his leadership, SRC has also formed wholly owned subsidiaries managing the Nanoelectronics Research Initiative (NRI), the Semiconductor Technology Advanced Research network (STARnet) and the SRC Education Alliance, among other programs. Sumney received a Bachelor of Physics from Washington and Jefferson (W&J) College, which recognized him with the 2012 Alumni Achievement Award, and a Master of Engineering Administration from George Washington University.

“I have enjoyed a front row seat in the development of today’s technology-based economy and advancement of humanity through the semiconductor industry,” said Sumney. “I am completely confident that SRC is well positioned and will continue to flourish, to seed breakthrough innovation and help provide the people and ideas to keep the U.S. semiconductor industry competitive and prosperous in years to come.”

Additional industry leaders with strong ties to SRC commended Sumney for his service over the years while supporting Hansen’s appointment.

“Over more than 30 years, Larry Sumney’s visionary leadership of SRC has steered one of the world’s most transformative industries through times of tremendous growth and innovation,” said John Kelly, Senior Vice President, Solutions Portfolio and Research for IBM.  “I’ll personally miss working with Larry, but also have tremendous respect for and confidence in Ken Hansen, and we look forward to collaborating with him to drive the next generation of research in this vital industry.”

“Larry’s leadership and vision are key reasons why SRC’s research has played a fundamental role behind many of the most significant semiconductor innovations of the last three decades,” said Lisa Su, AMD president and CEO and a former SRC student. “Ken’s broad industry experience makes him ideally suited to lead the next phase of the SRC, as the organization continues to expand its capabilities and provide the basic research and development foundation needed to further accelerate innovation across the industry.”

By Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

Scaling is now bifurcating – some scaling on with 28/22nm, while other push below 14nm.

In his famous 1965 paper Cramming more components onto integrated circuits, Moore wrote: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year”. Dimensional scaling below 28nm will only increase the ‘component cost’ as we described in Moore’s Law has stopped at 28nm and is detailed in the following tables published recently by IBS.

Fig 1

 

While there is still a strong effort behind dimensional scaling to 14, 10 and 7nm – and possibly even beyond, a new scaling effort is emerging to reduce the ‘component costs’ and increase integration yet still utilize the 28 nm process node. The semiconductor industry is now going through a bifurcation phase.

This new emerging trend of scaling by factors other than dimensional scaling was recognized early-on by Gordon Moore and was detailed in his 1975 famous IEDM paper “Progress in digital integrated electronics.”. In that paper Moore updated the time scaling rate to every two years and suggested the following factors are helping to drive scaling forward:

  1.  “Die size” – “larger chip area”
  2. “Dimension” – “higher density” and “finer geometries”
  3. “Device and circuit cleverness”

A fourth factor should have been added to the list above – improvement in manufacturing efficiency, which ensued from the increase in wafer sizes from 4” to 5” and all the way to the 12” of today, and many other manufacturing improvements.

In the past, all of these factors were aggregated into dimensional scaling as old fabs got obsolete and improvements were implemented predominantly in the new emerging node. Nowadays, as dimensional scaling has reached its diminishing returns phase, we can see a very diverse adaption of technology improvments.

In his keynote presentation at the 2014 Synopsys user group meeting, Art De Geus, Synopsys CEO, presented multiple slides to illustrate the value of Synopsys’ newer tools to improve older node design effectiveness. The following is one of them:

Fig 2

AMD’s recent presentation at ISSCC 2015 clearly illustrates this point by showing device improvements while still staying at the same 28 nm process node, see slide below. As could be seen, major improvements in power, yield, and performance are possible over time without changing the technology node. AMD’s President & CEO Dr. Lisa Su presentation in 2015 Semicon China, reiterated AMD’s technology progress within the same 28nm technology node:

Fig 3

Even more significant would be the adoption of a breakthrough technology. A good example is the SRAM technology developed by Zeno Semiconductor, which has recently been validated on a 28nm process. This new SRAM technology replaces the 6T SRAM bit cell with 1T SRAM (true SRAM – no refresh is needed) providing significant reduction of ‘component costs’ as is illustrated in the following two slides.

Fig 4

Fig 5

This new industry trend was nicely articulated by Kelvin Low of Samsung covered in “Samsung Describes Road to 14nm, FinFETs a challenge, FD-SOI an alternative.” Quoting: “Samsung spent several years developing its 14nm technology and debating which process node it would invest in after 28nm. Low expects that 28nm will still be a popular process node for years to come because of its price …The cost per transistor has increased in 14nm FinFETs and will continue to do so, Low said, so an alternative technology such as 28nm SOI is necessary”. TSMC too is now spending on new R&D efforts to improve their 28 nm as was presented in TSMC 2015 Technology Symposium, introducing new 28nm processes, 28HPC+ and 28ULP. 28HPC+ is for high performance, a speed gain of about 15% for the same leakage, or a reduction of 30-50% in leakage for the same speed. The 28ULP (for ultra-low power) process is for IoT applications with a lower operating voltage of 0.7V (versus 0.9V for 28HPC+). And also new standard cell libraries were developed for this process with 9 and 7 track libraries (compared to 12T/9T before).

“Device and circuit cleverness” as a factor will never stop; however, it is made of a series of individual improvements that will not be enough to sustain a long-term scaling path for the industry. An alternative long-term path will be “Die size” – “larger chip area,” which is effectively monolithic 3D, and manufacturing efficiency, which will have an important role in monolithic 3D.

And who is better to call it than Mark Bohr of Intel? In a recent blog piece “Intel predicts Moore’s Law to last another 10 years” Bohr is quoted predicting “that Moore’s Law will not come to an abrupt halt, but will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

And this is also visible in the marketplace by the industry-wide adoption of 3D NAND devices that Samsung started to mass-produce in 2014, and followed with a second generation 32 layer-stack device this year, and forecasting going to ~ 100 layers, as illustrated in their slide:

Fig 6

 

In the recent webcast “Monolithic 3D: The Most Effective Path for Future IC Scaling,” Dr. Maud Vinet of CEA Leti presented their “CoolCube” monolithic 3D technology, which was followed by our own, i.e., MonolithIC 3D, presentation. An important breakthrough presented by us was a monolithic 3D process flow that does not require changes in transistor-formation process and could be easily integrated by any fab at any process node.

Finally, I’d like to quote Mark Bohr again as we reported in our blog “Intel Calls for 3D IC”: “heterogeneous integration enabled by 3D IC is an increasingly important part of scaling” as was presented in ISSCC 2015.

Fig 7

 

This is illustrated nicely by the following figure presented by Qualcomm in their ISPD ‘15 paper titled “3D VLSI: A Scalable Integration Beyond 2D.”

Fig 8

 

In summary, the general promise of Moore’s Law is not going to end any time soon. Yet it is not going to be the simple brute-force x0.7 dimensional scaling that dominated the industry for the last 5 decades. Quoting Mark Bohr again, it “will morph and evolve and go in a different direction, such as scaling density by the 3D stacking of components rather than continuing to reduce transistor size.”

P.S. –

A good conference to learn about these new scaling technologies is the IEEE S3S ‘15, in Sonoma, CA, on October 5th thru 8th, 2015. CEA Leti is scheduled to give an update on their CoolCube program and three leading researchers from Berkeley, Stanford and Taiwan’s NLA Lab will present their work on advanced monolithic 3D integration technologies.

Advanced Semiconductor Engineering, Inc. and TDK Corporation announced today that both companies will enter into an agreement to establish a joint venture company to manufacture IC embedded substrates using TDK’s SESUB (Semiconductor Embedded SUBstrate) technology. ASE and TDK plan to own 51 percent and 49 percent, respectively, of the newly created entity. The indicative name of the joint venture company will be ASE Embedded Electronics Incorporated, and its manufacturing facility is planned to be located in the Nantze Export Processing Zone, Kaohsiung City, Taiwan.

TDK developed its proprietary SESUB technology by harnessing its signature technologies in ultrafine processing and materials. The SESUB technology enables semiconductor chips to be thinned down to as low as 50 μm and embedded in a four-layer plastic substrate. TDK’s SESUB technology provides numerous advantages, such as enabling miniaturization by reducing the mounting area on substrates and a thinner profile by achieving a 300 μm thickness. Other advantages include excellent thermal dissipation characteristics, which offer greater design flexibility and inter-chip connection that enhances EMI performance.

ASE SiP solutions using SESUB technology will offer a robust embedded solution in enabling a wide number of applications such as PMIC, sensors and RF tuners etc. The planned joint venture business model aims to leverage on TDK’s success in delivering SESUB technology to the market with ASE’s capabilities in advanced packaging, test and module level solutions for semiconductor miniaturization.

“With the anticipated need for further miniaturization and weight reduction of smartphones and wearable devices in the future, demand for semiconductors embedded in substrates, such as SESUBs, is expected to increase globally,” says Mr. Takehiro Kamigama, CEO and President of TDK Corporation. “TDK has already been producing SESUBs at its Kofu Plant, but to meet the anticipated increase in demand, it will establish the joint company in Taiwan to add to its production capacity with ASE, which possesses technologies including assembly of IC packages and other items, and boasts a world-class performance record in product testing. The joint venture establishment will create a structure for full-scale mass production,” added Mr Takehiro Kamigama.

“ASE serves a diverse group of customers including several major players supplying to the portable and wearable consumer market and is a leader in SIP integration using its advanced packaging solutions and test expertise. TDK, on the other hand, has a proven proprietary embedded substrate technology addressing the market needs of integrating more chips and functions, higher performance, lower power consumption and better heat dissipation onto a smaller form factor,” says Dr Tien Wu, COO, ASE Group. “We see this powerful alliance as an added value to the ASE SIP ecosystem and together, catapulting TDK’s SESUB technology into the forefront as an industry standard,’’ added Dr. Tien Wu.

The proposed establishment of and capital injection into the joint venture company will be subject to various regulatory approvals or consents (including but not limited to the approvals of the Taiwan Fair Trade Commission and Export Processing Zone Administration).

Interconnecting transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, are where the future limitations in performance, power, latency and cost reside.

BY BILL CHEN, ASE US, Sunnyvale, CA; BILL BOTTOMS, 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG, Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI, Toshiba Kangawa, Japan.

Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly that in the aggregate provides enhanced functionality and improved operating characteristics.

In this definition components should be taken to mean any unit whether individual die, MEMS device, passive component and assembled package or sub‐system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level cost-of-ownership.

The mission of the ITRS Heterogeneous Integration Focus Team is to provide guidance to industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics that is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the require- ments for heterogeneous integration in the electronics industry through 2030, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.

Background

The environment is rapidly changing and will require revolutionary changes after 50 years where the change was largely evolutionary. The major factors driving the need for change are:

  • We are approaching the end of Moore’s Law scaling.
  • The emergence of 2.5D and 3D integration techniques
  • The emerging world of Internet of Everything will cause explosive growth in the need for connectivity.
  • Mobile devices such as smartphones and tablets are growing rapidly in number and in data communications requirements, driving explosive growth in capacity of the global communications network.
  • Migration of data, logic and applications to the cloud drives demand for reduction in latency while accommodating this network capacity growth.

Satisfying these emerging demands cannot be accomplished with the current electronics technology and these demands are driving a new and different integration approach. The requirements for power, latency, bandwidth/bandwidth density and cost can only be accomplished by a revolutionary change in the global communications network, with all the components in that network and everything attached to it. Ensuring the reliability of this “future network” in an environment where transistors wear out, will also require innovation in how we design and test the network and its components.

The transistors ‘power consumption in today’s network account for less than 10 percent of total power, total latency and total cost. It is the interconnection of these transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, where the future limitations in performance, power, latency and cost reside. Overcoming these limitations will require heterogeneous integration of different materials, different devices (logic, memory, sensors, RF, analog, etc.) and different technologies (electronics, photonics, plasmonics, MEMS and sensors). New materials, manufacturing equipment and processes will be required to accomplish this integration and overcome these limitations.

Difficult challenges

The top‐level difficult challenges will be the reduction of power per function, cost per function and latency while continuing the improvements in performance, physical density and reliability. Historically, scaling of transistors has been the primary contributor to meeting required system level improvements. Heterogeneous integration must provide solutions to the non‐transistor infrastructure that replace the shortfall from the historical pace of progress we have enjoyed from scaling CMOS. Packaging and test have found it difficult to scale their performance or cost per function to keep pace with transistors and many difficult challenges must be met to maintain the historical pace of progress.

In order to identify the difficult challenges we have selected seven application areas that will drive critical future requirements to focus our work. These areas are:

  • Mobile products
  • Big data systems and interconnect
  • The cloud
  • Biomedical products
  • Green technology
  • Internet of Things
  • Automotive components and systems

An initial list of difficult challenges for Heterogeneous Integration for these application areas is presented in three categories; (1) on‐chip interconnect, (2) assembly and packaging and (3) test. These are analyzed in line with the roadmapping process and will be used to define the top 10 challenges that have the potential to be “show stoppers” for the seven application areas identified above.

On-chip interconnect difficult challenges

The continued decrease in feature size, increase in transistor count and expansion into 3D structures are presenting many difficult challenges. While challenges in continuous scaling are discussed in the “More Moore” section, the difficult challenges of interconnect technology in devices with 3D structures are listed here. Note that this assumes a 3D structure with TSV, optical interconnects and passive devices in interposer substrates.

ESD (Electrostatic Discharge): Plasma damage on transistors by TSV etching especially on via last scheme. Low damage TSV etch process and the layout of protection diodes are the key factors.

CPI (Chip Package Interaction) Reliability [Process]: Low fracture toughness of ULK (Ultra Low‐k) dielectrics cause failures such as delamination. Material development of ULK with higher modulus and hardness are the key factors.

CPI (Chip Package Interaction) Reliability [Design]: A layout optimization is a key for the device using Cu/ULK structure.

Stress management in TSV [Via Last]: Yield and reliability in Mx layers where TSV land is a concern.

Stress management in TSV [Via Middle]: Stress deformation by copper extrusion in TSV and a KOZ (Keep Out Zone) in transistor layout are the issues.

Thermal management [Hot Spot]: Heat dissipation in TSV is an issue. An effective homogenization of hot spot heat either by material or layout optimization are the key factors.

Thermal management [Warpage]: Thermal expansion management of each interconnect layer is necessary in thinner Si substrate with TSV.

Passive Device Integration [Performance]: Higher Q, in other words, thicker metal lines and lower tan dielectrics is a key for achieving lower power and lower noise circuits.

Passive Device Integration [Cost]: Higher film and higher are required for higher density and lower footprint layout.

Implementation of Optical Interconnects: Optical interconnects for signaling, clock distribution, and I/O requires development of a number of optical components such as light sources, photo detectors, modulators, filters and waveguides. On‐chip optical interconnects replacing global inter- connects requires the breakthrough to overcome the cost issue.

Assembly and packaging difficult challenges

Today assembly and packaging are often the limiting factors in performance, size, latency, power and cost. Although much progress has been made with the introduction of new packaging architectures and processes, with innovations in wafer level packaging and system in package for example, a significantly higher rate of progress is required. The complexity of the challenge is increasing due to unique demands of heterogeneous integration. This includes integration of diverse materials and diverse circuit fabric types into a single SiP architecture and the use of the 3rd dimension.

Difficult packaging challenges by circuit fabric

  • Logic: Unpredictable hot spot locations, high thermal density, high frequency, unpredictable work load, limited by data bandwidth and data bottle‐necks. High bandwidth data access will require new solutions to physical density of bandwidth.
  • Memory: Thermal density depends on memory type and thermal density differences drive changes in package architecture and materials, thinned device fault models, test & redundancy repair techniques. Packaging must support low latency, high bandwidth large (>1Tb) memory in a hierar- chical architecture in a single package and/or SiP).
  • MEMS: There is a virtually unlimited set of requirements. Issues to be addressed include hermetic vs. non‐hermetic, variable functional density, plumbing, stress control, and cost effective test solutions.
  • Photonics: Extreme sensitivity to thermal changes, O to E and E to O, optical signal connections, new materials, new assembly techniques, new alignment and test techniques.
  • Plasmonics: Requirements are yet to be determined, but they will be different from other circuit type. Issues to be addressed include acousto‐ magneto effects and nonlinear plasmonics.
  • Microfluidics: Sealing, thermal management and flow control must be incorporated into the package.

Most if not all of these will require new materials and new equipment for assembly and test to meet the 15 year Roadmap requirements.

Difficult packaging challenges by material

Semiconductors: Today the vast majority of semiconductor components are silicon based. In the future both organic and compound semiconductors will be used with a variety of thermal, mechanical and electrical properties; each with unique mechanical, thermal and electrical requirements.

Conductors: Cu has replaced Au and Al in many applications but this is not good enough for future needs. Metal matrix composites and ballistic conductors will be required. Inserting some of these new materials will require new assembly, contacting and joining techniques.

Dielectrics: New high k dielectrics and low k dielectrics will be required. Fracture toughness and interfacial adhesion will be the key parameters. Packaging must provide protection for these fragile materials.

Molding compound: Improved thermal conductivity, thinner layers and lower CTE are key requirements.

Adhesives: Die attach materials, flexible conductors, residue free materials needed o not exist today.

Biocompatible materials: For applications in the healthcare and medical domain (e.g. body patches, implants, smart catheters, electroceuticals), semiconductor‐based devices have to be biocompatible. This involves the integration of new (flexible) materials to comply with specific packaging (form factor) requirements.

Difficult challenges for the testing of heterogeneous devices

The difficulties in testing heterogeneous devices can be broadly separated into three categories: Test Quality Assurance, Test Infrastructure, and Test Design Collaboration.

Test quality assurance needs to comprehend and place achievable quality and reliability metrics for each individual component prior to integration, in order to meet the heterogeneous system quality and reliability targets. Assembly and test flows will become inter- twined and interdependent. They need to be constructed in a manner that maintains a cost effective yield loss versus component cost balance and proper component fault isolation and quantification. The industry will be required to integrate components that cannot guarantee KGD without insurmountable cost penalties and this will require integrator visible and accessible repair mechanisms.

Test infrastructure hardware needs to comprehend multiple configurations of the same device to enable test point insertion at partially assembled and fully assembled states. This includes but is not limited to different component heights, asymmetric component locations, and exposed metal contacts (including ESD challenges). Test infrastructure software needs to enable storing and using volume test data for multiple components that may or may not have been generated within the final integrators data domains but are critical for the final heterogeneous system functionality and quality. It also needs to enable methods for highly granular component tracking for subsequent joint supplier and integrator failure analysis and debug.

Test design collaboration is one of the biggest challenges that the industry will need to overcome. It will be a requirement for heterogeneous highly integrated highly functional systems to have test features co‐designed across component boundaries that have more test coverage and debug capability than simple boundary scans. The challenge
of breaking up what was once the responsibility of a wholly contained design for test team across multiple independent entities each trying to protect IP, is only magnified by the additional requirement that the jointly developed test solutions will need to be standardized across multiple competing heterogeneous integrators. Industry wide collaboration on and adherence to test standards will be required in order to maintain cost and time effective design cycles for highly desired components that traditionally has only been required for cross component boundary communication protocols.

The roadmapping process

The objective of ITRS 2.0 for heterogeneous integration is to focus on a limited number of key challenges (10) that have the greatest potential to be “show stoppers,” while leaving other challenges identified and listed but without focus on detailed technical challenges and potential solutions. In this process collaboration with other Focus Teams and Technical Working Groups will be a critical resource. While we will need collaboration with other groups both inside and outside the ITRS some of the collaborations are critical for HI to address its mission. FIGURE 1 shows the major internal collaborations in three categories.

FIGURE 1. Collaboration priorities.

FIGURE 1. Collaboration priorities.

We expect to review these key challenges and our list of other challenges on a yearly basis and make changes so that our focus keeps up with changes in the key challenges. This will ensure that our efforts remain focused on the pre‐competitive technologies that have the greatest future value to our audience. There are four phases in the process detailed below.

1. Identify challenges for application areas: The process would involve collaboration with other focus teams, technical TWGs and other roadmapping groups casting a wide net to identify all gaps and challenges associated with the seven selected application areas as modified from time to time. This list of challenges will be large (perhaps hundreds) and they will be scored by the HI team by difficulty and criticality.

2. Define potential solutions: Using the scoring in phase (1) a number (30‐40) will be selected to identify potential solutions. The remainder will be archived for the next cycle of this process. This work will be coordinated with the same collabo- ration process defined above. These potential solutions will be scored by probable success and cost.

3. Down select to only the 10 most critical challenges: The potential solutions with the lowest probability of success and highest cost will have the potential to be “show stopping” roadblocks. These will be selected using the scoring above and the focus issues for the HI roadmap. The results of this selection process will be commu- nicated to the relevant collaboration partners for their comments.

4. Develop a roadmap of potential solutions for “show stoppers”: The roadmap developed for the “show stopping” roadblocks shall include analysis of the blocking issue and identification of a number of potential solutions. The collaboration shall include detail work with other units of the ITRS, other roadmapping activity such as the Jisso Roadmap, iNEMI Roadmap, Communications Technology Roadmap from MIT. We are continuing to work with the global technical community: industry, research institutes and academia, including the IEEE CPMT Society.

The blocking issues will be specifically investigated by the leading experts within the ITRS structure, academia, industry, government and research organizations to ensure a broad based understanding. Potential solutions will be identified through a similar collaboration process and evaluated through a series of focused workshops similar to the process used by the ERD iTWG. This process is a workshop where there is one proponents and one critic presenting to the group. This is followed by a discussion and a voting process which may have several iterations to reach a consensus.

The cross Focus Team/TWG collaboration will use a procedure of iteration to converge on an understanding of the challenges and potential solutions that is self‐ consistent across the ITRS structure. An example is illustrated in FIGURE 2.

FIGURE 2. Iterative collaboration process

FIGURE 2. Iterative collaboration process

It is critically important that our time horizon include the full 15 years of the ITRS. The work to anticipate the true roadblocks for heterogeneous integration, define potential solutions and implement a successful solution may require the full 15 years. Among the tables we will include 5 year check points of the major challenges for the key issues of cost, power, latency and bandwidth. In order for this table to be useful we will face the challenge of identifying the specific metric or metrics to be used for each application driver as we prepare the Heterogeneous Integration roadmap chapter for 2015 and beyond.

BILL CHEN is a senior technical advisor for ASE US, Sunnyvale, CA; BILL BOTTOMS is President and CEO of 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG is director of business development at Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI works in the Toshiba’s Center for Semiconductor Research & Development, Kangawa, Japan.

By Pete Singer, Editor-in-Chief

Although the Xpedition was announced last week, it has been used in production for over two years. says five companies have been using it, two of which are extremely large semiconductor companies. “It’s a pretty mature technology,” he said.

Traditionally, chip, package and board designers have used relatively archaic means of communicating, including spreadsheets, whiteboard drawings and Microsoft’s VISIO (a diagramming and vector graphics application). Each group often uses different naming conventions as well, which further complicates co-design efforts.

“They try to use non-EDA technology to figure out an EDA problem,” said John Park, Methodology Architect, Systems Design Division at Mentor Graphics (Longmont, CO).

A new product from Mentor Graphics called Xpedition® Package Integrator provides a new methodology and platform in addition to a new suite of EDA tools. The platform enables chip, package and board designers to easily see how changing various design elements impact adjacent designs, an industry first.

Xpedition allows designers to pull in existing data in whatever form they’re presently using and examine different design considerations such as connectivity across all three design domains. “We’re aggregating people’s existing flow. We’re not replacing them,” Park said.

Park said the development of Xpedition was driven by the general need to simplify co-design, but also to address news challenges created by the Internet of Things (IoT) and new technology such as 2.5 and 3D integration and through-silicon-vias (TSVs). “You’re talking fairly sophis- ticated connectivity management when dealing with multiple die, the interposer and modeling that connec- tivity all the way up to the boards,” Park said. “It’s a pretty challenging problem for most people who have historically tried to use spreadsheets to manage that cross-domain connectivity.”

The Xpedition Package Integrator product also provides the industry’s first formal flow for ball grid array (BGA) ball-map planning and optimization based on an “intelligent pin” concept, defined by user rules. In addition, a new multi-mode connectivity management system (incorporating hardware description language (HDL), spreadsheet and graphical schematic) provides cross-domain pin-mapping and system level cross-domain logical verification (FIGURE 1).

FIGURE 1. With Mentor Graphics Xpedition Package Integrator solution, users manage connectivity in the design environment in which they are most comfortable.

FIGURE 1. With Mentor Graphics Xpedition Package Integrator solution, users manage connectivity in
the design environment in which they are most comfortable.

A modern day CPU or GPU has three of four packaging options, such as package-on-package, micro-BGA, or package-on-package (PiP). People are also targeting multiple end form factors. “It’s not a single board anymore,” Park said. “A lot of customers want to look at the device in the context of smartphone platform, a tablet platform or a set-top box platform, for example.”

One of the main advantages of the new platform is cost reduction by efficient layer reduction, optimized interconnect paths, and streamlined/automated control of the design process. “What’s really changing with IoT and with TSVs and expensive packages is people now want to do cross-domain exploration or path finding,” Park said. People evaluate options largely based on cost, performance and reliability. For example, designers want to look at the pros and cons if they take DRAM off the board and move them into the package.

Mentor Graphics Corporation this week announced the delivery of three new PADS family products starting at five thousand dollars to address the advancing needs of the independent engineer. The new PADS family provides for the wide spectrum of electronics complexity by combining ease of learning and use, characteristic of previous PADS products, with high-productivity design and analysis technologies and unprecedented price-performance value. It builds on the PADS legacy, and in some cases leverages certain technologies of the Xpedition suite.

These independent engineers are typically part of a small to mid-sized company, or members of an isolated team within a large enterprise (e.g. building prototypes, validating reference designs, and performing manufacturability studies), and perform the complete design, analysis and manufacturing data delivery of printed circuit board (PCB) electronic products. In the past, for engineers doing complex design, their only option was to look at enterprise solutions, and for many, these solutions were out of their reach due to budget and heavy infrastructure requirements.

As demands increase for the efficient design of electronic products, the burden often falls on independent engineers to perform the complete process but current lower-priced offerings run out of steam and do not support their complete needs. The design process can often include more than schematic entry and layout of the PCB and may require analysis such as signal integrity, thermal, design-for-manufacturability, and power distribution network integrity. As well, depending on the company, the complexity of the end-product can vary from relatively simple to extremely complex.

“The biggest pressure that we face is being able to produce a design that is good on the first run.” stated Louis Demers, CTO, Obzerv Technologies, Inc. “The PADS tool suite is a very cost-effective design solution that tackles our most complex design challenges, as well as providing a growth path for our future needs. The advantage of going with PADS is that we will be able to converge toward a workable design much quicker, with fewer iterations, fewer expenses and quicker delivery to market. We will also have more time to be bold in our design, driving for maximum performance and functionality.” Obzerv Technologies Inc. designs and manufactures high-end night-vision cameras for mid-range and long-range surveillance applications based on active imaging.

“To achieve maximum engineering efficiency and to optimize our products, our engineers work on board projects from concept through simulation and layout, all the way into manufacturing.” stated John Sherman, vice president, Astek Corporation. “They need to use a broad set of tools, which means tools must be easy to pick up after a period of non-use. They also push the edge on product complexity, with high-frequency, high-density designs. We believe the PADS technology will enable us to easily tackle our complexity challenges, optimizing the productivity of our multi-disciplinary engineers.” Astek Corporation provides storage solutions, test and measurement equipment, and electronic design services for the embedded market.

Technologies in the PADS products that differentiate them from the market include:

• Correct-by-construction methodology: Enabled by a common constraint management system used across the flow to support advanced high-speed topologies and design for manufacture, minimizing design cycle iterations by getting it right the first time.
• Integrated, accurate, easy-to-use analysis and verification technology: Designers can virtually prototype their system powered by the HyperLynx product with signal/power integrity analysis, analog or thermal simulation and advanced full-board rule checks, minimizing expensive, time-consuming physical prototype cycles.
• Highest performing, highest capacity layout environment: Leverages technology powered by the Xpedition product for placement/planning, 2D/3D layout, dynamic power distribution design, and constraint-driven routing including the Sketch Router tool to tackle the most complex layouts.
• Part library access: Engineers can use over 360,000 parts via PartQuest, a fully integrated website that also merges Digi-Key part numbers with symbols and footprints, reducing manual errors and saving time and cost.
• Manufacturing preparation: Validation of the design for fabrication and test, and preparation for manufacturing hand-off and documentation.
• Maintenance of data integrity: Management and archiving of different design revs, and simplification of reviews across the organization.

“Mentor Graphics has long been known for providing…solutions for team design in large enterprises with our Xpedition product line as well as our classic PADS offerings,” stated AJ Incorvaia, general manager of Mentor Graphics Systems Design Division. “But as the industry grows, there is more need for higher productivity design capabilities for the independent engineer. With the PADS product offerings we can better serve the independent engineer with scalable price-performance options from lower priced options up to highly complex design and analysis powered by Xpedition technologies. And as the design organization expands, we offer seamless scalability to our Xpedition Enterprise platform.”

The ability of materials to conduct heat is a concept that we are all familiar with from everyday life. The modern story of thermal transport dates back to 1822 when the brilliant French physicist Jean-Baptiste Joseph Fourier published his book “Théorie analytique de la chaleur” (The Analytic Theory of Heat), which became a corner stone of heat transport. He pointed out that the thermal conductivity, i.e., ratio of the heat flux to the temperature gradient is an intrinsic property of the material itself.

The advent of nanotechnology, where the rules of classical physics gradually fail as the dimensions shrink, is challenging Fourier’s theory of heat in several ways. A paper published in ACS Nano and led by researchers from the Max Planck Institute for Polymer Research (Germany), the Catalan Institute of Nanoscience and Nanotechnology (ICN2) at the campus of the Universitat Autònoma de Barcelona (UAB) (Spain) and the VTT Technical Research Centre of Finland (Finland) describes how the nanometre-scale topology and the chemical composition of the surface control the thermal conductivity of ultrathin silicon membranes. The work was funded by the European Project Membrane-based phonon engineering for energy harvesting (MERGING).

The results show that the thermal conductivity of silicon membranes thinner than 10 nm is 25 times lower than that of bulk crystalline silicon and is controlled to a large extent by the structure and the chemical composition of their surface. Combining state-of-the-art realistic atomistic modelling, sophisticated fabrication techniques, new measurement approaches and state-of-the-art parameter-free modelling, researchers unravelled the role of surface oxidation in determining the scattering of quantized lattice vibrations (phonons), which are the main heat carriers in silicon.

Both experiments and modelling showed that removing the native oxide improves the thermal conductivity of silicon nanostructures by almost a factor of two, while successive partial re-oxidation lowers it again. Large-scale molecular dynamics simulations with up to 1,000,000 atoms allowed the researchers to quantify the relative contributions to the reduction of the thermal conductivity arising from the presence of native SiO2 and from the dimensionality reduction evaluated for a model with perfectly specular surfaces.

Silicon is the material of choice for almost all electronic-related applications, where characteristic dimensions below 10nm have been reached, e.g. in FinFET transistors, and heat dissipation control becomes essential for their optimum performance. While the lowering of thermal conductivity induced by oxide layers is detrimental to heat spread in nanoelectronic devices, it will turn useful for thermoelectric energy harvesting, where efficiency relies on avoiding heat exchange across the active part of the device.

The chemical nature of surfaces, therefore, emerges as a new key parameter for improving the performance of Si-based electronic and thermoelectric nanodevices, as well as of that of nanomechanical resonators (NEMS). This work opens new possibilities for novel thermal experiments and designs directed to manipulate heat at such scales.