Category Archives: 3D Integration

GLOBALFOUNDRIES today announced the addition of nine new partners to its growing RFwave Partner Program, including Akronic, Ask Radio, Catena, University of Waterloo Centre for Intelligent Antenna and Radio Systems (CIARS), Giga Solution, Helic, Incize, Mentor Graphics and Xpeedic Technology. These new partners will provide unique mmWave test and characterization capabilities along with design services, IP and EDA solutions that will enable GF clients to rapidly implement RF designs in applications spanning Internet-of-Things (IoT), mobile, RF connectivity, and networking markets.

The RFwave Partner Program builds upon GF’s industry-leading radio frequency (RF) solutions, such as FD-SOI, RF CMOS (bulk and advanced CMOS nodes), RF SOI and silicon germanium (SiGe) technologies. The program provides a low-risk, cost-effective path for designers seeking to build highly optimized RF solutions for a range of wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.

“As the RFwave program continues to expand, partners play a critical role in helping to serve our growing number of clients and extend the reach of our RF ecosystem by providing innovative RF-tailored solutions and services,” said Mark Ireland, vice president of ecosystem partnerships at GF. “These new partners will help drive deeper engagement and enhance technology collaboration, including tighter interlock around quality, qualification and development methodology, enabling us to deliver advanced highly integrated RF solutions.”

GF is focused on building strong ecosystem partnerships with industry leaders. With the RFwave program, GF’s partners and clients can now benefit from a greater availability of resources to deliver innovative, highly optimized RF solutions. The new partners join current RFwave Program members including asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC.

GOWIN Semiconductor today announced that its GW1NS product family was named a 2018 Arm TechCon Innovation Award finalist for design innovation of the year.

GOWIN’s GW1NS-2C is the first of its microprocessor-based SoC family.  The architecture of the product is unique in that it uses a shared resource technology.  Typically, a microprocessor is designed with the core of the processor connected to peripherals via a bus architecture.  The peripherals could include JTAG, SRAM memory, I/O interfaces, PLL’s, oscillators, etc.  The GW1NS-2C shares its peripheral resources with a barebone Arm Cortex M3 to leverage the complete system for size and power.  In addition, because the peripheral functionality is located inside the FPGA portion of the SoC, it is possible to change the peripheral functionality by reprogramming the FPGA fabric.  This allows for complete flexibility in a SoC environment that no other microprocessor product can offer today.

The Arm TechCon Innovation Awards program celebrates leading-edge Arm-based technologies that have spawned new applications and sparked innovation in systems design. Arm TechCon, the world’s leading conference and exhibition showcasing Arm-based technologies, will be held Oct. 16-18 at the San Jose Convention Center.

A tour of finalists’ booths and their technologies will be conducted at Arm TechCon Wednesday Oct. 17 at 3:30 p.m. Winners will then be announced at 5 p.m. in the expo theater. For more information and to register for the event, please visit armtechcon.com.

“We are honored to receive this recognition from Arm.  As a partner, they have been very supportive of our approach to innovation,” said Scott Casper, Director of Sales, GOWIN Semiconductor.  “The GW1NS family demonstrates incredible functionality and flexibility needed for the success of today’s system designs.  We are happy to be accelerating growth in this field.”

Synopsys, Inc. (Nasdaq: SNPS) today announced the Synopsys Design Platform fully supports TSMC’s wafer-on-wafer (WoW) direct stacking and chip-on-wafer-on-substrate (CoWoS®) advanced packaging technologies. The design platform enablement, combined with the 3D-IC reference flow, enables customer deployments for high-performance, high-connectivity multi-die technology in mobile computing, network communication, consumer, and automotive electronics applications.

The platform-wide Synopsys solution includes multi-die and interposer layout capture, physical floorplanning, and implementation, as well as parasitic extraction and timing analysis coupled with physical verification. Key products and features of the Synopsys Design Platform supporting TSMC’s advanced WoW and CoWoS packaging technologies include:

  • IC Compiler™ II place-and-route: Supports multi-die floorplanning and implementation, including interposer and 3D stack-die generation, TSV placement and connectivity assignment, orthogonal multi-layer, 45-degree single-layer, and interface inter-die block generation for inter-die extraction and checking
  • StarRC™ extraction: Supports modeling of TSV and backside RDL metal extraction, silicon interposer extraction, and inter-die coupling capacitance extraction
  • IC Validator: Supports full-system DRC and LVS verification, inter-die DRC, and LVS checking of inter-die interface
  • PrimeTime® signoff analysis: Full-system static timing analysis, supports multi-die static timing analysis (STA)

“High-performance advanced 3D silicon fabrication and wafer stacking technologies require new EDA features and flows to support the corresponding increase in design and verification complexity,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We extend our collaboration with Synopsys to deliver design solutions for TSMC’s CoWoS and WoW advanced packaging technologies. We look forward to our mutual customers benefiting from the enabled design solutions, boosting designer productivity and accelerating time-to-market.”

“Built through deep collaboration, the design solution and reference flow for TSMC’s WoW and CoWoS chip integration solutions will enable our mutual customers to achieve optimal quality of results,” said Michael Jackson, corporate vice president of marketing and business development for Synopsys’ Design Group. “The Synopsys Design Platform and methodologies will allow designers to confidently meet their schedules for cost-effective, high-performance, and low-power multi-die solutions.”

Synopsys jointly highlighted the advances and collaborations of TSMC 2.5D and 3D technologies in a paper titled “Onwards and Upwards: How Xilinx is Leveraging TSMC’s Latest Integration and Packaging Technologies with Synopsys’ Platform-wide Solution for Next-generation Designs” at the TSMC Open Innovation Platform® (OIP) Ecosystem Forum on October 3, 2018 in Santa Clara, California.

To scale down a transistor below a 5nm node is one of the vital concerns for VLSI industry as there are various challenges due to the shrinking of components. Several researches are going on worldwide to overcome the challenges of future technology nodes. Among them, this article reviews the potential transistor structures and materials like Carbon Nano-tube FET, Gate-All-Around FET, and Compound Semiconductors as solutions to overcome the problems of scaling the existing silicon FinFET transistor below 5nm node.

By Pavan H Vora, Akash Verma, Dhaval Parikh

The ‘Semiconductor era’ started in 1960 with the invention of the integrated circuit. In an integrated circuit, all the active-passive components and their interconnection are integrated on a single silicon wafer, offering numerous advantages in terms of portability, functionality, power, and performance. The VLSI industry is following Moore’s law for many decades, which says, “the number of transistors on a chip becomes double approximately every two years”. To get the benefits of a scaled-down transistor, VLSI industry is continuously improving transistor structure and material, manufacturing techniques, and tools for designing IC. Various techniques, which have been adopted for transistors so far, include high-K dielectric, metal gate, strained silicon, double patterning, controlling channel from more than one side, silicon on insulator and many more techniques. Some of these techniques are discussed in ‘A Review Paper on CMOS, SOI and FinFET Technology’[1].

Nowadays, the demand of the internet of things, autonomous vehicles, machine learning, artificial intelligence, and internet traffic is growing exponentially, which acts as a driving force for scaling down transistor below the existing 7nm node for higher performance. However, there are several challenges of scaling down a transistor size.

Issues with Sub-Micron Technology:

Every time we scale down a transistor size, a new technology node is generated. We have seen transistor sizes such as 28nm, 16nm, etc. Scaling down a transistor enables faster switching, higher density, low power consumption, lower cost per transistor, and numerous other gains. The CMOS (complementary metal-oxide-semiconductor) transistor base IC technology performs well up to 28nm node. However, the short channel effects become uncontrollable if we shrink down CMOS transistor below 28 nm. Below this node, a horizontal electric field generated by drain-source supply tries to govern the channel. As a result, the gate is unable to control leakage paths, which are far from the gate.

16nm/7nm Transistor Technology: FinFet and FD-SOI:

The VLSI industry has adopted FinFET and SOI transistor for 16nm and 7nm nodes, as both the structures are able to prevent the leakage issue at these nodes. The main objective of both the structures is to maximize gate-to-channel capacitance and minimize drain-to-channel capacitance[1]. In both transistor structures, the channel thickness scaling is introduced as the new scaling parameter. As the channel thickness is reduced, there are no paths, which are far from the gate area. Thus, gates have a good control over the channel, which eliminates short channel effects.

In Silicon-on-Insulator (SOI) transistor, a buried oxide layer is used, which isolates the body from the substrate shown in Figure 1(a).Owing to the BOX layer, drain-source parasitic junction capacitances are reduced, which results in faster switching. The main challenge with the SOI transistor is that it is difficult to manufacture a thin silicon layer on the wafer.

Figure 1: a) FD-SOI Structure b) FinFET Structure and Channel

FinFET, which is also called as tri-gate controls channel is shown from three sides in Figure 1(b).  There is a thin vertical Si-body, which looks like a back fin of fish wrapped by the gate structure. A width of the channel is almost two times Fin height. Thus, to get higher driving strength, a multi-Fin structure is used. One of the gains with FinFET is higher driving current. The main challenge with FinFET is the complex manufacturing process.

Challenges with Technology Node below 5nm: What Next?

Reducing the body thickness results into lower mobility as surface roughness scattering increases. Since FinFET is a 3-D structure, it is less efficient in terms of thermal dissipation. Also, if we scale down the FinFET transistor size further, say below 7nm, the leakage issue becomes dominant again. Consequently, many other problems come into consideration like self-heating, threshold flattening, etc. These concerns lead to research on other possible transistor structures and replacing existing materials with new effective materials.

According to the ITRS roadmap (International Technology Roadmap for Semiconductors), the next technology nodes are 5nm, 3nm, 2.5nm, and 1.5nm. Many different types of research and studies are going on in VLSI industry and academia for potential solutions to deal with these future technology nodes. Here we discuss some promising solutions like carbon nanotube FET, GAA transistor structure, and compound semiconductor for future technology nodes.

Figure 2: Transistor Technology Roadmap

CNTFET – Carbon Nano Tube FET:

CNT (Carbon Nanotube) showcases a new class of semiconductor material that consists of a single sheet of carbon atoms rolled up to form a tubular structure. CNTFET is a field-effect transistor (FET) that uses semiconducting CNT as a channel material between the two metal electrodes, which behave as source and drain contacts. Here we will discuss carbon nanotube material and how it is beneficial to FET at a lower technology node.

  • What is a Carbon Nanotube?

CNT is a tubular shaped material, made of carbon, having diameters measurable on the nanometer scale. They have a long and hollow structure and are formed from sheets of carbon that are one atom thick. It is called “Graphene”. Carbon nanotubes have varied structures, differing in length, thickness, helicity, and the number of layers. Majorly, they are classified as Single Walled Carbon Nanotube (SWCNT) and Multi-Walled Carbon Nanotube (MWCNT). As shown in Figure 3(a), one can see that SWCNTs are made up of a single layer of graphene, whereas MWCNTs are made up of multiple layers of graphene.

Figure 3: a) Single Walled and Multi Walled CNTs b) Chirality Vector Representation

  • Properties of Carbon Nanotube:

The carbon nanotube delivers excellent properties in areas of thermal and physical stability as discussed below:

  1. Both Metallic and Semiconductor Behavior

The CNT can exhibit metallic and semiconductor behavior. This change in behavior depends on the direction in which the graphene sheet is rolled. It is termed as chirality vector. This vector is denoted by a pair of integer (n, m) as shown in Figure 3(b). The CNT behaves as metallic if ‘n’ equals to ‘m’ or the difference of ‘n’ and ‘m’ is the integral multiple of three or else it behaves as a semiconductor [2].

  1. Incredible Mobility

SWCNTs have a great potential for application in electronics because of their capacity to behave as either metal or as a semiconductor, symmetric conduction and their capacity to carry large currents. Electrons and holes have a high current density along the length of a CNT due to the low scattering rates along the CNT axis. CNTs can carry current around 10 A/nm2, while standard metal wires have a current carrying capacity that is only around 10 nA/nm2[3].

  1. Excellent Heat Dissipation

Thermal management is an important parameter for the electronic devices’ performance. Carbon nanotubes (CNTs) are well-known nanomaterials for excellent heat dissipation. Moreover, they have a lesser effect of the rise in temperature on the I-V characteristics as compared to silicon [4].

CNT in Transistor Applications: CNFET

The bandgap of carbon nanotubes can be changed by its chirality and diameter and thus, the carbon nanotube can be made to behave like a semiconductor. Semiconducting CNTs can be a favorable candidate for nanoscale transistor devices for channel material as it offers numerous advantages over traditional silicon-MOSFETs. Carbon nanotubes conduct heat similar to the diamond or sapphire. Also, they switch more reliably and use much less power than silicon-based devices [5].

In addition, the CNFETS have four times higher trans-conductance than its counterpart. CNT can be integrated with a High-K material, which is offering good gate control over the channel. The carrier velocity of CNFET is twice as compared to MOSFET, due to increased mobility. A carrier mobility of N-type and P-type CNFET is similar in offering advantages in terms of same transistor size. In CMOS, PMOS (P-type metal-oxide-semiconductor) transistor size is approximately 2.5 times more than NMOS (N-type metal-oxide-semiconductor) transistor as mobility values are different.

The Fabrication process of CNTFET is a very challenging task as it requires precision and accuracy in the methodologies.Here we discuss the Top-gated CNTFET fabrication methodology.

The first step in this technique starts from the placement of carbon nanotubes onto the silicon oxide substrate. Then the individual tubes are isolated. Source and drain contacts are defined and patterned using advanced lithography. The contact resistance is then reduced by refining the connection between the contacts and CNT. The deposition of a thin top-gate dielectric is performed on the nanotube via evaporation technique. Lastly, to complete the process, the gate contact is deposited on the gate dielectric [6].

Figure 4: Concept of Carbon-Nanotube FET

Challenges of CNTFET:

There are lots of challenges in the roadmap of commercial CNFET technology.  Majority of them have been resolved to a certain level, but a few of them are yet to be overcome. Here we will discuss some of the major challenges of CNTFET.

  1. Contact Resistance

For any advanced transistor technology, the increase in contact resistance due to the low size of transistors becomes a major performance problem. The performance of the transistor degrades as the resistance of contacts increases significantly due to the scaling down of transistors. Until now, decreasing the size of the contacts on a device caused a huge drop in execution — a challenge facing both silicon and carbon nanotube transistor technologies [7].

  1. Synthesis of Nanotube

Another challenge with CNT is to change its chirality such that it behaves like a semiconductor. The synthesized tubes have a mixture of both metals and semiconductors. But, since only the semiconducting ones are useful for qualifying to be a transistor, engineering methodologies need to be invented to get a significantly better result at separating metal tubes from semiconducting tubes.

  1. To develop a non-lithographic process to place billions of these nanotubes onto the specific location of the chip poses a challenging task.

Currently, many engineering teams are carrying out research about CNTFET devices and their logic applications, both in the industries and in the universities. In the year 2015, researchers from one of the leading semiconductor companies succeeded in combining metal contacts with nanotubes using “close-bonded contact scheme”. They achieved this by putting a metal contact at the ends of the tube and making them react with the carbon to form different compounds. This technique helped them to shrink contacts below 10 nanometers without compromising the performance [8].

Gate-All-Around FET: GAAFET

One of the futuristic potential transistor structures is Gate-all-around FET. The Gate-all-around FETs are extended versions of FinFET. In GAAFET, the gate material surrounds the channel region from the four directions. In a simple structure, a silicon nanowire as a channel is wrapped by the gate structure. A vertically stacked multiple horizontal nanowires structure is proven excellent for boosting current per given area. This concept of multiple vertically stacked gate-all-around silicon nanowire is shown in Figure 5.

Figure 5: Vertically Stacked Nanowires GAAFET

Apart from silicon material, some other materials like InGaAs, germanium nanowires can also be utilized for better mobility.

There are many hurdles for GAAFET in terms of complex gate manufacturing, nanowires, and contacts. One of the challenging processes is fabricating nanowires from the silicon layer as it requires a new approach for the etching process.

There are many research labs and institute working for Gate-all-around FET for lower nodes. Recently, Leuven based R&D firm claimed that they achieved excellent electrostatic control over a channel with GAAFET at sub 10nm diameter nanowire. Last year, one of the leading semiconductor companies unveiled a 5nm chip, which contains 30 billion transistors on a 50mm2chip using stacked nanowire GAAFET technology. It claimed to achieve 40% improvement in performance compared to 10nm node or 70% improvement in power consumption at the same performance.

Compound Semiconductors:

Another promising way to scale down a transistor node is the selection of novel material that exhibits higher carrier mobility. A compound semiconductor with ingredients from columns III and V are having higher mobility compared to silicon. Some compound semiconductor examples are Indium Gallium Arsenide (InGaAs), Gallium Arsenide (GaAs), and Indium Arsenide (InAs). According to various studies, integration of compound semiconductor with FinFET and GAAFET showing excellent performance at lower nodes.

The main concerns with compound semiconductor are large lattice mismatch between silicon and III-V semiconductor, resulting in defects of the transistor channel. One of the firms developed a FinFET containing V-shaped trenches into the silicon substrate. These trenches filled with indium gallium arsenide and forming the fin of the transistor. The bottom of the trench is filled with indium phosphide to reduce the leakage current. With this trench structure, it has been observed that defects terminate at the trench walls, enabling lower defects in the channel.

Conclusion:

From the 22nm node to 7nm node, FinFETs have been proven successful and it may be scaled down to one more node. Beyond that, there are various challenges like self-heating, mobility degradation, threshold flattening, etc. We have discussed how carbon nanotube’s excellent properties of motilities, heat dissipation, high current carrying capability offer promising solutions for replacing existing silicon technology. As the stack of horizontal nanowire opened a “fourth gate”, Gate-all-around transistor structure is also a good candidate for replacing vertical Fin structure of FinFET for achieving good electrostatic property. It is not clear what comes next in the technology roadmap. However, in the futuristic transistor technology, there must be changes of existing material, structure, EUV (Extreme ultraviolet) lithography process, and packaging to sustain Moore’s law.

References:

[1]  Pavan Vora, Ronak Lad, “A Review Paper on CMOS, SOI and FinFET Technology”, www.design-reuse.com/articles/

[2]  P.A Gowri Sankar, K. Udhaya Kumar, “Investigating The Effect of Chirality On Coaxial Carbon Nanotube Field Effect Transistor”, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET)

[3] Rashmita Sahoo, S.K Sahoo, “Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation”, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

[4] Yijian Ouyang and Jing Guo, “Heat dissipation in carbon nanotube transistors”, Appl. Phys. Lett. 89, 183122 (2006)

[5] Philip G. Collins & Phaedon Avouris, “Nanotubes for Electronics”, Scientific American 283, 62 – 69 (2000)

[6] Wind, S. J.; Appenzeller, J.; Martel, R.; Derycke, V.; Avouris, Ph. (2002). “Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes”, Applied Physics Letters. 80 (20): 3817. Bibcode:2002ApPhL..80.3817W.

[7] Aaron D. Franklin, Wilfried Haensch, “Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors”, 72nd Device Research Conference

[8] IBM, “IBM Research Breakthrough Paves Way for Post-Silicon Future with Carbon Nanotube Electronics”, https://www-03.ibm.com/press/us/en/pressrelease/47767.wss

About Authors:

Pavan Vora

Pavan Vora is working as an ASIC Physical Design Engineer at eInfochips, an Arrow company. He has more than 3 years of experience in ASIC designs for cutting technology nodes such as 12nm, 16nm FinFET, and 28nm. Pavan has expertise in ASIC P&R, LEC, LVS, Static Timing Analysis, Signal EM, DRC, and IR drop and has been awarded a Gold Medal in Master of Engineering in VLSI System Design.

Akash Verma

Akash Verma is working as an ASIC Trainee Engineer at eInfochips, an Arrow company. He has completed his bachelors in Electronics & Communication from the GIT, Gandhinagar. He is currently working on networking ASIC chip at 7nm FinFET technology, in which his accountabilities include block level APR, Static Timing Analysis and Physical Verification. His interest lies in Analog Mixed Signal designs and EDA tool’s algorithmic methodologies.

Dhaval Parikh

Dhaval Parikh is working as a Technical Manager at eInfochips, an Arrow company. He has more than 11 years of industry experience and has worked in various ASIC designs of IP’s & SoC’s, from 180nm to cutting technology node 7nm. He has been responsible for all the aspects of physical design and verification along with executing multiple projects simultaneously.

About eInfochips:

eInfochips, an Arrow company, is a global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure.

Along with Arrow’s $27B in revenues, 19,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients through Arrow Connect.

“2017 was an excellent year for CIS , with growth observed in all segments except computing,” commented Pierre Cambou, Principal Analyst, Technology & Market, Imaging at Yole Développement (Yole). Driven by new applications, the industry’s future remains on strong footing.

Yole announces its annual technology & market analysis focused on the CIS industry, from 2017 to 2023, titled: Status of the CMOS Image Sensor Industry. In 2017 the CIS market reached US$13.9 billion. The market research & strategy consulting company forecasts a 9.4% CAGR between 2017 and 2023, driven mainly by smartphones integrating additional cameras to support functionalities like optical zoom, biometry, and 3D interactions.

Yole proposes this year again a comprehensive technology & market analysis of the CMOS Image Industry. In addition to a clear understanding of the CIS ecosystem, analysts detail in this new edition, 2017-2023 forecasts, a relevant description of the M&A activities, an impressive overview of the dual and 3D camera trends for mobile. Mobile and consumer applications are also well detailed in this 2018 edition, with a deep added-value section focused on technology evolution.
In collaboration with Jean-Luc Jaffard, formerly at STMicroelectronics and part of Red Belt Conseil, Pierre Cambou pursued his investigation all year long and reveals today the status of the CIS industry.

2017 saw aggregated CIS industry revenue of US$13.9 billion. And 5 years later, the consulting company Yole announces more than US$ 23 billion. The YoY growth hit a peak at 20% due to the exceptional increase in image sensor value, across almost all markets, but primarily in the mobile sector. “CIS keeps its momentum”,confirms Pierre Cambou from Yole.

Revenue is dominated by mobile, consumer, and computing, which represent 85% of total 2017 CIS revenue. Mobile alone represents 69%. Security is the second-largest segment, behind automotive.

The CIS ecosystem is currently dominated by the three Asian heavyweights: Sony, Samsung, and Omnivision. Europe made a noticeable comeback. Meanwhile, the US maintains a presence in the high-end sector.

The market has benefited from the operational recovery of leading CIS player Sony, which captured 42% market share. “…Apple iPhone has had a tremendous effect on the semiconductor industry, and on imaging in particular. It offered an opportunity for its main supplier, Sony, to reach new highs in the CIS process, building on its early advances in high-end digital photography…”, explains Pierre Cambou in its article: Image sensors have hugely benefited from Apple’s avant-garde strategy posted on i-micronews.com.

The CIS industry is able to grow at the speed of the global semiconductor industry, which also had a record year, mainly due to DRAM revenue growth. CIS have become a key segment of the broader semiconductor industry, featuring in the strategy of most key players, and particularly the newly-crowned industry leader Samsung. Mobile, security and automotive markets are all in the middle of booming expansion, mostly benefiting ON Semiconductor and Omnivision.

These markets are boosting most players that are able to keep up with technology and capacity development through capital expenditure. The opportunities are all across the board, with new players able to climb the rankings, such as STMicroelectronics and Smartsense. Technology advancement and the switch from imaging to sensing is fostering innovation at multiple levels: pixel, chip, wafer, all the way to the system.

CIS sensors are also at the forefront of 3D semiconductor approaches. They are a main driver in the development of artificial intelligence. Yole’s analysts foresee new techniques and new applications all ready to keep up the market growth momentum… A detailed description of this report is available on i-micronews.com, imaging reports section.

Synopsys, Inc. (Nasdaq: SNPS) today announced delivery of automotive-grade DesignWare® Controller and PHY IP for TSMC’s 7-nanometer (nm) FinFET process. The DesignWare LPDDR4x, MIPI CSI-2 and D-PHY, PCI Express® 4.0, and security IP implement advanced automotive design rules for TSMC 7-nm process to meet the stringent reliability and operation requirements of ADAS and autonomous driving system-on-chips (SoCs). The delivery of automotive-grade IP in TSMC’s 7-nm process further extends Synopsys’ broad portfolio of ISO 26262 ASIL Ready IP solutions in FinFET processes, which has been adopted by more than a dozen leading automotive companies. The IP meets stringent AEC-Q100 temperature requirements, delivering high reliability for automotive SoCs. In addition, the included automotive safety packages with Failure Modes, Effects, and Diagnostic Analysis (FMEDA) reports enable designers to save months of development effort and accelerate SoC-level functional safety assessments.

“TSMC’s and Synopsys’ long history of successful collaboration has enabled our mutual customers to benefit from the latest technology advancements to help them achieve their performance, power, and area goals,” said Suk Lee, TSMC senior director of the Design Infrastructure Marketing Division. “Delivering automotive-grade DesignWare IP for TSMC’s 7-nanometer FinFET process underscores Synopsys’ continued commitment to providing designers with the quality IP necessary to meet their aggressive design goals and get products to market faster.”

“Developing automotive-grade IP requires intensive knowledge and strict processes to ensure the IP meets stringent ISO 26262 functional safety and AEC-Q100 reliability standards,” said John Koeter, vice president of marketing for IP at Synopsys. “Synopsys continues to make significant investments in developing automotive-qualified IP for the most advanced processes, such as TSMC’s 7-nanometer, to help designers accelerate their SoC-level qualification effort for functional safety, reliability, and automotive quality.”

STATS ChipPAC Pte. Ltd. (“STATS ChipPAC” or the “Company”), a provider of advanced semiconductor packaging and test services, announced Friday that the Board of Directors of its holding company, Jiangsu Changjiang Electronics Technology Co., Ltd (‘JCET’) has appointed Dr. Lee Choon Heung as Chief Executive Officer (‘CEO’) for JCET Group, as well as Chief Executive Officer and Chairman for STATS ChipPAC.

Dr. Lee brings to JCET a wealth of expertise and veteran leadership with 20 years of extensive semiconductor packaging and test experience. Dr. Lee served in several senior management positions at Amkor Technology Inc. including head of their R&D centre, head of global procurement, group vice president, senior vice president and Chief Technology Officer. Dr. Lee, holds a Ph.D. in Theoretical Solid State Physics from Case Western Reserve University, currently holds 59 industry patents, and has published 19 academic papers around the world.

“We are excited about the opportunity to bring on board an industry leader of the calibre of Dr. Lee Choon Heung as our new JCET Group CEO,” stated JCET Chairman, Mr. Wang Xinchao. “We are confident in his ability to lead JCET as we continue our growth in both technology and scale moving forward,” continued Mr. Wang. Mr. Wang will continue in his role as Chairman of JCET Group.

The JCET Board of Directors and the management team also expressed their utmost gratitude and appreciation to Dr. Han Byung Joon and Mr. Lai Chih-Ming for their outstanding leadership and valuable contributions during their tenure at STATS ChipPAC. Dr. Han is resigning as chairman of the board of STATS ChipPAC. Mr. Lai will now serve in a new role as executive vice president of JCET Group.

IC Insights’ September Update to The McClean Report shows that as a result of a 51% forecasted increase in the China pure-play foundry market this year (Figure 1), China’s total share of the 2018 pure-play foundry market is expected to jump by five percentage points to 19%, exceeding the share held by the rest of the Asia-Pacific region. Overall, China is forecast to be responsible for 90% of the $4.2 billion increase in the total pure-play foundry market in 2018.

Figure 1

With the recent rise of the fabless IC companies in China, the demand for foundry services has also risen in that country.  In total, pure-play foundry sales in China jumped by 26% last year to $7.5 billion, almost triple the 9% increase for the total pure-play foundry market.  Moreover, in 2018, pure-play foundry sales to China are forecast to surge by an amazing 51%, more than 6x the 8% increase expected for the total pure-play foundry market this year.

Although all of the major pure-play foundries are expected to register double-digit sales increases to China this year, the biggest increase by far is forecast to come from pure-play foundry giant TSMC.  Following a 44% jump in 2017, TSMC’s sales into China are forecast to surge by another 79% in 2018 to $6.7 billion. As a result, China is expected to be responsible for essentially all of TSMC’s sales increase this year with China’s share of the company’s sales more than doubling from 9% in 2016 to 19% in 2018.

As shown in Figure 2, much of TSMC’s sales surge into China has come over the past year, with 2Q18 sales into the country being almost double what they were in 3Q17.  A great deal of the company’s recent sales surge into China has been driven by increased demand for custom devices going into the cryptocurrency market.  It turns out that many of the large cryptocurrency fabless design firms are based in China and most of them have been turning to TSMC to produce their advanced chips for these applications.  It should be noted that TSMC includes its cryptocurrency business as part of its High-Performance Computing segment.

Figure 2

While TSMC has enjoyed a great ramp up in sales for its cryptocurrency business over the past year, the company has indicated that a slowdown is expected for this business in the second half of this year.  It appears that the demand for cryptocurrency devices is highly dependent upon the price for the various cryptocurrencies (the most popular of which is Bitcoin).  As a result, the recent plunge in the price for Bitcoins (going from over $15K per Bitcoin in January of this year to less than $7K in September), and other cryptocurrencies as well, is lowering the demand for these ICs.  Moreover, since TSMC realized from the beginning that the cryptocurrency market was going to be volatile, the company did not adjust its capacity plans based on the recent strong cryptocurrency demand and does not incorporate cryptocurrency business assumptions into its forecasts for future long-term growth.

GLOBALFOUNDRIES announced this week at its annual Global Technology Conference (GTC), that the company’s mobile-optimized 8SW 300mm RF SOI technology platform has been qualified and is in production. Several clients are currently engaged for this RF SOI process, tailored to accommodate aggressive LTE and Sub-6 GHz standards for front-end module (FEM) applications, including 5G IoT, mobile device and wireless communications.

Leveraging the 300mm RF SOI process, 8SW delivers significant performance, integration and area advantages with up to 70 percent power reduction and 20 percent smaller overall die size compared to the previous generation. The technology enables superior LNAs (low-noise amplifiers) switches and tuners by supplying higher voltage handling and a best-in-class on-resistance (Ron) and off-capacitance (Coff) for reduced insertion loss with high isolation. The optimized RF FEM platform helps designers develop solutions that enable extremely fast downloads, higher quality connections and reliable data connectivity for today’s 4G/LTE Advanced operating frequencies and future sub-6GHz 5G mobile and wireless communication applications.

“GF has now delivered more than 40 billion RF SOI chips for the world’s smart devices, and this latest generation of RF SOI technology is another proof point that we’re poised to meet accelerating global demand for solutions that deliver seamless, reliable data connectivity everywhere,” said Christine Dunbar, vice president of RF business unit at GF. “The mobile market continues to favor RF SOI, and GF’s industry leading, 8SW process in 300 mm manufacturing is specifically designed to help our clients take advantage of more frequency bands that will deliver ultra-reliable communications across high-band LTE and future 5G applications.”

“We are proud to support GF’s new advanced and differentiated 8SW technology on 300mm RF SOI substrates and to continue our long-term strategic engineering and manufacturing collaboration enabling next-generation connectivity solutions,” said Dr. Bernard Aspar, EVP, Soitec. “We are ready to deliver the 300mm RF SOI substrates in high volumes to meet GF clients’ growing market demands.”

“SEH congratulates GF on their 8SW platform. SEH believes 300 mm RF SOI products are an important technology, whose time has come,” Nobuhiko Noto, General Manager of SOI Division at SEH. “SEH has been a long time partner on RF technology and looks forward to supporting GF for their future generations of RF technologies as well. We will continue to be a supplier to the 300 mm RF SOI market as it grows.”

GF’s manufacturing legacy and deep technical expertise in RF SOI process has resulted in more than 40 billion RF SOI chips shipped for next-generation RF-enabled devices.

8SW is manufactured on GF’s 300mm production line at Fab 10 in East Fishkill, N.Y., enabling clients to take advantage of advanced tooling and processes for faster time-to-market with industry-leading RF SOI. Qualified process design kits are available now.

As part of the company’s new focus on intensifying investment in differentiation, GLOBALFOUNDRIES announced today at its annual Global Technology Conference (GTC), plans to introduce a full set of new technology features to its 14/12nm FinFET offering. The features are designed to deliver better scalability and performance for applications in high-growth markets such as hyperscale datacenters and autonomous vehicles.

In today’s data-intensive world, there is an insatiable demand for high-performance chips to process and analyze the surge of information produced by connected devices. GF’s FinFET offering is an ideal platform for designing high-performance, power-efficient system-on-chips (SoCs) for the most demanding compute applications. The new platform features will improve power, performance and scalability by delivering transistor enhancements optimized for ultra-high performance and enhanced RF connectivity, as well as new high-speed, high-density memories for emerging enterprise and cloud security needs.

“We are committed to enhancing our differentiated offerings to help clients get more value out of their investments in each technology generation,” said Dr. Bami Bastani, senior vice president of business units at GF. “By introducing these new features to our FinFET offering we are delivering powerful technology enhancements that will enable clients to extend performance and create innovative products for the next generation of intelligent systems.”

GF’s 14/12nm FinFET platform provides advanced performance and power with significant cost advantages. The feature-rich enhancements being added to the platform include:

  • Ultra-high density: Delivers increased transistor density through continued improvements to the 12LP design library (7.5T), combined with SRAM and analog advances, delivering a smaller die area to support clients in core compute, connect and store applications, as well as mobility and consumer.
  • Performance boost: Increases performance through reducing SRAM Vmin by 100mV and standby leakage current by ~50 percent – to extend performance for both existing and emerging applications in machine learning and artificial intelligence.
  • RF/analog: Provides a full suite of passive devices, ultra-thick metal and LDMOS options for advanced RF performance with Ft/Fmax at 340GHz targeting <6GHz RF SoCs with high digital content.
  • Embedded memory: Offers ultra-high security, one-time programmable (OTP) and multi-time programmable (MTP) embedded non-volatile (eNVM) memory for emerging enterprise, cloud and communication applications. Using physically undetectable charge-trapping technology (CTT) enables security solutions including “physically unclonable device” capabilities and efficient non-volatile memories for higher levels of SoC integration. GF’s CTT solution requires no additional processing or masking steps and delivers up to twice the density of similar OTP solutions based on dielectric fuse technology.

The company’s 14LPP technology can provide up to 55 percent higher device performance and 60 percent lower total power compared to 28nm technologies, while its 12LP technology provides as much as a 15 percent improvement in circuit density and more than a 10 percent improvement in performance over 16/14nm FinFET solutions on the market today. GF’s leading-edge FinFET platform has been in high-volume production since early 2016, and is Automotive Grade 2 ready.