Category Archives: 3D Integration

Synopsys, Inc. today announced new extensions to its open-source Interconnect Technology Format (ITF) which enable modeling of complex device and interconnect parasitic effects at the advanced 10-nanometer (nm) process node. The new extensions include modeling of variation effects due to multi-patterning technology (MPT). Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) (member list available at www.imtab.org), an IEEE-ISTO Federation Member Program, to define and ratify these new extensions. They will be available in the upcoming open-source ITF version 2015.06.

“Enabling productive design and analysis for a colored layout flow, while also providing a solution to model increased parasitic variation due to MPT approaches, is critical at 10nm,” said Bari Biswas, vice president of engineering for extraction solutions at Synopsys and chair of IMTAB. “Through our collaboration with IMTAB members and leading foundries, Synopsys developed an innovative solution that extended the existing variation models in ITF to become intrinsically color-aware to more accurately model mask dependency while fitting seamlessly into a designer’s existing flow.”

“ITF continues to be the cornerstone of parasitic modeling in the semiconductor industry,” said Marco Migliaro, President, IEEE-ISTO. “The new 10nm models represent the fourth successive generation of model extensions fostered by the IMTAB consortium.  IEEE-ISTO looks forward to continuing our support of the IMTAB mission to drive increased tool interoperability through the ITF common open-source modeling format.”

MPT is an evolution of the double patterning technology (DPT) first introduced by foundries at the 20nm process node, and it further extends the use of immersion lithography to 10nm and below. However, MPT imposes tighter requirements on design implementation and analysis to support layout decomposition into different masks (coloring) and manage increased variation due to misalignment of the multiple masks. Synopsys’ advanced MPT solution ratified by IMTAB for 10 nm includes color-aware models that cover all leading foundry manufacturing techniques including sequential litho-etch patterning, for example, triple patterning (LELELE) and quadruple patterning (LELELELE), as well as spacer-assisted/self-aligned patterning, for example, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

In addition to MPT modeling, Synopsys has introduced other ITF extensions approved by IMTAB for more accurate via resistance and device capacitance extraction at advanced FinFET process nodes. At 10nm, via resistivity has increased significantly with growing conductor environment context, so the existing self-aligned via resistance variation model has been extended to include coverage from top and bottom conductors. In addition, new ITF models have been added to accurately extract the floating gate to diffusion contact capacitance for polycide on diffusion edge (PODE) devices and spacer dielectric between gate polycide and contact, both of which are critical to regulating device performance.

More information on the new ITF extensions for 10nm can be found in the ITF specifications version 2015.06, targeted for release in June 2015.

Additional proposals for 10nm and below process modeling are planned for review in the next IMTAB meeting scheduled for Tuesday, June 9, 2015 in San Francisco, CA, USA.

Today, KLA-Tencor Corporation announced two new systems that support advanced semiconductor packaging technologies: CIRCL-AP and ICOS T830. Designed for characterization and monitoring of the diverse processes used in wafer-level packaging, CIRCL-AP enables all-surface wafer defect inspection, review and metrology at high throughput. The ICOS T830 provides fully automated optical inspection of integrated circuit (IC) packages, leveraging high sensitivity with 2D and 3D measurements to determine final package quality for a wide range of device types and sizes. Both systems help IC manufacturers and outsourced semiconductor assembly and test (OSAT) facilities address challenges, such as finer feature sizes and tighter pitch requirements, as they adopt innovative packaging techniques.

“Consumer mobile electronics continue to drive production of smaller, faster and more powerful devices,” stated Brian Trafas, chief marketing officer of KLA-Tencor. “Advanced packaging technologies offer device performance advantages, such as increased bandwidth and improved energy efficiency. The packaging production methods, however, are more complex—involving the implementation of typical front-end IC manufacturing processes, such as chemical mechanical planarization and high aspect ratio etch, and unique processes, such as temporary bonding and wafer reconstitution. By combining our expertise in front-end semiconductor manufacturing process control with experience gained through collaborations at key R&D sites and industry consortia, we have developed flexible and efficient inspection solutions that can help address packaging challenges from wafer-level to final component.”

The CIRCL-AP includes multiple modules that utilize parallel data collection for fast, cost-efficient process control of advanced wafer-level packaging processes. It supports a range of packaging technologies, including wafer-level chip scale packaging, fan-out wafer-level packaging and 2.5D/3D IC integration using through silicon vias (TSVs). The industry-proven 8-Series serves as the CIRCL-AP’s front side defect inspection and metrology module, which couples LED scanning technology with automated defect binning to reduce nuisance and speed detection of critical packaging defects, such as TSV cracks and redistribution layer shorts. The CV350i module, based on KLA-Tencor’s VisEdge technology, enables leading detection, binning and automated review of wafer edge defects and metrology for critical edge trim and bonding steps in the TSV process flow. With multiple imaging and illumination modes, the Micro300 module can produce high precision 2D and 3D metrology for bump, redistribution and TSV processes. Utilizing a flexible architecture, the CIRCL-AP can be configured with one or more modules to address the requirements of specific packaging applications, while the handler supports bonded, thinned and warped substrates.

The ICOS T830 extends the industry-leading ICOS component inspection series to address yield challenges associated with advanced packaging types, including lead frame, fan-out wafer-level, flip-chip and stacked packages. Enhanced package visual inspection capability, xPVI, enables high sensitivity detection of top and bottom component surface defects, such as voids, scratches, pits, chips and exposed wires. To ensure quality standards are being met for leading-edge memory and logic packaged devices, the ICOS T830 offers high speed 3D ball, lead and capacitor metrology, package z-height measurement and component side inspection. The xCrack+ inspection station enables accurate detection of micro-crack defects—a key failure mechanism of thinner components used in mobile applications. The ICOS T830 incorporates high-throughput operation of four independent inspection stations and high-speed sorting of the inspected packaged components to achieve cost-effective component quality control.

Multiple CIRCL-AP systems in various configurations have been installed worldwide for use in development and production of TSV, fan-out wafer-level packaging and other wafer-level packaging technologies. ICOS T830 systems are in use at many worldwide IC packaging facilities, providing accurate feedback on package quality across a range of device types and sizes. To maintain the high performance and productivity demanded by semiconductor packaging providers, the CIRCL-AP and ICOS T830 systems are backed by KLA-Tencor’s global, comprehensive service network.

A*STAR’s Institute of Microelectronics (IME), together with Amkor Technologies, NANIUM, STATS ChipPAC, NXP Semiconductors, GLOBALFOUNDRIES, Kulicke & Soffa, Applied Materials, Inc., Dipsol Chemicals, JSR Corporation, KLA-Tencor, Kingyoup Optronics, Orbotech and Tokyo Ohka Kogyo have formed a High-Density Fan-Out Wafer Level Packaging (FOWLP) consortium to extend FOWLP capabilities for applications in devices such as smart phones, tablets, navigation tools and gaming consoles.

These devices call for application processors with greater system capabilities such as increased memory and bandwidth, as well as faster processing speed to support myriad demanding applications and functions, while consuming low power. At the same time, the sheer market volume1 for such devices necessitates system cost reduction.

FOWLP is a low-cost packaging technology for system scaling which enables multiple chips to be integrated in a small form factor on a single package. However, the adoption of conventional FOWLP technology for high performance, multi-functional devices is being challenged by pin-count density of a few hundreds of I/Os per device package. These limitations have a direct impact on its capability to support increased system requirements and performance.

The consortium aims to provide solutions to overcome these limitations. It will develop a High-Density FOWLP test vehicle capable of supporting thousands of I/Os and characterising the package for die shift, die protrusion and wafer warpage analysis that will enable system scaling for smartphones and mobile tablets. Concurrently, tight wiring to accommodate increased pin counts using fine pitch multi-layer redistribution layer technology will be demonstrated for large area FOWLP while maintaining its signal/power integrity and reliability.

“System integration is necessary to enable diverse functionalities with high performance in future applications across a wide spectrum of industries including computing and networking, healthcare, consumer electronics, transport and automotive. With the High-Density Fan-Out Wafer Level Packaging consortium, IME continues to add to its portfolio of advanced packaging platforms so as to provide wide-ranging solutions for the continued evolution and different needs of complex and demanding devices,” said Prof. Dim-Lee Kwong, Executive Director of IME.

“Amkor is pleased to participate in the High-Density FOWLP consortium to help accelerate the adoption of this next-generation package platform technology. As a leader in the space, working to drive packaging and test technologies forward is one of our core objectives. We expect advanced platforms like High-Density FOWLP to become the prevailing packaging format for much of the advanced integration market, including mobile and high performance products,” said Mr. Ron Huemoeller, Senior Vice President, Advanced Product & Technology Development, IP of Amkor Technology, Inc.

“Market applications will always be our industry’s main drivers,” commented Mr. Armando Tavares, President of the Executive Board at NANIUM. “In times of More-than-Moore, I/Os requirements have been increasing steadily, as they translate into higher integration, improved performance, minimal form-factor and cost-effectiveness. The development of High-Density Fan-Out Wafer-Level Packaging technology represents a step towards fine-pitch multi-layer redistribution, which in turn will allow us to build higher-density structures. These will significantly increase the amount of interconnects enabled by FOWLP, turning this technology into an IC packaging platform for chip-to-chip interconnect with a higher I/O and at a competitive cost.

NANIUM regards IME’s initiative of creating a consortium as a very insightful one. Through the combination of our know-how and manufacturing capabilities with IME’s technology development expertise, we will surely contribute to the development of our FOWLP technology roadmap, to the benefit of our customers.”

“High-Density Wafer-Level Fan-Out Packaging technology enables advanced system scaling for form factor limited and cost challenged applications,” said Mr. Ramakanth Alapati, Director of Package Architecture and Customer Technology at GLOBALFOUNDRIES. “GLOBALFOUNDRIES appreciates IME’s effort to identify robust solutions needed for a cost-effective high volume manufacturing approach to wafer level packaging.”

“The strong collection of companies who have joined the consortium and our shared commitment to expanding the capabilities of FOWLP reflects the promising value of this technology for a wide range of high performance applications. This collaboration will accelerate the important development activities we have been focusing on such as ultra thin package profiles, finer line/space widths down to 2μm/2μm and multi-layer redistribution in order to achieve smart system integration at a lower cost for our customers,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

“This consortium has members from the entire supply chain, and with the combined experience and knowledge of all the members, the solution developed will be industry leading and targeted for high volume manufacturing benefiting the industry as a whole,” said Mr. Cheam Tong Liang, Vice President, Advanced Packaging Business Line & Corporate Strategy of Kulicke & Soffa.

Semiconductor equipment manufacturer ClassOne Technology announced today that it has signed a joint electrochemical deposition (ECD) applications lab agreement with Shanghai Sinyang Semiconductor Materials Co., Ltd.  Sinyang, China’s premier supplier of ECD chemicals, is purchasing ClassOne electroplating equipment and will be providing a site for demonstrating ClassOne’s tools in the Chinese marketplace. SPM International Ltd., ClassOne’s representative in China will also be providing product support and process assistance.

“This collaborative lab will be the first of its kind in the region,” said Byron Exarcos, President of ClassOne Technology. “Now, in a single location, users will be able to see the advanced performance of ClassOne’s electroplating tools and Sinyang’s electroplating chemicals and also be able to evaluate processes. It allows us to provide a complete solution — and a significant convenience — to users throughout the region.”

“We are looking forward to working with customers on the Solstice LT plating system because it is a high-performance tool and will provide an excellent real-world laboratory for ongoing enhancement of our chemicals,” said Dr. Wang Su, Vice President of Sinyang. “The new working arrangement will also enable us to provide direct input to ClassOne as they develop future generations of wet processing equipment.”

Shanghai Sinyang is purchasing ClassOne’s Solstice LT Electroplating System and Trident Spin Rinse Dryer (SRD). The Solstice LT is a two-chamber plating development tool designed for <200mm wafers. In Sinyang’s applications, one chamber will be dedicated to copper plating and the second to nickel plating, with the Trident SRD servicing both process streams. This will provide significant flexibility while substantially reducing cycle time and streamlining process development. The new equipment will be installed at the Sinyang lab facility in Shanghai, which is scheduled to begin live demonstrations in late May. The lab will be able to plate virtually all metals except gold, and it can also cross-reference with all chemicals for comparison benchmarks.

In addition to the LT development tool, ClassOne also offers the Solstice S8, an 8-chamber, fully-automated electroplating system for high-volume production needs. These tools are particularly well suited to wafer level packaging (WLP), through silicon via (TSV) and other applications that are important for MEMS, Sensors, LEDs, RF, Power and many other devices.

ClassOne Technology products have been described as “Advanced Wet Processing Tools for the Rest of Us” because they address the needs of many cost-conscious users. The company’s stated aim is to provide advanced yet affordable alternatives to the large systems from the large manufacturers. ClassOne supplies a range of innovative new wet processing tools, including its Solstice Electroplating Systems, Trident Spin Rinse Dryers and Trident Spray Solvent Tools (SSTs).

Duke University researchers are working to advance the tools and methodologies used to test 3D integrated circuits (ICs), which promise to help ensure the ongoing development of higher performance, lower power semiconductor chips.

Sponsored by Semiconductor Research Corporation (SRC), the Duke research focuses on testing of 3D integration since testing remains an obstacle that hinders mainstream adoption and mass manufacturing of 3D technology.

“Even though manufacturing processes for 3D integration are nearly mature, a barrier to technology adoption is our insufficient understanding of 3D testing issues and the need for design-for-testability (DFT) solutions,” said Krishnendu Chakrabarty, professor of Electrical and Computer Engineering at Duke. “Test challenges for 3D ICs must be addressed before high-volume production can be practical. Breakthroughs in  test technology will allow higher levels of silicon integration, fewer defect escapes, and commercial exploitation.”

The Duke research has introduced probing solutions that may enable pre-bond and post-bond testing of Through Silicon Vias (TSVs) and logic dies used in manufacturing semiconductor components. The Duke team has also introduced design-for-test (DFT) innovations for 3D stacked chip technologies.

Specifically, it is paramount to stack “known good dies” to ensure a high manfufacturing yield with stacked technology. However, due to the small feature sizes of TSVs and micro-bumps, it is extremely difficulty to probe wafers at a pre-bond stage. The Duke team has presented an innovative solution to this problem by probing multiple micro-bumps at the same time, thereby shorting TSVs and forming a TSV network. Aggregated measurements from TSV networks can then be used to detect defects in TSVs as well as in the die logic.

Furthermore, by developing the DFT structures that must be included on the die and the measurement infrastructure needed on the probe cards, the research demonstrates that the proposed approach is robust to process variations as well variations in contact resistance to the potentially non-uniform nature of probe contacts.

Next, in the area of post-bond testing, the Duke team developed a test-architecture optimization and test scheduling solution that minimizes test time by considering various stages of 3D assembly. The research included formal models based on integer linear programming as well as fast heuristic solutions. An especially innovative aspect of this research is its solution for recovering the delay overhead introduced by the DFT that is added for 3D stack testing.

“We have shown that retiming can be used to redistribute the slack on critical paths, whereby the delay overhead due to 3D DFT can be reduced to zero. This is a remarkable research breakthrough, which shows that there is something called a ‘free lunch’ after all,” said Brandon Noia, a Ph.D. student who was part of the Duke team and a recipient of the SRC Ph.D. Fellowship. Now graduated and part of SRC member company, AMD, Noia also received the European Design and Automation Association 2014 Outstanding Dissertation Award for this research.

The Duke research has already led to three U.S. patents being granted in 2014, and multiple semiconductor and electronic design automation (EDA) companies are collaborating with the Duke team on incorporating the research into their test processes—with at least one company prepared to have measurement data on chips available this fall.

“Among all EDA challenges for 3D designs, tools and methodologies for 3D stacked IC testing are critical, and this research from Duke goes a long way toward removing these obstacles,” said William Joyner, SRC director of Computer-Aided Design and Test.

Consider these eight issues where the packaging team should be closely involved with the circuit design team.

BY JOHN T. MACKAY, Semi-Pac, Inc., Sunnyvale, CA

Today’s integrated circuit designs are driven by size, performance, cost, reliability, and time- to-market. In order to optimize these design drivers, the requirements of the entire system should be considered at the beginning of the design cycle—from the end system product down to the chips and their packages. Failure to include packaging in this holistic view can result in missing market windows or getting to market with a product that is more costly and problematic to build than an optimized product.

Chip design

As a starting consideration, chip packaging strategies should be developed prior to chip design completion. System timing budgets, power management, and thermal behavior can be defined at the beginning of the design cycle, eliminating the sometimes impossible constraints that are given to the package engineering team at the end of the design. In many instances chip designs end up being unnecessarily difficult to manufacture, have higher than necessary assembly costs and have reduced manufacturing yields because the chip design team used minimum design rules when looser rules could have been used.

Examples of these are using minimum pad-to-pad spacing when the pads could have been spread out or using unnecessary minimum metal to pad clearance (FIGURE 1). These hard taught lessons are well understood by the large chip manufacturers, yet often resurface with newer companies and design teams that have not experienced these lessons. Using design rule minimums puts unnecessary pressure on the manufacturing process resulting in lower overall manufacturing yields.

Packaging 1

FIGURE 1. In this image, the bonding pads are grouped in tight clusters rather than evenly distributed across the edge of the chip. This makes it harder to bond to the pads and requires more-precise equipment to do the bonding, thus unnecessarily increasing the assembly cost and potentially impacting device reliability.

Packaging

Semiconductor packaging has often been seen as a necessary evil, with most chip designers relying on existing packages rather than package customization for optimal performance. Wafer level and chipscale packaging methods have further perpetuated the belief that the package is less important and can be eliminated, saving cost and improving performance. The real fact is that the semiconductor package provides six essential functions: power in, heat out, signal I/O, environmental protection, fan-out/compatibility to surface mounting (SMD), and managing reliability. These functions do not disappear with the implementation of chipscale packaging, they only transfer over to the printed circuit board (PCB) designer. Passing the buck does not solve the problem since the PCB designers and their tools are not usually expected to provide optimal consideration to the essential semiconductor die requirements.

Packages

Packaging technology has considerably evolved over the past 40 years. The evolution has kept pace with Moore’s Law increasing density while at the same time reducing cost and size. Hermetic pin grid arrays (PGAs) and side-brazed packages have mostly been replaced by the lead-frame-based plastic quad flat packs (QFP). Following those developments, laminate based ball grid arrays (BGA), quad flat pack no leads (QFN), chip scale and flip-chip direct attach became the dominate choice for packages.

The next generation of packages will employ through-silicon vias to allow 3D packaging with chip-on-chip or chip-on-interposer stacking. Such approaches promise to solve many of the packaging problems and usher in a new era. The reality is that each package type has its benefits and drawbacks and no package type ever seems to be completely extinct. The designer needs to have an in-depth understand of all of the packaging options to determine how each die design might benefit or suffer drawbacks from the use of any particular package type. If the designer does not have this expertise, it is wise to call in a packaging team that possesses this expertise.

Miniaturization

The push to put more and more electronics into a smaller space can inadvertently lead to unnec- essary packaging complications. The ever increasing push to produce thinner packages is a compromise against reliability and manufacturability. Putting unpackaged die on the board definitely saves space and can produce thinner assemblies such as smart card applications. This chip-on-board (COB) approach often has problems since the die are difficult to bond because of their tight proximity to other components or have unnecessarily long bond wires or wires at acute angles that can cause shorts as PCB designers attempt to accommodate both board manufacturing line and space realities with wire bond requirements.

Additionally, the use of minimum PCB design rules can complicate the assembly process since the PCB etch-process variations must be accommodated. Picking the right PCB manufacturer is important too as laminate substrate manufacturers and standard PCB shops are most often seen as equals by many users. Often, designers will use material selections and metal systems that were designed for surface mounting but turn out to be difficult to wire bond. Picking a supplier that makes the right metallization tradeoffs and process disciplines is important in order to maximize manufacturing yields

Power

Power distribution, including decoupling capaci- tance and copper ground and power planes have been mostly a job for the PCB designer. This is a wonder to most users as to why decoupling is rarely embedded into the package as a complete unit. Cost or package size limitations are typically the reasons cited as to why this isn’t done. The reality is that semiconductor component suppliers usually don’t know the system requirements, power fluctuation tolerance and switching noise mitigation in any particular installation. Therefore power management is left to the system designer at the board level.

Thermal Management

Miniaturization results in less volume and heat spreading to dissipate heat. Often, there is no room or project funds available for heat sinks. Managing junction temperature has always been the job of the packaging engineer who must balance operating and ambient temperatures and packaging heat flow.

Once again, it is important to develop a thermal strategy early in the design cycle that includes die specifics, die attachment material specification, heat spreading die attachment pad, thermal balls on BGA and direct thermal pad attachment during surface mount.

Signal input/output

Managing signal integrity has always been the primary concern of the packaging engineer. Minimizing parasitics, crosstalk, impedance mismatch, transmission line effects and signal atten- uation are all challenges that must be addressed. The package must handle the input/output signal requirements at the desired operating frequencies without a significant decrease in signal integrity. All packages have signal characteristics specific to the materials and package designs.

Performance

There are a number of factors that impact perfor- mance including: on-chip drivers, impedance matching, crosstalk, power supply shielding, noise and PCB materials to name a few. The performance goals must be defined at the beginning of the design cycle and tradeoffs made throughout the design process.

Environmental protection

The designer must also be aware that packaging choices have an impact on protecting the die from environmental contamination and/or damage. Next- generation chip-scale packaging (CSP) and flip chip technologies can expose the die to contami- nation. While the fab, packaging and manufacturing engineers are responsible for coming up with solutions that protect the die, the design engineer needs to understand the impact that these packaging technologies have on manufacturing yields and long-term reliability.

Involve your packaging team

Hopefully, these points have provided some insights on how packaging impacts many aspects of design and should not be relegated to just picking the right package at the end of the chip design. It is important that your packaging team be involved in the design process from initial specification through the final design review.

In today’s fast moving markets, market windows are shrinking so time to market is often the important differentiator between success and failure. Not involving your packaging team early in the design cycle can result in costly rework cycles at the end of the project, having manufacturing issues that delay the product introduction or, even worse, having impossible problems to solve that could have been eliminated had packaging been considered at the beginning of the design cycle.

System design incorporates many different design disciplines. Most designers are proficient in their domain specialty and not all domains. An important byproduct of these cross-functional teams is the spreading of design knowledge throughout the teams, resulting in more robust and cost effective designs.

Packages are changing. Acoustic methods provide a way to image and analyze them.

BY TOM ADAMS, SONOSCAN, INC., Elk Grove Village, IL

By the year 2020, the design, dimensions and materials of various electronic component packages will have changed in varying degrees from their current forms. PEMs (plastic-encap-sulated microcircuits) will still be in production, but likely with shrinking sizes and better (or less expensive) encapsulants. Stacking of die connected by non-wire methods such as through-silicon vias (TSVs) will be in production. These and other package types, along with components such as ceramic chip capacitors, will need to be inspected for internal anomalies, typically by non-destructive acoustic micro imaging. This article takes a forward look at some of the challenges and changes that may take place in various packages and the possible advances in acoustic methods for imaging and analyzing them.

In electronic components, the business of acoustic micro imaging is to make visible and and analyze internal structural features. Acoustic micro imaging tools such as Sonoscan’s C-SAM series are used to image anomalies and defects, or to verify their absence. The defects are typically gaps – delaminations, voids, cracks, non-bonds and the like – but an acoustic micro imaging tool will also reveal surprises such as the out-of-place or missing die sometimes noted in counterfeit components.

New acoustic imaging methods

Today, the prevalent imaging mode for acoustic micro imaging tools is what is commonly called the Time Domain Amplitude Mode. The scanning transducer sends a pulse of VHF (5 to 100 MHz) or UHF (above 100 MHz) ultrasound into an x-y location. A few micro-seconds later, the transducer receives a number of echoes from the depth of interest. The amplitude of the highest-amplitude echo within a gate (time window) is used to assign a pixel value to that x-y location. The other echoes are ignored.

At the moment, there are about a dozen other imaging modes which collect data in different ways and which yield different information and images about a sample. One example: it is important in imaging IGBT modules to measure and map the thickness of the solder bonding the heat sink to the ceramic raft above. Irregular solder thickness often means that the raft is tilted or warped (and thus may restrict heat dissipation). The Time Difference mode will map the interface. This mode ignores echo amplitude altogether and uses the arrival time of the echoes to measure and map the thickness of the solder. Irregular solder thickness means that the raft is tilted or warped (and thus may restrict heat dissipation). Other acoustic imaging modes use other techniques to detect thickness variations.

The Frequency Domain mode produces multiple images of the target depth in a sample. Each image is made using echoes within a very narrow frequency range (e.g., 102.0-103.5 MHz). This mode is useful in samples having subtle anomalies or defects that may be hard to discern with, say, Amplitude Mode.

A new mode is typically developed when the user of an acoustic micro imaging tool expresses the need to push acoustic imaging beyond its current capabilities in order to solve a specific inspection problem. In some instances an existing mode that was previously developed for research purposes is found to be useful for emerging sample types. It is very likely that new acoustic imaging modes will developed as electronic components and assemblies continue to evolve.

A recently developed mode is the Echo Integral Mode. It gives a view similar to, but more informative than, the Amplitude Mode. While Amplitude Mode picks the highest single amplitude to assign a pixel value, The Echo Integral Mode uses the sum of the amplitude of all the echoes at a given x-y coordinate to determine the pixel color for that coordinate. This approach makes it easier to see subtle local differences in, say, the quality of a bond between two materials.

FIGURE 1 is the Thru-Scan mode image of a plastic BGA package. Thru-Scan pulses ultrasound into the top of the package and uses a sensor beneath the package to read the amplitude of the arriving ultrasound at each x-y location. Gap-type defects block ultrasound and thus appear in a Thru-Scan image as black acoustic shadows.

FIGURE 1. Thru-Scan image shows acoustic shadows of anomalies in a BGA package, but gives no depth information.

FIGURE 1. Thru-Scan image shows acoustic shadows of anomalies in a BGA package, but gives no depth information.

In Figure 1, the black features within the die at center are surely significant anomalies, but an engineer cannot tell from this Thru-Scan image what depth they lie at: are they in the die attach material or in the substrate below?

At left in FIGURE 2 is the Amplitude Mode image of the die area. This image is gated on (reads echoes only from) the die attach depth, and ignores echoes from other depths. The black dots are not features in the gated depth, but are the acoustic shadows of voids in the mold compound above the die. The die area itself is rather uniformly pale gray, with no features of note. The image at right used the Echo Integral Mode, also gated on the die attach material. Using the average amplitude of all the echoes at of millions of x-y coordinates gave a different result: there are significant differences in brightness. The large bright area marked by arrows is a gap-type defect in the die attach, and there are other, smaller defects of the same type. The defects imaged as black shadows by Thru-Scan are imaged here as near-white defects by the Echo Integral Mode. They are clearly in the die attach, and not in the substrate. The roughly spherical feature in the upper right of the Thru-Scan image, however, is the shadow of the void in the mold compound above the die.

FIGURE 2. Amplitude mode (left) shows no defects, but Echo Integral Mode (right) shows locations of defects in the die attach.

FIGURE 2. Amplitude mode (left) shows no defects, but Echo Integral Mode (right) shows locations of defects in the die attach.

Components will continue to shrink

Sonoscan’s laboratories have for some time been imaging PEMs that are only 200 microns thick and 3mm x 3mm in area. The die is typically less than 100 microns thick. In some ways, the small dimensions are an advantage in acoustic imaging: the plastic encapsulant scatters and absorbs ultrasound, so the less encapsulant the pulse and the resulting echo need to travel through, the better the resolution in the acoustic image. Such a component may be imaged with the very high frequency of 230 MHz, rather than the 15 MHz to 100 MHz of larger plastic packages. Higher frequency means better spatial resolution in the acoustic image.

One of the most commonly imaged non-PEM components is the ceramic chip capacitor, where the goal is to image delaminations and cracks that can lead to leakage between electrode layers. The very smallest ceramic chip capacitors currently being manufactured measure 0.010 inch by 0.005 inch. They can be imaged acoustically, but extremely small dimensions make imaging time-consuming.

Mid-end components

So named because they involve both front-end and back-end processes, mid-end components are typically assembled by mounting flip chips onto a wafer and then encapsulating the flip chips with plastic before dicing the wafer. They have been described as non-wired QFNs.

What has evolved is that some mid-end components can be imaged well enough to see details of the solder bump bonds, while others cannot. Sonoscan has developed transducers having an acoustic frequency that is low enough to get through the plastic encapsulant, and high enough to give good details about the bump bonds.

But many mid-end components have an encap- sulant that is only partly transparent to ultrasound. Gross features and defects will be visible, but not the details of the bump bonds, which will probably become even smaller in the future. The alternative is to use the Thru-Scan imaging mode. Any gap in between, such as a break in a solder bump, will block the arriving ultrasound and be visible as a black feature. These acoustic shadows contain no information about the depth of a feature, but the relatively simple design along with experience with a given mid-end component are helpful.

The evolution of package design may in time alleviate the encapsulant problem. The trend is toward more chip-on-wafer type designs, and toward ever-smaller dimensions. The encapsulants may perhaps become unnecessary; their departure would enhance acoustic inspection.

Stacked die

Individual components typically have industry standards that can be used to judge the risk posed by a void in the die attach material or a delamination along a lead finger. Stacked die have no industry standards; presumably each maker of stacked die uses their own guidelines to reduce field failures.

Die stacks can be imaged acoustically before encapsulation, and in the future some may be imaged after encapsulation, particularly if ultrasound-friendly encapsulants are used. In both situations, the same problem occurs: each pulse encountering a material interface is partly reflected and partly transmitted across the interface. Unencapsulated stacks are typically imaged during development in order to refine assembly processes. Even a four-die stack (that has at least eight interfaces) can generate so many echoes that it becomes very difficult to identify the echo being sent by the delamination of the adhesive on the top of die #3.

For unencapsulated stacks, this problem has largely been solved by software developed jointly by Sonoscan and the Technical University of Dresden. The software uses material properties and dimensions to create a virtual stack as much like the physical stack as possible, and works out the imaging techniques, which are then further refined on the physical stack. The goal is to identify the echoes that were returned from specific depths of interest – e.g., the interface between the bottom surface of die #6 and the adhesive beneath it. By repeatedly moving between the virtual sample and the physical sample, the imaging parameters are defined that will show the echoes at this depth.

Nearly all memory devices are stacked, and the die are wire-bonded to each other. But there are stacks have many different configurations; one common configuration puts a small memory chip on top of a larger processing chip.

It’s hard to tell where the architecture of die stacks may go from here. In some stacks, through-silicon vias (TSVs) will replace wires. Defects such as delamina- tions will be visible acoustically, but whether the TSVs will be visible acoustically is difficult to judge at this point. What manufacturers want to see is that each TSV is filled. Their diameters are already extremely small. Whether acoustic methods will be devised to make them nondestructively visible is not known yet.

A long-standing problem in imaging typical PEMs is that a delamination on the back side of the die paddle cannot be imaged when scanning the top side of the PEM. Before the PEM is surface-mounted, it can simply be flipped over and imaged from the back side. After mounting, only the top surface is available for scanning. The problem is that there are too many interfaces: the pulsed ultrasound must cross the top surface of the plastic, the plastic-to-die interface, the die-to-die attach interface, and the die attach-to-die paddle interface. This is essentially the same problem encountered in the imaging of stacked die. In theory, a delamination between the die paddle and the plastic below it can be located and imaged by the software developed for die stacks.

Package-on-package

Package-on-package assemblies, such as a package containing one or more memory die on top of a package containing one or more logic die, are beginning to appear in Sonoscan’s testing laboratories. These package designs have some advantages over the stacking of die; for example, if one of the two packages is found to be defective before assembly, it can be replaced, while the logic package is retained. It seems likely that the popularity of these assemblies will increase in the next few years.

After the two packages are bonded together, the chief structural reliability concern is the adhesive between the two packages. This is where gap-type defects, primarily voids, may be found. If present, voids put stress on the solder joints for the BGA balls.

How acoustic imaging is performed depends on the structure of the assembly. Normal reflection-mode pulse-echo imaging can sometimes be used, but the assembly is likely to have numerous material interfaces that could limit the effectiveness of this method. Because internal structural defects in this assembly are largely limited to voids at a specific known depth, it often makes more sense to use the Thru-Scan mode to reveal the voids.

Interposers

The term “interposer” is used rather loosely to describe a redistribution layer between a top die and a lower die or printed circuit board. chip and the solder balls that make connection with a substrate. In terms of acoustic imaging, interposers behave much like flip chips, in that the depth of interest is between two structures.

The common defects are delaminations, signif- icant because they are capable of attracting contaminants (and thus causing corrosion) and of expanding through thermal cycling. The growth of chips having advanced processing capabilities will likely make the acoustic imaging of interposers more frequent.

Summary

The advantage of acoustic micro imaging tools is their ability to image nondestructively gap-type anomalies and certain other anomalies (tilting, warping) in electronic materials. In recent years, the original Amplitude Mode has been joined by roughly a dozen other modes that push imaging capabilities into new areas.

It can be expected that electronic components will continue to add their own capabilities and to reduce their physical dimensions. Some components will become more difficult to image; others, particularly those that become thinner or that use acoustically friendly materials, may permit the use of higher frequencies to image smaller features. Since there is no good non-destructive substitute for acoustic modes, engineers who demand reliability may want to apply acoustic micro imaging to new device configurations and keep track of new acoustic imaging modes.

Supplier Hub answers the needs of a changing semiconductor industry. 

BY LUC VAN DEN HOVE, imec, Leuven, Belgium

Supplier HubOur semiconductor industry is a cyclical business, with regular ups and downs. But we have always successfully rebounded, with new technologies that have brought on the next generation of electronic products. Now however, the industry stands at an inflection point. Some of the challenges to introduce next generation technologies are larger than ever before. Overcoming this point will require, in our opinion, a tighter collaboration than ever. To accommodate that collaboration, we have set up a new Supplier Hub, a neutral platform where researchers, IC producers, and suppliers work on solutions for technical challenges. This collaboration will allow the industry to overcome the inflection point and to move on to the next cycle of success, driven by the many exciting application domains that appear on the horizon.

Call for a new collaboration model

The formulas for the industry’s success have changed. Device structures are pushing the limits of physics, making it challenging to continue progressing according to Moore’s Law. Intricate manufacturing requirements make process control ever more difficult. Also chip design is more complex than ever before, requiring more scrutiny, analysis and testing before manufacturing can even begin. And the cost of manufacturing equipment and setting up a fab has risen exponentially, shutting out many smaller companies and forcing equipment and material suppliers to merge.

In that context, more and more innovation is coming from the supplier community, both from equipment and material suppliers. But as processes are approaching some fundamental limits, such as material limits, chemical, physical limits, it is also for suppliers becoming more difficult to operate and develop next-generation process steps in an isolated way. An earlier and stronger interaction among suppliers is needed.

All this makes a central and neutral platform more important than ever. That insight and the requests we got from partners set imec on the path to organizing a supplier hub. A hub that is structured as a neutral, open innovation R&D platform, a platform for which we make a substantial part of our 300mm cleanroom floor space available, even extending our facilities. It is a platform where suppliers and manufacturers collaborate side-to- side with the researchers developing next-generation technology nodes.

Organizing the supplier hub is a logical evolution in the way we have always set up collaborations with and between companies that are involved in semiconductor manufacturing. Collaborations that have proven very successful in the previous decade and that have resulted in a number of key innovations.

Supplier Hub off to a promising start

Today, both in logic and in memory, we are developing solutions to enable 7nm and 5nm technology nodes. These will involve new materials, new transistor architectures, and ever shrinking dimensions of structures and layers. At imec, the bulk of scaling efforts like these used to be done in collaborative programs involving IDMs and foundries, but also the fabless and fablite companies. All of these programs were strongly supported by our partnerships with the supplier community.

But today, to work out the various innovations in process steps needed for future nodes, we simply need this stronger and more strategic engagement from the supplier community, involving experimenting on the latest tools, even if they are still under development. And vice-versa, the tool and material suppliers can no longer only develop tools based on specs documents. To fabricate their products successfully and on time, they need to develop and test in a real process flow, and be involved in the development of new device concepts, to be able to fabricate tools and design process steps that match the requirements of the new devices.

A case in point: it is no longer possible now to develop and asses the latest generation of advanced litho without matching materials and etch processes. And reversely, the other tool suppliers need the result of the latest litho developments. So today, all process steps have to be optimized concurrently with other process steps, integrating material innovations at the same time. And this is absolutely necessary for success.

So that’s where the Supplier Hub enters.

In 2013, imec announced an extended collaboration with ASML, involving the set up an advanced patterning center, which will grow to 100 engineers. In 2014, the new center was started as the cornerstone of the supplier hub. Mid 2014, Lam Research agreed to partake in the hub. And since then a growing number of suppliers has been joining, among them the big names in the industry. Some of more recent collaborations that we announced e.g. were Hitachi (CD-SEM metrology equipment) and SCREEN Semiconductor Solutions (cleaning and surface preparation tools).

End of 2014, ASML started installing its latest EUV-tool, the NXE:3300. In the meantime, we have initiated building a new cleanroom next to our existing 300mm infrastructure. The extra floor space will be needed to accommodate all the additional equipment that will come in in the frame of the tighter collaboration among suppliers. Finally, during our October 2014 Internal Partner Conference, we organized a first Supplier Collaboration Forum where the suppliers discussed and evaluated their projects with all partners, representing a large share of the semiconductor community.

We have also been expanding the supplier hub concept through a deeper involvement of material suppliers. These will prove a cornerstone of the hub, as many advances we need for scaling to the next nodes will be based on material innovations.

Enabling the Internet-Of-Everything

I hold great optimism for the industry. The last years, the success of mobile devices has fueled the demand for semiconductor-based products. These mobile applications will continue to stimulate data consumption, going from 4G to 5G as consumers clamor for greater data availability, immediacy, and access. Beyond the traditional computing and communications applications loom new markets, collectively called the ‘Internet of Everything.’

In addition, nanoelectronics will enable disruptive innovations in healthcare to monitor, measure, analyze, predict and prevent illnesses. Wearable devices have already proven themselves in encouraging healthier lifestyles. The industry’s challenge is now to ensure that the data delivered via personal devices meet medical quality standards. In that frame, our R&D efforts will continue to focus on ultra-low-power multi-sensor platforms.

While there are many facets to the inflection point puzzle, the answers of the industry begin to take shape. The cost of finding new solutions will keep on rising. Individual companies carry ever larger risks if their choices prove wrong. But through closer collabo- ration, companies can share that risk while developing solutions, exploring and creating new technologies, shorten times to market, and be ready to bring a new generation of products to a waiting world. The industry may indeed stand at an inflection point, but the future is bright. Innovation cannot be stifled. And collaboration remains the consensus of an industry focused on the next new thing. Today, IC does not just stand for Integrated Circuit, it indeed calls for Innovation and Collaboration.

Micron Technology, Inc. and Intel Corporation today revealed the availability of their 3D NAND technology, the world’s highest-density flash memory. Flash is the storage technology used inside the lightest laptops, fastest data centers, and nearly every cellphone, tablet and mobile device.

3D_NAND_Die_with_M2_SSD

This new 3D NAND technology, which was jointly developed by Intel and Micron, stacks layers of data storage cells vertically with extraordinary precision to create storage devices with three times higher capacity than competing NAND technologies. This enables more storage in a smaller space, bringing significant cost savings, low power usage and high performance to a range of mobile consumer devices as well as the most demanding enterprise deployments.

Planar NAND flash memory is nearing its practical scaling limits, posing significant challenges for the memory industry. 3D NAND technology is poised to make a dramatic impact by keeping flash storage solutions aligned with Moore’s Law, the trajectory for continued performance gains and cost savings, driving more widespread use of flash storage.

“Micron and Intel’s collaboration has created an industry-leading solid-state storage technology that offers high density, performance and efficiency and is unmatched by any flash today,” said Brian Shirley, vice president of Memory Technology and Solutions at Micron Technology. “This 3D NAND technology has the potential to create fundamental market shifts. The depth of the impact that flash has had to date—from smartphones to flash-optimized supercomputing—is really just scratching the surface of what’s possible.”

“Intel’s development efforts with Micron reflect our continued commitment to offer leading and innovative non-volatile memory technologies to the marketplace,” said Rob Crooke, senior vice president and general manager, Non-Volatile Memory Solutions Group, Intel Corporation. “The significant improvements in density and cost enabled by our new 3D NAND technology innovation will accelerate solid-state storage in computing platforms.”

Innovative Process Architecture

One of the most significant aspects of this technology is in the foundational memory cell itself. Intel and Micron chose to use a floating gate cell, a universally utilized design refined through years of high-volume planar flash manufacturing. This is the first use of a floating gate cell in 3D NAND, which was a key design choice to enable greater performance and increase quality and reliability.

The new 3D NAND technology stacks flash cells vertically in 32 layers to achieve 256Gb multilevel cell (MLC) and 384Gb triple-level cell (TLC) die that fit within a standard package. These capacities can enable gum stick-sized SSDs with more than 3.5TB of storage and standard 2.5-inch SSDs with greater than 10TB. Because capacity is achieved by stacking cells vertically, the individual cell dimensions can be considerably larger. This is expected to increase both performance and endurance and make even the TLC designs well-suited for data center storage.

Following two lethargic years of low growth and some setbacks, worldwide sales of optoelectronics, sensors, actuators, and discrete semiconductors regained strength in 2014 and collectively increased 9 percent to reach an all-time high of $63.8 billion after rising just 1 percent in 2012 and 2013, according to IC Insights’ new 2015 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.  Modest gains in the global economy, steady increases in electronic systems production, and higher unit demand in 2014 drove a strong recovery in discretes along with substantial improvements in sensors/actuators and greater growth in optoelectronics, says the new 360-page annual report, which becomes available in March 2015.

Each of the three O-S-D market segments are forecast to increase at or above their long-term annual growth rates in 2015 and 2016 (Figure 1) as the global economy continues to gradually improve and major new end-use systems applications boost sales in some of the largest product categories of optoelectronics, sensors/actuators, and discretes.  After a modest slowdown in 2017, due to the next anticipated economic downturn, all three O-S-D market segments are expected to continue reaching record-high sales in 2018 and 2019, based on the five-year forecast in the new 10th edition of IC Insights’ O-S-D Report.

Optoelectronics sales are now forecast to rise 10 percent in 2015 to set a new record-high $34.8 billion after growing 8 percent in 2014 to reach the current annual peak of $31.6 billion.  Sales of sensors/actuators are also expected to strengthen slightly in 2015, rising 7 percent to $9.9 billion, which will break the current record high of $9.2 billion set in 2014 when this market segment grew 6 percent.  The commodity-filled discretes market is forecast to see a more normal 5 percent increase in 2015 and reach a new record high of $24.2 billion after roaring back in 2014 with a strong 11 percent increase following declines of 7 percent in 2012 and 5 percent in 2013.  The two-year drop was the first back-to-back decline for discretes sales in more than 30 years and primarily resulted from delays in purchases of power transistors and other devices as cautious systems manufacturers kept their inventories low in the midst of uncertainty about the weak global economy and end-user demand.

OSD fig 1

 

In 2014, combined sales of O-S-D accounted for 18 percent of the semiconductor industry’s $354.9 billion in total revenues compared to 16 percent in 2004 and 13 percent in 1994.  (Optoelectronics was 9 percent of the 2014 sales total with sensors/actuators being 3 percent, discretes at 6 percent and ICs accounting for 82 percent, or $290.8 billion, last year).  On the strength of optoelectronics and sensor products—including CMOS image sensors, high-brightness light-emitting diodes (LEDs), and devices built with microelectromechanical systems (MEMS) technology—total O-S-D sales have outpaced the compound annual growth rate (CAGR) of ICs since the late 1990s.  IC Insights’ new report shows this trend continuing between 2014 and 2019 with combined O-S-D sales projected to grow by a CAGR of 6.9 percent versus 5.5 percent for ICs.

The 2015 O-S-D Report shows strong optoelectronics growth being driven in the next five years by new embedded cameras and image-recognition systems made with CMOS imaging devices as well as the spread of LED-based solid-state lights and high-speed fiber optic networks built with laser transmitters that are needed to keep up with tremendous increases in Internet traffic, video transmissions, and cloud-computing services, including those connected to the huge potential of the Internet of Things (IoT). The sensors/actuators market is forecast to see steady growth from high unit demand driven by the spread of automated embedded-control functions, new sensing networks, wearable systems, and measurement capabilities being connected to IoT in the second half of this decade.  Discretes sales are expected to climb higher primarily due to strong growth in power transistors and other devices used in battery-operated electronics and to make all types of systems more energy efficient—including automobiles, high-density servers in Internet data centers, industrial equipment, and home appliances.