Category Archives: 3D Integration

The recent acquisition of Freescale Semiconductor by NXP Semiconductors would catapult the merged entity into the world’s eighth-largest chipmaker, positioning the newly minted giant for an even more formidable presence in key industrial sectors, according to IHS, a global source of critical information and insight.

Prior to the merger, NXP ranked 15th in revenue and Freescale 18th. With combined revenue last year of approximately $10 billion, the resulting new company would have surpassed Broadcom. Only Intel, Samsung Electronics, Qualcomm, SK Hynix, Micron Technology, Texas Instruments and Toshiba would have been bigger, as shown in the table below.

Global Top 10 Semiconductor Makers’ Revenue Share

2014 Company  Revenue Share
Rank
1 Intel 14.14%
2 Samsung Electronics 10.77%
3 Qualcomm 5.46%
4 SK Hynix 4.56%
5 Micron Technology 4.56%
6 Texas Instruments 3.46%
7 Toshiba 2.90%
8 NXP-Freescale (Merged) 2.83%
9 Broadcom 2.38%
10 STMicroelectronics 2.10%

 

“The merged company’s strength will be especially apparent in automotive-specific analog applications,” said Dale Ford, vice president and chief analyst at IHS. “Automotive products clearly will be the biggest convergence resulting from a merged product portfolio of the Dutch-based NXP and its smaller U.S. rival.”

The amalgamated NXP-Freescale would place the company in second place in the area of microcontroller units (MCUs), which are integrated circuits for embedded and automatically controlled applications, including automotive engine-control systems.  The merged company could also affect the digital signal processing (DSP) market, where Texas Instruments reigns supreme. DSPs are an important component in the audio and video handling of digital signals used in myriad applications, including mobile-phone speech transmission, computer graphics and MP3 compression.

“While both NXP and Freescale boast diverse portfolios with complementary products, the high-performance lines of the two chipmakers have very different target solutions,” said Tom Hackenberg, senior analyst for MCUs and microprocessors at IHS.

Freescale has been a key strategic provider of high-reliability automotive, telecomm infrastructure and industrial solutions, including both application-specific and general-purpose products that go after high-performance applications. NXP’s broad portfolio, by comparison, has strategically targeted precision analog and low-power portable-device applications, most of which are directed at portable wireless, automotive infotainment, consumer components and a complementary base of industrial components, including secure MCUs for smart cards. Even in the auto industry, where the two companies both focus on infotainment, their technologies harmonize: NXP dominates the radio market, while Freescale fills a large demand for low- to midrange center-stack processors and instrument cluster controllers.

“The most significant processor competition will likely occur in low-power connectivity solutions, where both chipmakers offer competitive connectivity MCUs,” said Hackenberg. “In particular, the newly merged company will be well-positioned to make groundbreaking advances in the human-machine interface market.”

Freescale recently began developing its portfolio of vision-related intellectual property with Canadian maker CogniVue, used in advanced driver assistance systems (ADAS). For its part, NXP has solid voice-processing expertise. Both companies overall have strong sensor fusion intellectual property, with each maker tending toward different applications. “The resulting combination could offer strategic symmetry in combined vision-, voice- and motion-controlled systems,” Hackenberg added.

Another important aspect of the merger is that Freescale is a near-exclusive source for power architecture processors and processor intellectual property. Although its market share overall is small compared to x86 and ARM, Freescale plays a significant role in the military aerospace industry, where many high-reliability equipment controls rely on power architecture. “While the acquisition of Freescale by a foreign owner is unlikely to be a deal breaker, the development could have some bearing on the approval process in the military, as it will now involve a non-U.S. company possessing ownership of its primary source of military aerospace specific Power Architecture,” Hackenberg noted.

Ziptronix Inc., a developer and provider of patented, low-temperature direct bonding technology for 3D integration, today announced a patent licensing agreement with Sony Corporation for application in advanced image sensors. The agreement marks the continued adoption of Ziptronix’s hybrid bonding patents for high volume applications.

“This license agreement with Sony is an exciting milestone for Ziptronix because it removes any doubt that our patented DBI hybrid bonding technology is both manufacturable and beneficial for high volume applications,” noted Dan Donabedian, CEO and president of Ziptronix. “We believe it demonstrates that our patented hybrid bonding technology is both enabling and cost effective as compared to stacking with TSVs. Sony licensed Ziptronix’s ZiBond direct bonding patents in 2011, which we also believe grew their image sensor market share from a few percent to the largest market share in the industry. We expect this new license for Ziptronix’s DBI hybrid bonding patents will further contribute to Sony’s growth within the industry. Any company wishing to compete in this space will need Ziptronix’s DBI hybrid bonding patents.”

Ziptronix offers patented technology for wafer- or die-level bonding. The company’s intellectual property has been licensed for a variety of semiconductor applications including BSI sensors, RF front ends, pico-projectors, memories and 3D integrated circuits.  Founded in 2000 as a venture-backed spinoff of RTI International, the company has been issued 45 U.S. patents and 42 international patents, with 18 U.S. and international patent applications pending.

XMC, a 300mm semiconductor manufacturing company, today announces it has shipped over 100 million Backside Illumination (BSI) CMOS Image Sensor (CIS) units. All of the BSI CIS units are high end products ranging from 5 to 23 mega pixels by using wafer bonding technology. In addition, the state of the art 3D wafer stacking technology developed by XMC for BSI CIS has also entered volume production now. It indicates that XMC has become one of the leading BSI CIS and 3D IC manufacturing companies in the world.

XMC is dedicated to developing advanced specialty IC manufacturing technologies and providing its customers with high performance and cost effective total solutions. The R&D of wafer-level BSI technology started in the second half of 2012. It took over one year’s joint effort with our partner to reach mass production at the beginning of 2014. A year later, the more advanced 3D wafer stacking, based on the BSI technology, has also been successfully developed. It is a wafer stacking technology that not only bonds two functional wafers (of different process technologies), but also establishes the electrical connection between the two different chips in the bonded wafers. The technology fully realizes vertical wafer integration and improves both chip reliability and efficiency.

“With the offering of the advanced wafer stacking technology, XMC enables its partners to enlarge the share of high-end CIS market,”Dr. Shaoning Mei, CTO at XMC said, “We will further enhance our 3D IC expertise on the basis of 3D wafer stacking technology, by which we can achieve high performance and low power through directly connecting the core parts of two chips. 3D IC is expected to be an important technology to keep us on track with Moore’s Law. It is also the key strength for XMC to establish its leadership in 3D IC industry.”

IC Insights’ March Update to the 2015 McClean Report (being released later this month) refreshes the forecasts for 33 major IC product categories through 2019.  The complete list of all 33 major IC product categories ranked by the updated forecast growth rates for 2015 is shown in Figure 1.  Eleven product categories (led by Automotive Special Purpose Logic, DRAM, and Automotive Application-Specific Analog devices) are expected to exceed the 7 percent growth rate forecast for the total IC market this year.  Five of the eleven categories are forecast to see double-digit growth in 2015.  The total number of IC categories forecast to register sales growth in 2015 drops slightly to 27 products from 28 in 2014.

IC Insights forecasts a solid growth year for automotive-specific ICs.  In addition to Automotive Special Purpose Logic and Automotive Application-Specific Analog, “intelligent” cars are contributing to growth in the 32-bit MCU market. Driver information systems, throttle control, and semi-autonomous driving features such as self-parking, advanced cruise control, and collision-avoidance are some of the systems that rely on 32-bit MCUs.  In the next few years, complex 32-bit MCUs are expected to account for over 25 percent of the processing power in vehicles.

Automotive is forecast to be among the strongest electronic systems market in 2015.  The automotive segment is expected to register a compound annual growth rate of 6.5 percent in the 2014-2019 timeperiod compared to projected CAGRs of 6.8 percent for communications, 4.3 percent for consumer, 4.2 percent for computer, 4.5 percent for industrial, and 2.7 percent for government/military.  Despite automotive being one of the fastest growing electronic system markets over the next five years, automotive’s share of the total IC market is forecast to be only 8 percent in 2015 and remain less than 10 percent through 2019.

Big gains in the DRAM average selling price (ASP) the past two years resulted in greater-than-30 percent growth for the DRAM market in both 2013 and 2014.  DRAM ASP growth is expected to subside this year but demand for mobile DRAM is forecast to help this memory market category grow another 14 percent, placing it second among the 33 IC product categories shown, according to the newly refreshed forecast.

IC Insights 0312 Fig 1

 

Growth of Cellphone Application MPUs (10 percent) is forecast to remain near the top on the growth list for a fifth consecutive year. Meanwhile, the previously high-flying Tablet MPU market is forecast to sputter to just 3 percent growth in 2015 as demand for tablets slows and ASPs decline. Other IC categories that support mobile systems are expected to see better-than-industry-average growth in 2015, including gains of 9 percent for NAND flash and 8 percent for Power Management Analog.

Increased sales of medical/personal health electronic systems and the growth of the Internet of Things will help the markets for Industrial/Other Application-Specific Analog and 32-bit MCU devices outpace total IC market growth in 2015, as well.

IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW).

The new and disruptive 3D configurations and assemblies created by this IRT Nanoelec/CMP initiative are designed to promote 3D integration.

This service, the first of its kind, extends CMP’s regular MPW offer by using mature 3D post-process technologies at wafer level from IRT Nanoelec. These technologies include through-silicon-vias (TSV, via last), fine-pitch vertical interconnects (micro pillar with solder) and specific finishing for 3D integration like under-bump metallurgy (UBM). These 3D modules will enable a wide panel of new, full 3D architectures, like multiple-die stacking with flip-chip, side-by-side heterogeneous integration, and 3D partitioning of different CMOS dies issued from CMP runs.

3D integration is highly complementary to traditional CMOS scaling, and has very strong potential in terms of size reduction, heterogeneous integration, miniaturization, performance improvements and, possibly, reduction of costs at the system level. The technology is now emerging in more and more applications, such as FPGA, 3D memories and MEMS, and involves wafer-level processing on dedicated runs.

The new platform provides for the first time access to post-process 3D technologies after regular CMOS MPW runs, for proof of concept, prototypes and/or small series production. This enables a large group of users to take advantage of cost division made possible, at silicon level, by the MPW regular services followed by post-process technologies. In addition, it allows 3D-MPW users to divide the cost of post processing. This benefits a large group of customers, such as universities, SMEs, research institutes and systems integrators, that usually do not have access to the 3D modules at large foundries.

These 3D post-process technologies require very limited re-design of existing chips, and will be initially used for specific CMOS nodes available at CMP. They may be extended in the future, depending on demand. CMP is responsible for supporting, checking and compiling the customer’s requests, while IRT Nanoelec, which has a very strong background in 3D integration – in particular through the institute CEA-Leti – will manage the 3D post-processing.

“Embedded die in substrate is a promising packaging technology,” comments Yole Développement (Yole) in its latest advanced packaging report entitled “Fan-Out and Embedded Die: Technologies & Market” (Feb. 2015 Edition – Yole Développement). According to Yole’s team, this approach becomes more and more attractive for potential customers because of its numerous advantages. Embedded die in substrate: what are the next steps for the growth?

“The embedding allows a smaller form-factor, and it can be done using a mature manufacturing chain, providing low costs,” explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging and Manufacturing at Yole Développement. “The approach also offers good thermal performance, high integration capability and low inductance thanks to shorter connections”, he adds.
But these advantages still have to be realistic at high volume manufacturing scales before being able to convince customers. Embedding die in laminate substrates is indeed a promising packaging principle, but it has to overcome several challenges.

embedded die

One of these challenges is the supply chain. The process is being pushed by printed circuit board manufacturers such as AT&S and can create a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models, including packagers, module sellers, IDMs pushing for embedding solutions and R&D laboratories.

One of the supply chain’s main advantages is the usage of a mature and affordable manufacturing chain created initially for PCB manufacturing. That achieves low cost technology that would allow easier component integration, with easy access to both sides of the chips. However, a new supply chain brings with it a lack of technical experience with embedding processes and questions about business models that require clarification.

Under the report “Fan-out and Embedded Dies: Technologies & Market Trends,” Jérôme Azemar and the advanced packaging team, analyze the applications that will drive the embedded die market in the future and the potential keys for success.

Single die are the first products currently being sold, demonstrating the technology’s capabilities.

They are essentially low I/O applications with easy to embed dies such as DC/DC converters for wireless products. Yole’s expectations are that the technology will show its real potential with more complex systems such as power application SiPs. There, actives and passives will fully benefit from embedded packages thanks to good heat management and low inductance.

Among the technical requirements, one is especially important: pad pitch on the die. In order to reach volume in the mobile/wireless market, pad pitch has to go below 150μm. Some players, like TDK-EPCOS, claim they already have products with 50μm pitch.

If technical and logistic objectives like this are achieved, and if an application provides a real boost in terms of initial large volumes, the overall market will be able to grow rapidly in the near future.
Under this new advanced packaging technology & market study, Yole, the More than Moore market research and strategy consulting company gives an overview of players involved in embedded die packages. The company describes the strategies they’re hoping will overcome technical issues such as yield, resolution and reliability and their choices of business model to enter the semiconductor packaging market with.

Under this report, Yole’s analysts also detail the different milestones this technology must pass if it is to reach high volumes, and what room there is for innovations where embedded die could provide clear added value. Yole’s study report highlight the different possibilities under investigation or required by customers to achieve volume manufacturing and sustainability. These include details of technical requirements, multi-sourcing and standardization needs and integration roadmaps.

By Shannon Davis, Web Editor

Chipmaker NXP Semiconductors NV announced Sunday night that it has agreed to buy Freescale Semiconductor Ltd for $11.8 billion and merge business operations. The combined enterprise values at just over $40 billion and will create a new leader in the auto and industrial semiconductor markets.

“Financially, this deal makes sense. By being bigger, you limit the impact of the product cycles and volatile end markets,” said RBC analyst Doug Freedman.

NXP and Freescale shares were trading about 16 and 11 percent higher, respectively, on Monday morning, reflecting investors’ confidence in the deal. NXP anticipates achieving cost savings of $200 million in the first full year after closing the transaction, with a clear path to $500 million of annual cost synergies. Freescale shareholders will receive $6.25 in cash and 0.3521 of an NXP ordinary share for each Freescale common share held at the close of the transaction.

This deal is the fourth semiconductor merger and acquisition so far this year, and it will be the biggest of these by far.

Last month, Avago Technologies agreed to would buy wireless networking company Emulex Corp for more than $600 million, while MaxLinear said it would buy Entropic Communications Inc for $287 million. In January, Lattice Semiconductor announced the acquisition of Silicon Image for $600 million.

Freescale was originally created as a division of Motorola in 1948, which would become one of the world’s first semiconductor businesses. Freescale would eventually leave Motorola in 2004, to be acquired in 2006 by Blackstone Group LP, Carlyle Group LP, TPG and Permira. Now based out of Austin, Texas, Freescale currently operates in more than 25 countries, while generating net sales of $4.6 billion in 2014.

NXP is based in Eindhoven, the Netherlands and has operation in more than 25 countries, generating revenue of $5.7 billion in 2014.

“In the short-term, we will continue to benefit with the secular trend of increasing semiconductor content in auto market. The trend has a positive effect on both companies’ portfolio of products. Longer term, the merged company is superbly positioned to become the thought leader in the merging areas of secure cars and Advanced Driver Assistance Systems to facilitate smarter driving,” NXP said on a Monday investor call.

The transaction is expected to close the second half of the 2015 calendar year, after which Freescale shareholders will own approximately 32 percent of the combined company.

Credit Suisse acted as financial adviser to NXP, while Morgan Stanley advised Freescale.

This week, at the 2015 International Solid State Circuits Conference (ISSCC), nanoelectronics research center imec, in collaboration with Tyndall National Institute, the University of Leuven (KULeuven) and the Ghent University, demonstrated a 4x20Gb/s wavelength division multiplexing (WDM) hybrid CMOS silicon photonics transceiver, paving the way to cost-effective, high-density single-mode optical fiber links.

Hybrid CMOS silicon photonics transceivers, transmitting and receiving data over single-mode optical fiber, are expected to play a key role in next-generation datacenter connectivity. By leveraging existing CMOS manufacturing and 3-D assembly infrastructure, the hybrid CMOS silicon photonics platform enables high integration density and reduced power consumption, as well as high yield and low manufacturing cost. Combined with wavelength division multiplexing capability, highly scalable single-mode optical transceivers can be constructed, satisfying the growing need for interconnect bandwidth in next-generation cloud infrastructure.

Imec’s CMOS silicon photonics transceiver comprises a silicon photonics (SiPh) chip, flip-chip integrated with a low-power 40nm CMOS chip. The SiPh chip, fabricated on imec’s 25Gb/s Silicon Photonics Platform (iSiPP25G), comprises an array of four compact 25Gb/s ring modulators, coupled to a common bus waveguide to allow WDM transmission. On the receive side, a ring-based, low-loss (2dB) demultiplexing filter with 300GHz channel spacing is implemented and further connected to an array of four 25Gb/s Ge waveguide photodetectors. Both the ring modulators and the ring WDM filters include highly efficient integrated heating elements to tune their resonant wavelengths to the desired WDM channels. The CMOS chip includes four differential 20Gb/s ring modulator drivers and four 20Gb/s trans-impedance amplifiers. A 12 channel single-mode fiber array is packaged onto the grating coupler array on the chip, using a planar approach developed at Tyndall National Institute.

Error-free operation was demonstrated in a 20Gb/s loop-back experiment for all four WDM channels as well as with two channels running together. The dynamic power consumption of the transceiver, including the CMOS driver and receiver, was less than 2pJ/bit. Thermal tuning of the WDM channel wavelengths consumed only 7mW/nm per channel. The transceiver can be further scaled to higher bandwidth capacity by adopting more advanced CMOS technology and by adding more WDM channels, enabling optical modules for 100GbE, 400GbE and beyond for future datacenter interconnects.

imec transceiver

 

This work was supported by imec’s optical I/O core partner program. Imec’s iSiPP25G technology can be accessed through Europractice, while Si Photonics packaging services are available through Tyndall National Institute (Ireland).

At the SPIE Advanced Lithography conference in San Jose, Calif., Applied Materials, Inc., today announced the industry’s first in-line 3D CD SEM metrology tool for solving the challenges of measuring the high aspect ratio and complex features of 3D NAND and FinFET devices. The new Applied VeritySEM 5i system offers state-of-the-art high-resolution imaging and backscattered electron (BSE) technology that enable exceptional CD control in-line. Using the VeritySEM 5i system can speed up chipmakers’ process development and production ramp, and improve device performance and yield in high-volume production.

“Complex 3D structures require new measurement dimensions, increasing the demands placed on metrology technologies,” said Itai Rosenfeld, corporate vice president and general manager of Applied’s Process Diagnostics and Control group. “Continuing to rely on traditional CD SEM techniques to measure 3D devices is virtually impossible. Offering imaging innovations based on Applied’s expertise in advanced e-beam technology and image processing for fast, accurate on-device CD SEM metrology, allows our customers to see, measure and control their 3D device during R&D, ramp and volume production. Multiple customers using the tool are already benefiting from better yields with these new 3D devices. This system should continue to set the benchmark for the industry as chipmakers require new precision materials engineering capabilities to transition to 3D architectures and scale beyond the 10nm node.”

Innovations in metrology precision are needed to improve device performance, reduce variability and boost yields of increasingly intricate high-performance, high-density 3D devices. An advanced high-resolution SEM column, tilted beam and BSE imaging give the VeritySEM 5i system its unique 3D metrology capability to measure and monitor the most vital and challenging FinFET and 3D NAND structures in-line. Specifically, BSE imaging for via-in-trench bottom CD enables chipmakers to ensure connectivity between underlying and overlaying metal layers. For controlling FinFET sidewall, as well as gate and fin height, where the smallest variation impacts device performance and yield, the VeritySEM 5i tool’s tilt-beam provides exact, repeatable in-line measurements. High-resolution BSE imaging enables continued vertical scaling through enhanced sensitivity for measuring the asymmetrical sidewall and bottom CDs of 3D NAND devices with very high aspect ratios reaching up to 60:1 and beyond.

Applied Materials, Inc. (Nasdaq:AMAT) is the global leader in precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries. Our technologies help make innovations like smartphones, flat screen TVs and solar panels more affordable and accessible to consumers and businesses around the world. Learn more at www.appliedmaterials.com.

Thermal performance of 3DICs


February 20, 2015

By PHIL GARROU, Contributing Editor

3DICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. There are four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs.

Heat dissipation in small hotspots is primarily diffused through the high thermal conductive silicon substrate and spreads in a semi-spherical direction, rapidly decreasing the heat density and lowering the peak temperature. In case of thinned silicon dies in a 3D stack, the inter-die interface layer acts as a thermal barrier due to its poor thermal properties, forcing the heat to spread laterally in the silicon substrate and thus resulting in a temperature distribution which approximates a cylindrical shape.

Thinned silicon dies present reduced lateral heat spreading capacity while poorly conductive adhesive materials used to bond dies together contribute to increase the vertical thermal resistance.
An increase in power density may come from higher power dissipation and/or from a reduction of the
chip footprint. It means either more power needs to be removed from the same package or that the same power dissipation has to go through a reduced chip footprint. While chip footprint reduction is one of the advantages of 3D integration, it usually leads to higher temperatures for the same amount of energy dissi- pation when compared to single-die implementations.

At the 2014 IEEE 3DIC Conference recently in Cork, Ireland, Leti and ST Micro presented two papers on the thermal performance of Packaging 3DICs. Leti shows that inserting TSVs as thermal vias is of limited value. They contend that it is more important to reduce the thermal resistance between the stacked silicon dies which is due to poor thermally conductive layers such as BEOL metallization and underfill.

Thinned dies can present a severe thermal impediment especially to chips with hot spots. Thinned dies present high lateral thermal resistances thus forcing the heat to go through the underfill layer to the next die, which acts as a heat spreader reducing the hotspot temperature. Consequently, the thinner the die the more important is the thermal coupling between dies in case of hotspot heat dissipation.

The use of “thermal TSVs” for thermal mitigation has been routinely reported in the literature. Several thermal-aware physical optimization techniques can be found in the literature which rely on simplistic thermal models where the TSV is treated as a vertical lumped thermal resistor with thermal conductivity calculated according to its diameter and length. Such thermal models ignore the lateral heat transfer and the impact of the thin SiO2 layer, which surrounds each TSV and thermally isolates TSVs from silicon substrate. The poor thermal conductivity properties of the SiO2 dominate the thermal impact of the TSVs in case of hotspot dissipation. Thus while having TSVs in the silicon substrate increases the equivalent vertical thermal conductivity at the same time it causes a lateral thermal blockage effect, especially for fine TSV pitches.

Increasing the TSV density increases the vertical thermal conductivity as well as the lateral thermal blockage effect. Splitting large TSVs into smaller ones increases the ratio of the SiO2 layer thickness to the TSV diameter and hence increases also the lateral thermal blockage effect. Considering TSV technologies with very fine pitch, where this ratio is typically 1:10, also lead to TSV arrays with higher lateral thermal blockage effect.