Category Archives: 3D Integration

ON Semiconductor has successfully characterized and demonstrated its first fully-functional stacked CMOS imaging sensor featuring a smaller die footprint, higher pixel performance and better power consumption compared to traditional monolithic non-stacked designs. The technology has been successfully implemented and characterized on a test chip with 1.1-micron (µm) pixels and will be introduced in a product later this year.

Conventional sensor designs in a monolithic substrate process require separate die area to support both the pixel array and supporting circuitry. With 3D stacking technology, the pixel array and the supporting circuitry are manufactured on separate substrates and then stacked with connections between the two made with through silicon vias (TSVs). This allows the pixel array to overlay the underlying circuitry and result in a more efficient die floorplan. With this approach, design engineers can optimize each part of the sensor for imaging performance, cost, power and die size. With the optimization of the pixel array, sensors can have improved pixel performance with lower noise levels and enhanced pixel response. The underlying circuitry can use more aggressive design rules to lower power consumption as well. The smaller overall footprint supports today’s advanced camera modules that integrate Optical Image Stabilization (OIS) and additional data storage in the same module footprint.

“3D stacking technology is an exciting breakthrough that enhances our ability to optimize ON Semiconductor’s future sensors,” said Sandor Barna, vice president of Technology for ON Semiconductor’s Image Sensor Group. “This technology provides manufacturing and design flexibility to ensure continued performance leadership across our entire sensor product portfolio.”

ON Semiconductor will be demonstrating its latest image sensor technology and products at CES 2015 in Las Vegas from Jan. 6-8.

SEMI Europe will ring in the New Year by holding the first major, international 3D TSV event of 2015. On January 19-21, members of the 3D TSV industry will convene in Grenoble, France for the 3rd edition of the European 3D TSV Summit. This year’s theme: Enabling Smarter Systems.

The European 3D TSV Summit’s 2015 conference will feature Keynote and Invited Speakers, a Market Briefing and a Panel Discussion. The Panel Discussion, moderated by Jean-Christophe Eloy, CEO and founder of Yole Développement, is entitled “From TSV Technology to Final Products – What Business for 3D Smart Systems ?” Panelists from AMKOR, Qualcomm, ams AG and AMD, will share their viewpoints on the 3D TSV market and the shift that many companies are beginning to make from 3D TSV technology development to the commercialization phase. Attendees can expect a lively discussion about the next big steps for the 3D-IC market.

The conference will be accompanied by a sold-out industry exhibition, featuring over 25 important industry players. Conference attendees will be invited to visit the exhibition during coffee and lunch breaks. In addition, the event will offer numerous opportunities for networking including a gala dinner and a one-on-one meeting service with dedicated private meeting spaces. With more than 125 companies planning to be present (including GlobalFoundries, STMicroelectronics, HP, Microsoft, AMD, Qualcomm, IBM, Infineon, AMKOR, ASE, NANIUM, Silex, XFAB, EVGroup, SPTS, and more…) the event promises to be a ripe ground for important professional meetings.

For more information about registration for the European 3D TSV Summit 2015 visit the event’s website:  www.semi.org/European3DTSVSummit. For more information about the remaining sponsorship opportunities, contact Jérôme Boutant: [email protected]

By Dr. Phil Garrou, Contributing Editor

There is an old proverb that states “All things Come to Those Who Wait.” I personally am not the waiting type wanting to get things done ASAP but most civilizations look at patience as a virtue.

We’ve discussed the leading edge before. The leading edge is where the money is made. So while you don’t want to be too early, you certainly don’t want to sit back and wait to see if something is going to happen and let others drain all the profit from that early period of introduction.

Now having said that, let me counter by saying that “All things don’t come to those who wait”. I waited for thin film MCMs to take off in the 90’s and early 2000’s and they never did. A lot of us gambled and, in that case, lost. Life is a gamble!

TSV technology and 2.5/3D has had its own dichotomy. We couldn’t sit back and allow others to
get there first so we all anteed up our time and money without any assurance that there is big money to be made on this technology. Like the cat, we have been waiting (some more patiently than others) for 2.5/3D to enter HVM when in fact there has been no assurance that the mouse wasn’t going to exit from another wall (i.e another technological solution as happened in thin film MCMs).

Anyone who understood what TSV technology could bring to the party, knew that HVM and actually new product design itself could not expand until foundry technology was available (since TSV were/are clearly going in during chip fabrication) and memory stacks were available, since foundries don’t make DRAM. Of course, it all has to be at the right price, but if it’s not even available, what matters the price? In terms of foundries, TSMC was the first to announce and GlobalFoundries is not far behind, so those at the leading edge can now design in 2.5D. But what about memory?

While UMC and a few others have made noise about entering the 3D market space, they appear to be significantly further behind.

The status of memory

The DRAM industry has been undergoing significant consolidation in the last few decades. The recent acquisition of Elpida by Micron has left 3 major players in the DRAM: Samsung with 38%, Hynix with 29% and Micron with 28% (according to Gartner).

Moving forward. the main roadmaps for DRAM suppliers all address: (1) reduce power consumption, (2) satisfy bandwidth requirements and (3) satisfy density requirements, all while maintaining low cost.

With DDR architecture running into a brick wall the memory suppliers have been focusing on new architectures that will deliver lower power, higher bandwith memory solutions. As shown in the Table, these include wide IO-2, HBM (high bandwidth memory) and HMC (hybrid memory cube).
Definition, standardization and scale up of these memory technologies has simply taken longer than any of us would have liked, but these are the new architectures what will take advantage of TSV stacking technology.

As we head into the fall of 2014, the last probably most important of the big three memory suppliers, Samsung has now announced production of TSV based memory stacks. This means we are about to have HBM for graphics modules, wide IO-2 for mobile products and HMC for HPC and high end servers. Now there can be no more excuses.

Within the next 18 months, if we do not see product introductions announced 2.5/3D will begin to fade away until it is only remembered as another one of the bad bets we made attempting to stay on the leading edge.

The most expensive defect


December 18, 2014

Defects that aren’t detected inline cost fabs the most. 

By DAVID W. PRICE and DOUGLAS G. SUTHERLAND, KLA-Tencor, Milpitas, CA

Defect inspection tools can be expensive. But regardless of the cost of the inspection tool needed to find a defect, the fab is almost always better off financially if it can find and fix that defect inline versus at the end of line (e.g., electrical test and failure analysis). Here, we are referring to the term defect in a general sense—the same concepts also apply to metrology measurements.

The third fundamental truth of process control for the semiconductor IC industry is:

The most expensive defect is the one that wasn’t detected inline.

FIGURE 1A (top) shows an imaginary SPC chart for a factory experiencing a baseline shift in defectivity (an excursion) beginning at Lot #300. FIGURE 1B (bottom) shows the same scenario except the fab has an effective inline monitor at the point of the excursion. In this case, the excursion is quickly identified and the offending process tool is taken offline for process tuning or maintenance. The excursion is contained and relatively few lots are impacted by the resulting yield loss.

Defects 1a

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

The difference between these two scenarios is that in the top chart, the fab is unable to detect the excursion inline so the baseline shift continues unabated until the first affected lots hit end of line test. For a foundry process with a 60-day cycle time, this delay could easily exceed 20 days.

In our experience working with IC manufacturers, the majority of financial impact does not come from large excursions that cause significant yield loss to every affected wafer—those problems are usually identified and rectified very early on. Rather, the largest losses usually come from small excursions that are difficult to detect. They cause relatively low levels of yield loss but persist for prolonged periods of time. It is not uncommon to see thousands or even tens of thousands of wafers exposed to these low level excursions.

The culprit is nearly always a process control capability issue that can be traced back to one or more possible problems. The following list is not meant to be exhaustive, but is instead, representative of the most common causes:

Defects 2

FIGURE 2. Cost vs. mean time to detection (MTTD) of finding a defect inline. The curves are drawn for 4 different wafer costs in a fab with 100k WSPM. It is assumed that the excursion takes place at a single step in the process and happens once per year to each of the process tools at that step. The yield loss is assumed to be 20% during the excursion.

  • Insufficient number of inspection points to allow effective isolation of the defect source.
  • Failing to use a sensitive enough inspection tool or recipe (pixel size is too large, wrong wavelength,
  • etc.)
  • Inspection area of wafer is too low.
  • Review sample size is too small.

Often, the original inspection strategy was carefully designed, but as time passed, changes were made to reduce costs. As new sources of noise are introduced in the SPC chart, the fab becomes less sensitive to small excursions.

FIGURE 2 shows the economic impact to the fab for the two scenarios shown by the SPC chart in FIGURE 1. Imagine an excursion which results in a net 25 percent yield loss (e.g., one out of four wafers must be scrapped). Finding that excursion at end-of-line (+30 days) versus inline (greater than one day) would amount to a staggering $21 million loss per occurrence for an average size run rate of 25k wafer starts per month. Given that this value only repre- sents the cost of re-manufacturing the scrapped wafers it could actually be a conservative estimate. The true cost could easily be double that amount for a fab that is running at the limit of their capacity since it would directly impact revenue.

Even if the situation requires the use of a relatively expensive inspection tool to find, monitor and resolve the problem, it is nearly always in the factory’s best interest to do so. One of the implications of this truth is that if an important defect type can only be detected by a certain inspection tool, then that inspection tool is almost always the most cost-effective solution for that layer. Rather than modifying process control strategies to save costs, it is nearly always in the factory’s best interest to maintain capable, inline process control strategies that prevent the financial impact of ‘the most expensive defect.’

Author’s Note: This is the third in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications.

Read more Process Watch:

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

“The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

 

Cross section sample preparation is demonstrated using a workflow that combines High Accuracy Cleaving I(HAC) and Broad Ion Beam (BIB) milling.

By TESHIMA, LatticeGear, Beaverton, OR and JAMIL J. CLARKE, Hitachi High Technologies America, Inc., Clarksburg, MD 

In order to develop and manufacture new materials and processes, the cross section is essential (FIGURE 1). Cross sections allow one to visualize, measure, and characterize the chemistry of the film stack or device structures. This allows engineers to verify the integrity of devices and to make critical decisions about the process. To be able to provide this data, manufacturers and equipment suppliers invest close to a billion dollars annually [1] to purchase equipment for off-line use and out- of-fab support labs.

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

Because such labs are not considered a “make wafer” function, lab managers are under constant pressure to reduce costs, both per sample and for lab operations. This paper demonstrates cross section sample preparation using a workflow that combines High Accuracy Cleaving (HAC) and Broad Ion Beam (BIB) milling. Coupling these techniques, which are relatively low in cost when compared to Focused Ion Beam (FIB) or automated polishing or cleaving [2], reduces sample preparation time, complexity, and cost without sacrificing cross-section quality. The LatticeAxTM HAC and the Hitachi IM4000 BIB milling tools were used to demonstrate this process and are also described.

Preparing cross sections for SEM analysis

Characterization of semiconductor structures and material properties commonly begins with sample preparation. Semiconductor samples are inspected either as a cross section or “top down.” Cross-section samples are needed to inspect layers of subsurface features. As shown in FIGURE 2, if a cross-section view is required and the original sample is a wafer or a die, cleaving is typically the first step in the sample preparation procedure.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

In many cases, the sample can proceed directly to the Scanning Electron Microscope (SEM) as shown in the Single-Tool workflow. For fully processed devices and those with large metal structures, improving surface quality with another method enhances the results (see Multi-Tool workflow).

Advanced techniques used in the multi-tool workflow, such as FIB and automated polishing, have benefits in terms of submicron—or in the case of FIB, nanometer—targeting accuracy, but the tradeoff is high cost, long cycle time, and the need for skilled operators.

Methods

The following sections describe the techniques used to perform multi-tool, cross-section sample prepa- ration workflow using HAC and BIB milling.

High Accuracy Cleaving An accurate and high quality cleave is critical to preparing a cross section for SEM imaging regardless of whether it follows the single- or multi-tool workflow. Manual cleaving, in which you scribe a line and then break the sample along the fracture over a raised edge or pin, has inherent problems with accuracy and repeatability. In addition, because the user handles the sample with fingers that are often gloved, great skill is required to achieve good results. FIGURE 3a shows traditional scribing hand tools used in manual cleaving. Cleaving results using these tools are obviously dependent on the hand-eye coordination of the operator.

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

Figure 3b

Figure 3b

The LatticeAx process overcomes these disadvantages by controlling the indent location and depth, as well as the cleaving operation, with fine-positioning knobs on the LatticeAx high magnification digital microscope. This new machine-assisted Indent and Cleave[3] approach bridges both manual scribing and fully automated cleaving or polishing, and increases success rates while keeping costs down.

The accurate, repeatable indent and slow, controlled cleaving that results from this hybrid tool (FIGURE 3b) speeds preparation time and produces high accuracy, quality results—regardless of user experience—and with greater flexibility of sample size and dimensions.

Broad Ion Beam Milling The BIB milling system is a specimen preparation device (FIGURE 3c) for SEM and surface analysis (EDX[4], EBSP[5], etc.). The device uses a defocused beam of argon ions that sputter material from the target specimen at a rate up to 2-500μm/hour, depending on the mode used. The BIB milling system uses a simple, repeatable process to remove surface layers of a specimen and for final finish of specimens in cross section. It is advantageous compared to mechanical polishing methods, which require well-trained operators to polish the specimen to a flat and mirror-like surface and hit a specific target. In addition, complex material composites that contain materials varying in hardness pose challenges when mechanically prepared using polishing wheels and compounds. This mechanical approach can lead to cracks, stress, relief (pull-out effects), and smearing. These adverse effects are minimized when using the low voltage (0-6kV) argon beam to remove material.

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

Flat Milling Mode Using the BIB’s “Flat Milling” mode yields a high quality cross section in a short amount of time. It requires the initial high accuracy cleave to be through or within a few 100nms of the area of interest and the face of the cross section to be at 90 degrees to the sample surface. With a high quality cleave, the BIB’s Flat Milling mode quickly polishes the cross-section face. Material is removed at a rate of 2μm/hr. Using the flat milling holder, the milling process can uniformly sputter an area approximately ~5mm across around the center of rotation of the specimen (FIGURE 3d). Typical operating parameters for the Hitachi IM4000Plus are 3kV accelerating voltage and a tilt of 70 degrees, with sample stage oscillation set to ±90 degrees and 10rpm. The best quality surface is achieved with a minimum mill time, thus the importance of cleaving through, or very close to, the region of interest. Otherwise, variations in the milling rates of different materials produce artifacts, often called “curtaining.”

Figure 3d

Figure 3d

Cross-section Mode When more than a few microns of material need to be removed, the BIB system is operated in “Cross-section” mode. This is commonly used when exposing a sub-surface target structure. Mechanical grinding causes mechanical artifacts and deformation from stress, making it difficult to obtain a smooth surface for SEM analysis. When using the cross-section milling holder, the BIB IM4000Plus shields part of the argon ion beam with the mask arranged on the specimen, and produces a cross section along the trailing edge of the mask into the sample. For Cross-section mode, targeting accuracy is approximately +/- 15μm.

Backside Milling Backside (as opposed to topside) milling mode can be used in both flat milling and cross-section modes. Backside milling is effective and necessary to alleviate curtaining effects[6] that can occur when traditional top-down ion milling induces striations. These striations are caused by the milling differential from neigh- boring materials that are atomically denser than the surrounding area. FIGURE 4 shows the direction of the ion beam during backside milling and the trench milled by the ion beam.

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

Case Study 1. Quick 5-minute HAC and Flat Milling for Cross Section Final Polish

In this example, a cross section was prepared of an Intel microprocessor removed from its package. The size of the sample available after deprocessing was 8 x 8mm. To prepare the cross section, the sample was cleaved parallel to 15μm contacts visible on the sample surface. The Hitachi IM4000 was then used to prepare the final surface using flat milling mode. Approximately 100nm of material was removed in 10 minutes to achieve the polished surface of the final cross section.

The cross-section process included:

1. Indenting the 15μm area of interest (AOI) with the LatticeAx (FIGURE 5a) (3 min)
2. Cleaving through the AOI using the small sample cleaving accessory[7] (2 min) (FIG 5b-c)
3. Mounting the sample for the IM4000Plus and backside milling using flat milling mode (15 min)

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5b. View of sample after cleaving with the small sample cleaver

FIGURE 5b. View of sample after cleaving with the small sample cleaver

 

FIGURE 5c. Optical view of the cross section after cleaving

FIGURE 5c. Optical view of the cross section after cleaving

Results

This demonstrates a rapid (15-minute) method to obtain a damage-free cross section from a fully processed microprocessor over a very large area (5mm in diameter). A comparison of the results before and after milling shows the clear improvement in surface quality and SEM imaging results (FIGURE 5d and e). Using other methods such as mechanical polishing or FIB can take several hours to achieve a comparable size produced by the large flat-milled region. The best results were obtained when removing a minimum of material (nms), demonstrating the importance of an accurate, high quality cleave prior to BIB milling. FIGURE 5f shows a high-magnification view of the resulting cross section after flat milling that is high quality and without curtaining.

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

 

FIGURE 5f. SEM image showing planar cross section after flat milling

FIGURE 5f. SEM image showing planar cross section after flat milling

Case Study 2. Using HAC and BIB Milling in Cross-section Mode to Prepare Cross Sections of Solder Bumps

Cross sections are required to inspect solder bump reliability for interconnect problems during development and production, or for electromigration failure after aging. Creating these cross sections in a targeted location is critical for effective fault isolation and SEM analysis. With the advent of large Through Silicon-Via (TSV) and solder bump structures—often 100μm in depth or width—high throughput methods are necessary to make cross sections efficiently and effectively.[8]

In this case study, the solder bumps were prepared for SEM in a two-step process. In step 1, the LatticeAx cleaver was used to cleanly cross-section close to, and parallel to, a specific row of copper bumps. The copper bumps had a diameter of 85μm and were cleaved 30 μm from the center of a bump. Time to cleave was 5 minutes and yielded the results shown in FIGURE 6a and FIGURE 6b.

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

In step 2, a broad argon ion beam instrument, the Hitachi IM4000, was used to prepare the final imaging surface within the copper bump. The backside milling method was used; no further preparation was performed.

Results

FIGURES 6c and 6d, taken after ion milling, plainly show the improved surface quality and copper grain structures, as well as fine details at the interface between the bump and adjacent structures. By cleaving close to the center of the copper bumps, the milling time on the BIB was reduced to less than 2 hours versus tens of hours for large cross-section areas (multiple bumps).

This two-step sample preparation process described has been implemented in production by a large semiconductor manufacturer. The technique described reduces turn-around time and repeatedly results in artifact-free cross sections of copper solder bumps.

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

Conclusion

For “off-line” laboratories, using HAC and BIB together for creating high quality cross sections is a compelling, low-cost alternative to investments in FIBs or automated polishing or cleaving equipment. High accuracy cleaving reduces sample preparation time, complexity, and cost without sacrificing cross- section quality. Combining this with a broad argon ion beam instrument for quick removal of minimal amounts of material or for milling of large flat areas, HAC presents effective, accurate results critical to product or failure analysis, while keeping both equipment and per-sample costs low.

Whether for final polish or in sample preparation of solder bumps, the results from the machine-assisted high accuracy Indent and Cleave approach combined with broad ion beam milling rival those of fully automated cleaving or polishing systems

References

1. Per industry sources
2. Approximate costs: FIB/SEM at $1-2 million; Automated HAC at $300,000; HAC+BIB milling tool at $160,000.
3. Cleaving Breakthrough: A New Method Removes Old Limitations, E. Moyal, E. Brandstädt, EDFAAO (2014) 3:26-31
4. Energy-dispersive X-ray spectroscopy
5. Electron backscatter pattern
6. CAVolkert and AM Minor, MRS Bull 32(5) (2007) 389–99.
7. The small sample cleaving accessory is used to clamp samples as small as 4mm wide for indenting with the LatticeAx and cleaving using a separate cleaving base. 8. Sample Preparation of Semiconductor Materials with a New Site-specific Cleaving Technology, Microscopy Today, September 2013, Teshima et al., 56-59.

J. TESHIMA is with LatticeGear, LLC., 1500 NW Bethany Blvd., Suite 200, Beaverton, OR 97006, USA. JAMIL J. CLARKE is with Hitachi High Technologies America, Inc., Nanotechnology Systems Division, 22610 Gateway Center, Dr. Clarksburg, MD 20871, USA

LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices. 

By YUN WANG, Ph.D., Ultratech, San Jose, CA

Sub-20nm system-on-chip and FinFET devices have specific manufacturing challenges that can be resolved with laser spike annealing (LSA) technology. Over the last decade, new process technologies and materials have emerged, such as strained silicon, high-k/metal gate (HKMG) and advanced silicide. Meanwhile transistor structures have evolved significantly, from bulk planar and PDSOI to 3D FinFET. With dimensions approaching atomic scales, the need for low thermal budget processes offered by millisecond annealing (MSA) becomes more important to precisely control the impurity profiles and engineer interfaces. This article will explain how LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices.

LSA and MSA

The European semiconductor equipment market is expected to grow along with the world market. Global capital spending on semiconductor equipment is projected to grow 21.1 percent in 2014 and 21.0 percent in 2015. According to the August edition of the SEMI World Fab Forecast, semiconductor equipment spending will increase from $29 billion in 2013 to $42 billion in 2015.

In this article the terms LSA and MSA are used interchangeably. MSA can be implemented either by a scanning laser or a bank of flash lamps (FIGURE 1). In both cases, a reduced volume of substrate is heated to high temperature by a powerful light source, which results in fast temperature ramping compared to conventional RTP. Surface cooling in the millisecond time scale is dominated by conductive heat dissipation through the lower temperature substrate, which is several orders of magnitude faster than radiation heat loss or convection cooling through surfaces. The wafer backside is typically heated by a hot chuck or lamps to reduce the front surface peak temperature jump, and in some cases, to reduce the flash lamp power requirement or facilitate laser light absorption. Flash usually requires higher backside heating temperature than the laser option.

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

There are important differences between flash and laser approaches. The flash system provides global heating where the top surface of the entire wafer is heated at the same time. Hence heat dissipation occurs only in one dimension (1D – vertical direction). In addition, the backside needs to be floated to relieve the stress caused by global wafer bending due to the vertical thermal gradient. The laser system, on the other hand, provides localized heating around the scanning beam. The heat dissipation is between two-dimensional (2D) and three-dimensional (3D) (2D for an infinitely long line beam, and 3D for a point source). Since the thermal stress is localized, the backside can be chucked to facilitate heat sinking.

The difference in heat dissipation has a significant impact on the cooling rate, in particular, when long annealing or high intermediate (preheat) temperature is used. FIGURE 2 compares the temperature (T) profiles between laser and flash systems for the same peak surface temperature (Tpk) and dwell time (tdwell— defined as the full-width-half-maximum duration when a fixed point on the wafer sees the laser beam or flash pulse). The latter shows much slower ramp down. This is because once the flash energy is dissipated through the wafer thickness, the cooling is limited by the same radiation loss mechanism as in RTP. For applications relying on non-equilibrium dopant activation, the extra thermal budget due to the slow ramp down could be a concern for deactivation.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

LSA technology uses a long wavelength p-polarized CO2 laser with Brewster angle incidence. Previous studies have shown that such configuration has benefits of reduced pattern density effect compared to short wavelength with near normal incidence. A second beam can be added to form a dual beam system that allows more flexibility to adjust the temperature profiles, and expands the process capability to low T and long dwell time.

FIGURE 3 shows different LSA annealing temperature-time (T-t) regimes that can be used to meet various application needs. Standard LSA used in front-end applications has Tpk ranging from 1050~1350°C and tdwell from 0.2~2ms. Short dwell time is beneficial for reducing wafer warpage and litho misalignment, especially for devices with high strain. Long dwell time (2~40ms) adds more thermal budget for defect curing. It can also be used to improve activation and fine tune the junction depth. The low T regime enables applications that require lower substrate and peak annealing temperatures, such as annealing of advanced silicide or new channel/gate stack materials that have poor thermal stability.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

High-k/metal gate (HKMG)

The impact of MSA on HKMG is thinner equivalent oxide thickness (EOT) due to reduced interfacial layer growth from a lower thermal budget. Lower leakage and better surface morphology are also observed in hafnium-based, high-k films when annealed by a laser.

Incorporating nitrogen into a high-k dielectric film can improve thermal stability, reliability, and EOT scaling. Post nitridation anneal with MSA provides opportunities to stabilize the film with a more precisely controlled nitrogen profile, which is important since excessive nitrogen diffusion can increase interface trap and leakage. Oxygen has a strong impact on the characteristics of HKMG and it is important to control the ambient environment during the gate annealing. Full ambient control capability has been developed for LSA to accommodate this need. FIGURE 4 shows the schematics of our patented micro-chamber approach that allows ambient control to be implemented in a scanning system using non-contact gas bearing. Different process gas can be introduced to accommodate various annealing and material engineering needs.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

Advanced silicide

Conventional NiSi processing involves two RTA steps. The 1st RTA (200~300°C) forms Ni-rich silicide, and the 2nd RTA (400~500°C) after selective etch of un-reacted Ni forms the desired low resistance NiSi phase. By replacing the 2nd RTA with a high temperature MSA (700~900°C), it can reduce leakage as well as improve performance. The improvement in leakage distribution results from the statistical reduction of Ni pipe defects due to the low thermal budget of MSA.

High temperature promotes phase mixing of Si-rich Ni silicide at the silicide/Si interface and lowers Schottky barrier height (SBH). In conventional RTA, this requires T > 750°C; such high T would lead to morphology degradation, excess diffusion, and higher resistivity. With MSA, because of the short duration, agglomeration does not occur until ~900°C.

To maximize the performance gain, anneal at high T close to the agglomeration threshold is desired. In such a case, minimizing within-die pattern effects and implementing within-wafer and wafer to-wafer temperature control becomes very important.

FinFETs

As FinFETs shrink, interface contact resistance, Rc, becomes more critical (FIGURE 5). A promising path to lower Rc is interface engineering by dopant segregation using pre or post silicide implantation.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

 

Thermal annealing is necessary to repair implant damage and activate dopants in pre silicide implantation scheme, and to drive-in dopants in post silicide case. Using MSA instead of RTA results in more precise dopant profile control, higher dopant concentration at the interface and less potential silicide defectivity, due to the lower thermal budget.

Recently, Ti re-emerged as an option for contact metal because of better thermal stability and potential lower SBH. LSA can be applied to form low Rc Ti/Si contact. In advanced FinFET flow where contacts are formed after source/drain activation and gate stack, low thermal budget process is beneficial to minimize dopant deactivation and unintentional gate work function shift.

In-situ doped selective epitaxial growth is increasingly used to form the raised source/drain for FinFET. There is, however, a limitation in the maximum activation level it can achieve. Activation can be improved using MSA in combination with additional implantation. Drastic FinFET performance improvement has been achieved with co-optimization of conformal doping, selective epitaxial growth, implantation and MSA. In addition to front-end and middle-of-line applications, there are also opportunities at the back-end. One example is low-k curing. For FinFET, low-k is important not only as an inter-Cu dielectric, but also as a transistor-level dielectric to minimize the parasitic capacitance arising from 3D topography. The modulus and hardness of the low-k films can be improved without adversely impacting the k value using MSA.

New channel materials

Below the 10nm technology node, new materials with enhanced transportation, such as SiGe/Ge and III-V compounds, may be needed to meet the performance requirements. These materials have low thermal stability and are lattice mis-matched with the Si substrate, as a result physical integrity during thermal annealing is a very big concern. Low thermal budget processing by MSA provides a way to alleviate this issue. For example, studies on SiGe/Si heterostructures have shown that MSA can enable a higher annealing temperature than RTA, without strain relaxation or structural degradation. This results in improved activation. With MSA, junctions with enhanced activation and reduced diffusion can be obtained.

Summary

We have reviewed various applications of millisecond annealing for advanced device fabrication. As new materials emerge and device dimensions approach the atomic scale, precise thermal budget control becomes critical. This opens new opportunities for short time scale annealing. In addition to the traditional dopant activation and impurity profile control, MSA can also be used for interface engineering and material property modifications (structural, electrical, chemical, and mechanical). In general, if a desired process has higher thermal activation energy than an undesired process, application of high temperature, short duration annealing is beneficial.

YUN WANG, Ph.D., is Senior Vice President and Chief Technologist of Laser Processing Ultratech, San Jose, CA.

Synopsys, Inc. today announced the expansion of its collaboration with imec (nanoelectronics research center imec) to nanowire and other devices (FinFETs, Tunnel-FETs) targeting the 5-nanometer (nm) technology node and beyond. The agreement enables Synopsys to deliver accurate, process-calibrated models for its Sentaurus TCAD (technology computer aided design) tools to semiconductor manufacturers for use during 5nm technology node research and development. This latest agreement between imec and Synopsys follows successfully completed collaborations on FinFET and 3D-IC technologies for the 10nm and 7nm technology nodes.

“At imec, we focus on bringing the semiconductor industry leaders together to deliver future technologies,” said An Steegen, senior vice president of process technologies at imec. “We are excited to expand our cooperation with Synopsys, the primary TCAD provider, to explore next-generation device and process technologies for 5 nanometer. This continued tight collaboration with Synopsys will enable us to tackle the physics and engineering of advanced devices and introduce a new device design infrastructure for the industry.”

Working closely together, the joint Synopsys-imec team is investigating, among other topics, a vertical nanowire-nanosheet hybrid SRAM cell to target 5nm technology. Early studies show the benefits of nanowire-nanosheet technology in density and performance compared to conventional FinFETs and lateral nanowires. Synopsys’ Sentaurus TCAD tools that support this collaboration are used by technology development teams at foundries and integrated device manufacturers (IDMs) for device architecture selection, design and process optimization. Using early versions of Synopsys’ TCAD models allows the imec project team to explore a range of topics including fundamental device physics (material science, quantum transport and strain engineering), middle-of-line (MOL) local interconnects and the optimization of parasitics. A significant part of the analysis involves full-3D process and electrical simulations to identify device and interconnect reliability solutions for these highly scaled circuits.

“This is the first time a process-calibrated TCAD simulation flow has been used to comprehensively study the process, device and circuit architectures so early in the technology path-finding process,” said Anda Mocuta, logic device manager at imec.

The Synopsys TCAD tools used in this collaboration include the industry-standard simulators Sentaurus Process, Sentaurus Device, Sentaurus Interconnect and Raphael. 3D process structures are read into Raphael for extracting the resistance and capacitance of MOL structures and are combined with Sentaurus-derived compact models for circuit simulation with Synopsys’ HSPICE tool. This simulation flow enables technologists to evaluate the speed and power consumption of ring oscillators and other test circuits in the early stage of technology development, thereby closely linking technology development and selection with circuit-level targets.

“This expanded collaboration with imec builds on the success of previous collaborations to address key challenges at the 5 nanometer technology node,” said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. “Imec’s advanced technology prototyping and characterization capabilities make it an ideal partner for our development and calibration of advanced Sentaurus TCAD models to address the significant technical and business challenges that our customers face in the development of 5nm node technologies.”

With just over a month left to go, industry experts are looking forward to the third edition of the European 3D TSV Summit (Jan 19-21, 2015 in Grenoble, France), this year focusing on “Enabling Smarter Systems.” For the past two years, the event has been a growing success, becoming internationally recognized as a “must-attend” event for companies involved in the development of 3D TSV technology. With a sold-out exhibition and an all-star lineup of conference speakers, the 2015 European 3D TSV Summit is on its way to being one of the most important events of the year for the 3D-IC industry.

Members of the 3D TSV industry have witnessed the giant leap taken by 2.5 and 3D technologies this year, with several announcements about wide scale commercialization of the technology by notable industry players. Samsung, IBM, Bosch and others have started marketing products that integrate 3D TSV or stacked-die technology, making the production of chips and systems smarter than ever. In response to this news, organizers of the European 3D TSV Summit conference have chosen to provide attendees with the most up-to-date and essential information on the business ramifications of the commercialization of 2.5 and 3D technology. Yole Developpement, who recently published a report on the outlook for the 3D-IC market, will be present at the Summit to go into more detail about their outlook for the future of 3D TSV in the marketplace. In addition to Yole, talks by AlixPartners, TechSearch International and ATREG will round out the market briefing portion of the conference.

On the technology side, speakers will include notable companies participating in the development of 3D TSV, including IBM, HP, Qualcomm, AMD, Microsoft, STMicroelectronics, ams AG, ASE Group, Broadpak, Oerlikon, and others. The program appears to offer a cross between the technological development of the 3D TSV technology and its application in finished products. Never-before-dealt-with themes, such as Glass Interposers and Photonics, will be treated during the conference, adding to the Summit’s relevance for the evolving industry of 3D technology.

For mid- to high-level executives and for top technologists working in the 3D TSV industry, the 2015 European 3D TSV Summit will be worth the detour to Grenoble, France. In addition to the top-notch conference, attendees will have a chance to network while visiting the Summit’s exhibition. Located at the heart of the Summit venue, as in past years, the 2015 exhibition is already sold out and promises to offer attendees a well-rounded view of the industry, with representatives from the entire supply chain exhibiting.

As in previous years, the Summit will also offer networking opportunities: a one-on-one meetings service, a gala dinner, lunch breaks, a welcome cocktail and numerous coffee breaks. This year’s gala dinner will be held in the Chateau de Sassenage (Sassenage Castle), bringing an element of “French charm” to the event.

For more information about the European 3D TSV Summit or to register for the event, visit www.semi.org/European3DTSVSummit or contact Yann Guillou at SEMI Europe: [email protected].

CEA-Leti will present its latest results on CoolCube, the technique for stacking transistors sequentially in the same process flow for 3D-VLSI, at a Dec. 14 workshop in San Francisco, Calif. The workshop precedes IEDM 2014, Dec. 15-17.

“The technology is designed to allow a connection of the stacked active layers on a nanometric scale, with a very high density, due to their alignment by a standard lithographic process,” said Maud Vinet, Leti’s advanced CMOS laboratory manager, who will give the presentation. “This 3D concept should allow a gain of 50 percent in area and 30 percent in speed compared to the same technology generation ​​in classic 2D – gains comparable to those expected in the next generation.”

Under development for eight years, CoolCube aims at cutting in half the thermal budget in manufacturing transistors, while maintaining their performance. This low-temperature fabrication allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.

During the continuation of the project over the next three years, Leti and its industrial partners will target development of a silicon component prototype of CoolCube.

In addition to the CoolCube overview, the workshop for invited guests will include summaries of:

  • Leti’s innovative route with industry
  • Emerging material for future market opportunities
  • Leti’s vision towards 10nm and below
  • Embedded NVM for the future
  • Going further with disruptive designs and architectures
  • Electronic medicine: a new market needing new medical methodologies

Leti also will present 17 papers, including four invited papers, at IEDM 2014.

3D TSV begins


December 10, 2014

3D TSV integration has already been adopted in MEMS and CMOS Image Sensors for consumer applications (Source: 3DIC & 2.5D TSV Interconnect for Advanced Packaging Business Update report). Device makers such as Sony, Toshiba, Omnivision, Samsung, Bosch Sensortec, STMicroelectronics and mCube … have all brought devices to the market that integrate 3D TSV technology.

“TSV’s added- value is important: increased performance and functionality, more compact devices, more efficient utilization of the silicon space,” explained Yole Développement (Yole). Moreover, even if 3D TSV process steps are adding cost at the device manufacturing level, these technologies enable cost- saving in other parts of the supply chain.

tsv

“No more doubts about adoption of 3D TSV platform across a wider range of applications: all key players added 3D TSV into their roadmaps, engineering samples have already started to ship and preparation is on-going for entering volume manufacturing,” said Rozalia Beica, CTO & Business Director, Advanced Packaging and Semiconductor Manufacturing at Yole. This year, the industry witnessed several memory product announcements for high-end applications, with transfer to volume production planned in the near future.

“Driven by the demand to further increase in performance, 2015 will be the year for the implementation of 3D TSV technology in high volume production,” explains Rozalia.

The market research and strategy consulting company, Yole and its advanced packaging team, are closely studying and monitoring the industry’s activities in this field. The latest results can be found in Yole’s new 3DIC & 2.5D Business Update Report published this year.

Yole’s vision on further 3D TSV technology adoption will be presented during the European 3D TSV Summit 2015 in Grenoble. The company is partnering with SEMI to support the European TSV Summit, which will take place in Grenoble, France on January 19 to 21, 2015. The European 3D TSV Summit is organized by SEMI Europe. To meet Yole’s experts, discover the detailed program and register, click European 3D TSV Summit 2015.

Also, at the European 3D TSV Summit, Jean-Christophe Eloy, President & CEO, Yole will moderate the panel discussion, “From TSV Technology to Final Products – What is the Business for 3D Smart Systems?” taking place on Tuesday 20, at 5:20 PM. Jean-Christophe will highlight 3D TSV market trends and technology challenges, especially its integration for 3D smart systems application. He will welcome the following panelists: Ron Huemoeller, Senior VP Advanced Product / Platform Development, AMKOR – Martin Schrems, VP of R&D, ams AG – Bryan Black, Senior Fellow, AMD – Mustafa Badaroglu, Senior Program Manager, Qualcomm.

In parallel, Rozalia Beica will be part of the Market Briefing Symposium, on Monday 19. Her presentation is entitled: “From Development to Manufacturing: An Overview of Industry’s 3D Packaging Activities”.

“We are excited to have a group of highly qualified market experts, such as Yole Développement, joining us this year for the European 3D TSV Summit,” stated Anne-Marie Dutron, Director of SEMI Europe’s Grenoble office. “To highlight the adoption of 3D TSV technology in several market applications and to answer the demand from our members, we have given the business aspects of the 3D TSV industry more importance in this 2015 edition.”

The European 3D TSV Summit final program is now available.