Category Archives: 3D Integration

Interview with SEMI Europe’s Yann Guillou gives attendees a preview of the event

This year’s European 3D TSV Summit is fast approaching. Many actors from the 3D TSV supply chain will convene to Grenoble (France) on Jan 19-21, 2015. This year’s theme is “Enabling Smarter Systems”.

In a recent interview published by 3DIncites, Yann Guillou, the event’s architect, revealed the inspiration behind this year’s theme. “Each year, we try to have our conference theme reflect the current state of 3D technology as expressed by industry leaders,” he explained. “When we look at the most recent evolution of 3D TSV technology, we see that TSVs have become an indispensable part of the smarter systems development, so the theme ‘Enabling Smarter Systems’ seemed to stem quite naturally from this.”

The Summit will boast three keynote speakers who are experts in the field of 3D TSV.  In the interview, Guillou shares his excitement about the keynote choices, who all hail from companies particularly active in the 3D TSV sector. Of keynote speaker Timo Henttonen, Senior manager of packing at Microsoft, Guillou said: “For years, [he] has been a key person at Nokia in the packaging group driving new technology developments and implementing them in large volumes. Now, with Nokia’s mobile phone unit having been absorbed into Microsoft, what Timo will share with attendees should be a highlight of the Summit.” Also participating as keynote speakers will be Bryan Black, Senior Fellow at AMD and Bill Chen, Fellow and Senior Technical Advisor at ASE Group.Of the latter, Guillou says, “Bill rarely delivers talks in Europe, and I’m sure he will have key messages to pass on to attendees in his explanation of how ASE sees TSV contributing to their upcoming business activities.”

Along with keynote speakers, the conference will offer a host of invited speakers to discuss various topics that relate to 3D TSV. According to Yann Guillou, multiple criteria such as internationality and diversity of functions in the supply chain determine which speakers will be invited to present at the European 3D TSV Summit. To continue offering a program that deals with the most pressing challenges being faced by manufacturers, SEMI will include new subjects that have not been treated in previous editions of the Summit.

“For instance,” Mr. Guillou explains, “we wanted to have some presentations on ‘Interposers’, from a product and business perspective as well as from a technology perspective. In this regard, on the interposer technology side, we will take a closer look at the glass approach that is important not to neglect.”

For the first time ever, the Summit will also highlight 3D TSV technology in photonics hosting IBM and HP to present on the subject.

Since its debut, the organizers of the European 3D TSV Summit have insisted on the importance of presenting 3D TSV not only from a technology angle, but also from a business angle. “SEMI is a trade association,” states Guillou, “and one of our main goals is to inform and support our members in detecting business opportunities.” This year, SEMI will take this one step further, offering an entire Market Briefing dedicated to the outlook for the 2.5D and 3D markets, and hosting market analysts from Yole Développement, ATREG, TechSearch International and AlixPartners.

When asked what is unique about the event, Yann Guillou answers, “We are proposing a full ‘experience’ for attendees… The event is a unique combination of keynote and invited talks, industry-relevant panel discussion and a quite specialized exhibition that receives high foot traffic.” With over 330 attendees at each of the past two editions of the European 3D TSV Summit, it appears that the 3D TSV community has embraced the concept.

For more information about the European 3D TSV Summit, you can visit the website: www.semi.org/European3DTSVSummit

With the recent Samsung announcement of mass production of 64 GB DDR4 DIMMs that use TSV technology for enterprise servers and cloud-based applications, all three of the major DRAM memory manufactures, Samsung, Hynix and Micron, have now announced the commercialization of TSV based memory architectures.

The challenges for DRAM are to reduce power consumption, satisfy required bandwidth and satisfy density (miniaturization) requirements all the while maintaining low cost.

Many expect current DDR, both the compute variety (DDR3 / DDR4) and the mobile variety (LPDDR3/LPDDR4) to reach the end of their road soon, as the DDR interface reportedly cannot run at data rates higher than 3.2 Gbps in a traditional computer main memory environment. Thus several new DRAM memory architectures based on 3D layer stacking and TSV have evolved to carry memory technology forward.

The challenges for DRAM are to reduce power consumption, satisfy required bandwidth and satisfy density (miniaturization) requirements all the while maintaining low cost. Applications are evolving with different demands on these basic requirements. For example, graphics in a smartphone may require bandwidth of 15GB/sec while a networking router may require 300GB/sec.

memory_3dicbusiness_1_384x288

Memory is also known to be the biggest user of power in server farms, thus there is a requirement in both portable devices and networking and server applications for low power memory solutions.

Hynix has announced the release of multiple memory solutions over the next 2 years.
Emerging DRAM technologies such as wide IO, HMC and HBM are being optimized for different applications and present different approaches to address bandwidth, power, and area challenges. The common element to HMC, HBM and Wide IO are 3D technologies.

Wide I/O 2: supporting 3D-IC packaging for PC and server applications

Wide I/O increases the bandwidth between memory and its driver IC logic by increasing the IO data bus between the two circuits. Wide I/O typically uses TSVs, interposers and 3D stacking technologies.

The 2014 Wide I/O 2 standard JESD229-2 from JEDEC, is designed for high-end mobile applications that require high bandwidth at the lowest possible power. Wide I/O 2 provides up to 68GBps bandwidth, at lower power consumption (better bandwidth/Watt) with 1.1V supply voltage. From a packaging standpoint, the Wide I/O 2 is optimized to stack on top of a system on chip (SOC) to minimize power consumption and footprint. This standard trades a significantly larger I/O pin count for a lower operating frequency. Stacking reduces interconnect length and capacitance. The overall effect is to reduce I/O power while enabling higher bandwidth.

In the 2.5D-stacked configuration, cooling solutions can be placed on top of the two dies. With the 3D-stacked form of Wide I/O 2, heat dissipation can be an issue since there is no standard way to cool stacked die. The Hybrid Memory Cube is a specialized form of the wide I/O architecture.
The Hybrid Memory Cube (HMC) developed by Micron and IBM is expected to be in mass production in 2014. This architecture consists of 3D stacked DRAM layers on top of a controller logic layer. For example, 4 DRAM die are divided into 16 “cores” and then stacked. The logic base is at the bottom has 16 different logic segments, each controlling the four DRAMs cores that sit directly on top of it . This type of memory architecture supports a very large number of I/O pins between the logic and DRAM cores, which deliver bandwidths as high as 400GB/s. According to the Hybrid Memory Cube Consortium, a single HMC can deliver more than 15x the performance of a DDR3 module and consume 70 per cent less energy per bit than DDR3.

In addition to Micron and IBM, the HMC architecture developer members include Samsung, Hynix, ARM, Open Silicon, Altera, and Xilinx (HMC specs).

High bandwidth memory (HBM)
The 2013 JEDEC HBM memory standard, JESD235 was developed for high end graphics and gaming applications. HBM consisting of stacked DRAM die, built with Wide I/O and TSV, supports 128GB/s to 256GB/s bandwidths. TSMC has recently compared these different memory architectures in terms of bandwidth, power and price.

Architecture choice depends on application
Different applications will have different requirements in terms of bandwidth, power consumption, and footprint.
• Because thermal characteristics are critical in high end smartphones, the industry consensus is that Wide I/O 2 is probably the best choice. Wide I/O 2 meets heat dissipation, power, bandwidth, and density requirements. However, it is more costly than LPDDR4.
• Given its lower silicon cost, LPDDR4 is probably better suited for tablets and low end smart phones, less cost-sensitive mobile markets.
• For high-end computer graphics processing, which are less constrained by cost then mobile devices, HBM memory may be the best choice.
• High performance computing (HPC) or a networking router requiring 300GBps BW is probably best matched to the HMC.
The properties of these standardized memory architectures and the applications they appear best suited for are compared below.
As we move into 2015 several industry segments have announced applications using the new memory stacks.
• Intel recently announced that their Xenon Phi processor “Knights Landing” which will debut in 2015 will use 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth for high performance computing applications.
• AMD and Nvidia have also announced the use of HBM in their next generation graphics modules like the Nvidia Pascal due out in 2016.

Yole Développement has been studying 2.5/3DIC technology and commercial adoption for nearly a decade.

The above described advances and all the rest of the latest 3DIC happenings can be found in Yole Développement’s new report “3DIC & 2.5D TSV Interconnect for Advanced Packaging – 2014 Business Update”. More information on www.i-micronews.com, advanced packaging reports section.

The Hybrid Memory Cube Consortium (HMCC), dedicated to the development and establishment of an industry-standard interface specification for Hybrid Memory Cube (HMC) technology, announced the finalization and public availability of its HMCC 2.0 specification (HMCC 2.0).

The new HMCC 2.0 specification advances data rate speeds from 15 Gb/s up to 30 Gb/s, establishing a new threshold for memory performance. HMCC 2.0 also migrates the associated channel model from short reach (SR) to very short reach (VSR) to align with existing industry nomenclature.

“With 150 members, the Hybrid Memory Cube Consortium has gained considerable momentum since its inception and, as a result, has more and better inputs on how the interface can best fit tomorrow’s applications,” said Jim Handy, director, Objective Analysis. “The release of the HMCC 2.0 specification shows a commitment to evolving a family of specifications targeting all high-performance computing applications.”

The HMCC was founded in October 2011 by co-developers Altera, Micron, Open-Silicon, Samsung Electronics and Xilinx. The HMCC finalized and released its first specification in May 2013, demonstrating consensus among leading semiconductor developers to drive adoption of HMC into next-generation systems. Since its establishment, the HMCC has grown to include more than 150 OEMs, enablers and integrators who regularly participate in the development and discussion of HMC standards. Finalization of the second generation of HMCC specifications is a key milestone in the development of this innovative memory technology and an indication of its continued adoption.

“HMCC 2.0 gives designers a mature solution for breaking through memory bottlenecks and delivering a new generation of systems with unprecedented memory performance,” said Hans Boumeester, Open-Silicon’s vice president of IP and engineering operations. “Ratification of the new standard means that these designers will have access to standards-compliant IP for immediate integration into chips and systems that meet the growing bandwidth demands of next-generation data center and high-performance computing applications.”

This week, SEMI announced the keynote speakers for the third edition of the European 3D TSV Summit, event that will take place on January 19-21, 2015 in Grenoble, France. As an increasing number of companies, such as IBM, Xilinx, Samsung and Bosch, are taking 3D through-silicon-via (TSV) technology to the commercialization phase, the necessity for understanding the business and technological context surrounding these devices has become more important than ever. In this context, SEMI has invited experts on the forefront of the technology to share their perspectives on the industry.

Joining the conference as a keynote speaker, Bryan Black, senior fellow at AMD, will inform participants that die stacking is finally happening in mainstream computing and explain the impacts of this technology on the industry. Timo Henttonen, senior manager packaging at Microsoft, will discuss his vision of the future of 3D TSV for smartphones and connected devices. Finally, Bill Chen, fellow and senior technical advisor at ASE Group, will deliver a talk about the integration of 3D TSV into the DNA of packaging.

In addition to these three keynote speakers, over 20 invited speakers and panel discussion participants will share their views during the 3D TSV conference, including industry experts from Qualcomm, IBM, HP, ams AG, imec, CEA-LETI, Fraunhofer-IKTS, Broadpak, SPTS, Suss Microtec, EV Group, BESI, KLA-Tencor, Rudolph Technologies, Asahi Glass, Corning, Oerlikon, STMicroelectronics, AMKOR and more.

New this year, the Summit will include a Pre-Summit Market Briefing dealing specifically with the 3D TSV market outlook and hosting several talks by financial analysts and industry consultants, including Yole Development, TechSearch International, AlixPartners and ATREG.

Over 30 companies will join the event as exhibitors. In addition to the exhibit and conference, attendees will have the opportunity to set up one-on one business meetings and visit the CEA-Leti 300mm TSV-capable clean room.

For more information, please visit www.semi.org/european3DTSVSummit or contact Yann Guillou, SEMI Europe Grenoble Office ([email protected]).

“The long term growth of the equipment & materials business will be supported by the expansion of 3D TSV stack platforms,” says Yole (Yole Développement) in its latest report, “Equipment & Materials for 3DIC & WLP Applications“. The market research and strategy consulting company, Yole proposes a deep analysis of the equipment & materials market for 3DIC & WLP applications. Under this new report, analysts announce a market multiplied by 2.5 in the next 5 years.

“Mainly supported today by flip-chip wafer bumping, the equipment market generated revenue of more than $930M in 2013,” said Amandine Pizzagalli, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing, Yole. “It is expected that this equipment market revenue will peak at almost $2.5B”, she added.

Equipment & Materials for 3DIC & WLP Applications report presents an overview of the main equipment and materials used in the 3D & WLP applications. Under this technology & market analysis, Yole’s analysts describe insights on a number of equipment tools, breakdown by wafer size & revenue, by type of equipment & materials and advanced packaging applications. Moreover, they also provide a detailed analysis dedicated to key suppliers, market shares and technological highlights that impact the 3D & WLP industry. Equipment & materials market forecasts are calculated from 2013 to 2019.

This market is fueled by the 3D IC technology with TSV interconnects, an area offering opportunities for new developments in equipment modification— equipment that is much more expensive than the tools used for established Advanced Packaging platforms :3D WLP, WLCSP and flip-chip wafer bumping. Indeed, according to Yole, 2015 will be the key turning point for the adoption of 3D TSV Stacks since the memory manufacturers, such as Samsung, SK Hynix, Micron, have already started to ship prototypes this year and might be ready to enter in high-volume manufacturing next year.

In its latest announcement (Source: Song Jung-a, Financial Times), Samsung Electronics reveals its $14.7 billion investment, to build a new semiconductor plant in South Korea. This investment becomes the biggest single expenditure on a memory chip factory.

“The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%”

According to the Korean company, construction of the world’s biggest plant will begin in the first half of next year and complete in the second half of 2017. In addition, logic manufacturers will diversify investments from System-on-Chip to Package-on-Package and will benefit from Advanced Packaging platforms such as 2.5D interposer and FOWLP to stimulate their high-volume production.

From the materials side, Yole confirmed: “The materials market will grow from $789M in 2013 to over $2.1B with a CAGR of 18%.”

Growth will mainly be driven by the expansion of the next generation Wafer-Level-Packaging platforms: 3D TSV stacked memories, multi-layer RDL for FOWLP & WLCSP. Such platforms are becoming more complex and requiring additional and various thin layers, as well as advanced materials, to achieve better performance.

Kandou Bus has announced the Glasswing family of chip interconnects targeted for in-package chip-to-chip links. Kandou introduced Chord Signaling in February 2014 and outlined how signals can be correlated across more than two wires to achieve higher bandwidth and lower power with excellent signal integrity and low latency. The Glasswing architecture optimizes Chord Signaling to address the unique challenges of both substrate and interposer in-package solutions.

For the first time in history, the cost to manufacture a transitor in the most advanced silicon process has increased compared to the previous generation. As a result, system architects are looking for more cost effective ways to partition and package silicon devices for optimal performance. Integrating several chips into a shared package can be attractive, but only if the in-package communication between chips allows for extremely high bandwidth and very low power.

“Architectures that combine multiple chips into a single package are not new,” said Kandou Founder and CEO Amin Shokrollahi, “but increasing bandwidth and improving signal integrity while maintaining very low power in an affordable package is a daunting task. Glasswing delivers on the promise of 2.5D integration by providing a cost-effective solution that offers unprecendented, in-package, chip-to-chip bandwidth at very low power.”

Glasswing Architecture and Applications

The core of Kandou’s Glasswing technology is a chordal code that delivers five bits over six correlated wires within each clock cycle. Through a simple yet elegant comparator network, signals are received and translated into bits resulting in much higher overall link throughput.

Depending on the application the link can run at up to 25 GBaud and deliver up to 20.8 Gbps per wire at less than 0.5pJ/bit in a 28nm logic process. These benefits are ideal for very short links (less than 10mm) such as the connnection inside a package between a DRAM stack and a controller, the link to an out-boarded high speed SerDes, or the coherency buses of a partitioned multi-core processor. The link can also work over channels up to 25mm in length with slightly more power.

To fully realize the benefits of the Glasswing architecture, Kandou has developed optimized circuits and architectures for all parts of the transmission chain including serializers, drivers, receivers, CDR units, skew mitigators, equalizers, deserializers and test circuits.

Kandou’s Glasswing product development is underway for the first instantiation of the PHY optimized for in-package links between processor cores. A comprehensive 28nm PHY evaluation package will be available Q3 2015.

SEMI announced today that the deadline for presenters to submit an abstract for the 26th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 11.  ASMC, which takes place May 3-6, 2015 in Saratoga Springs, New York, will feature technical presentations of more than 80 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, and tutorials.

ASMC, in its 26th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.  Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. Technical abstracts are now due November 11, 2014.

This year SEMI (www.semi.org) is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:

·        3D/TSV/Interposer

·        Advanced Metrology

·        Advanced Equipment Processes and Materials

·        Advanced Patterning / Design for Manufacturability

·        Advanced Process Control (APC)

·        Contamination Free Manufacturing (CFM)

·        Data Management and Data Mining Tools

·        Defect Inspection and Reduction

·        Discrete Power Devices

·        Enabling Technologies and Innovative Devices

·        Equipment Reliability and Productivity Enhancements

·        Fabless Experience

·        Factory Automation

·        Green Factory

·        Industrial Engineering

·        Lean Manufacturing

·        Yield Enhancement

·        Yield Methodologies

Complete descriptions of each topic and author kit can be accessed at www.semi.org/en/node/38316.  If you would like to learn more about the conference and the selection process, please contact Margaret Kindling at [email protected] or call 1.202.393.5552.   

Papers co-authored between device manufacturers, equipment or materials suppliers, and/or academic institutions that demonstrate innovative, practical solutions for advancing semiconductor manufacturing are encouraged.  To submit an abstract, visit http://semi.omnicms.com/semi/asmc2015/collection.cgi

Technical abstracts are due November 10, 2014. Learn more about the Advanced Semiconductor Manufacturing Conference; visit www.semi.org/asmc2015.

Yesterday, KLA-Tencor announced a plan to significantly accelerate its strategy to drive stockholder returns. KLA-Tencor’s Board of Directors authorized the financing of a leveraged recapitalization, which would feature a special cash dividend of $16.50 per share, representing approximately 23 percent of the company’s common stock price as of October 22, 2014, or approximately $2.75 billion.

In its official release, KLA-Tencor said its Board of Directors currently intends to declare and pay the special cash dividend before December 31, 2014. The special cash dividend would be in addition to the Company’s regular $0.50 per share quarterly cash dividend. The company’s regular $0.50 per share quarterly cash dividend is expected to be declared and paid following the company’s regularly scheduled Board of Directors meeting in November 2014.

In connection with the leveraged recapitalization, the Board of Directors has approved an increase to the company’s stock repurchase program for up to 3.6 million additional shares of the company’s common stock, which is valued at approximately $250 million based upon the closing price of the company’s common stock as of October 20, 2014. This is in addition to the $1 billion stock repurchase program previously announced in July 2014.

KLA-Tencor expects to complete these share repurchases within 12 to 18 months. The repurchases may occur from time to time, in the open market, with consideration given to the market price of the common stock, the company’s other investment opportunities, and general economic conditions.

Including the intended special cash dividend of $16.50 per share (or an aggregate value of approximately $2.75 billion), the $250 million increase to the stock repurchase program announced today, and the $1 billion stock repurchase program previously announced in July 2014, the total capital that would be directed to stockholders would be approximately $4 billion in aggregate.

The intended special cash dividend of $2.75 billion in the aggregate will be funded in part with a portion of the cash on the company’s balance sheet, and in part with incremental debt. To fund the debt financed portion of the special cash dividend, KLA-Tencor intends to add up to $2.5 billion of incremental debt, consisting of a combination of investment grade senior notes and a pre-payable term loan facility, subject to market conditions. The company also expects to enter into an unfunded revolving credit facility, subject to market conditions. The declaration and payment of the special cash dividend are conditioned on the company’s ability to obtain requisite debt financing on satisfactory terms and conditions. KLA-Tencor intends to manage its capital structure to preserve and maintain its investment grade rating.

What the analysts are saying

Getting a read on what this means for KLA-Tencor’s future is difficult, but Srini Sundararajan, Semiconductor, Semi-cap Equipment Analyst, Summit Research Partners, provided these thoughts.

“Most likely, an increased capital intensity projection due to FinFET and 3D NAND next year likely left the management to seize the opportunity for a one-time special mega-dividend shareholder return during 2014,” said Sundararajan. “KLAC could potentially be an acquisition target for LRCX or ASML given that they might need to ‘bulk-up’ post the potential consummation of an Applied Materials-Tokyo Electron merger.”

While the leveraged recapitalization plan benefits shareholders and upper management, it will definitely lead to higher interest expenses and during down-turns, Sundararajan said, there could be some pressure put on continued dividends and buybacks while paying down the debt.

“The use of debt to return money to shareholders will definitely leave some wondering whether the company thinks that: a) additional internal R&D is a worthy use of money, and, b) no external M&A targets are out there that are attractive,” Sundararajan concluded.

Samsung today announced that it is mass producing the industry’s most advanced 8-gigabit (Gb) DDR4 memory and 32-gigabyte (GB) module, both of which will be manufactured based on a new 20-nanometer (nm) process technology, for use in enterprise servers.

“Our new 20nm 8Gb DDR4 DRAM more than meets the high performance, high density and energy efficiency needs that are driving the proliferation of next-generation enterprise servers,” said Jeeho Baek, Vice President of Memory Marketing at Samsung Electronics. “By expanding the production of our 20nm DRAM line-ups, we will provide premium, high-density DRAM products, while handling increasing demand from customers in the global premium enterprise market.”

With its new 8Gb DDR4, Samsung now offers a full line-up of 20nm-based DRAM to lead a new era of 20nm DRAM efficiency that also includes the 20nm 4Gb DDR3 for PCs and the 20nm 6Gb LPDDR3 for mobile devices.

Using the new 8Gb DDR4 chip, Samsung began producing the 32GB registered dual in-line memory module (RDIMM) earlier this month. The new module’s data transfer rate per pin reaches up to 2,400 megabits per second (Mbps), which delivers an approximately 29 percent performance increase, compared to the 1,866 Mbps bandwidth of a DDR3 server module.

Beyond the 32GB modules, the new 8Gb chips will allow production of server modules with a maximum capacity of 128GB by applying 3D through silicon via (TSV) technology, which will encourage further expansion of the high-density DRAM market.

The new high density DDR4, also boasts improved error correction features, which will increase memory reliability in the design of enterprise servers. In addition, the new DDR4 chip and module use 1.2 volt, which is currently the lowest possible voltage.

On January 19-21, 2015, SEMI will hold its 3rd edition of the European 3D TSV Summit in Grenoble, France.  After the last successful edition that brought over 330 participants from over 21 countries in January 2014, SEMI will renew the Summit in 2015 with the theme: “Enabling Smarter Systems,” focusing on the critical chip integration that 3D through silicon vias (TSV) now play in business strategies and the latest technology advancements.

After a long period of development, disruptive TSV technology is now transitioning to the commercialization stage and delivering higher performance, lower power consumption and reduced footprint products to enable overall smarter system integration. Companies like SK Hynix, Micron or Samsung are manufacturing engineering samples and some are even ramping up the production of stacked memories with TSV. Bosch, a MEMS company, is proposing 3-axis accelerometers with TSV. Sony is manufacturing 3D stacked backside illuminated Image Sensors with TSV in the logic die. Xilinx, pioneer of TSV with its VIRTEX 7 in 28nm, announced their next generation FPGA products Kintex and Virtex Ultra Scale in 20 and 16nm stacked die on interposer. These examples of recent product launches and announcements from major semiconductor companies make it more relevant than ever to attend this year’s TSV Summit to learn about future opportunities.

The event will be the platform for over 20 invited speakers from design houses, IDMs, OSATs, as well as from equipment and materials suppliers to share their views during plenary presentations and panel discussions. Executives and experts from leading global companies will address the latest business and technological issues pressing the industry ,—including cost of ownership, business models, supply chain, manufacturability and other technological aspects.

The European 3D TSV Summit will address the most relevant and controversial issues related to 2.5 and 3D manufacturing. Companies will also have the opportunity to showcase their products and services in the exhibition zone. In addition to the exhibit and conference, attendees will have the opportunity to schedule on-site business meetings through the event’s online business meeting platform and to visit the CEA-Leti 300mm TSV-capable clean room.

This year’s European 3D TSV Summit Steering Committee includes executives from: ams AG, BESI, CEA-Leti, EV Group, Fraunhofer-IZM, imec,  Oerlikon Systems, Scint-X,  SPTS, STMicroelectronics, and SUSS Microtec.

Please visit www.semi.org/european3DTSVSummit to register as an attendee or to exhibit at the event. Sponsorship packages are also available. Early-bird pricing will be available until 31 October. For additional information, contact Yann Guillou, SEMI Europe Grenoble Office ([email protected]).