Category Archives: 3D Integration

Electrical engineers at the Technische Universität München (TUM) have demonstrated a new kind of building block for digital integrated circuits. Their experiments show that future computer chips could be based on three-dimensional arrangements of nanometer-scale magnets instead of transistors. As the main enabling technology of the semiconductor industry – CMOS fabrication of silicon chips – approaches fundamental limits, the TUM researchers and collaborators at the University of Notre Dame are exploring “magnetic computing” as an alternative. They report their latest results in the journal Nanotechnology.

In a 3D stack of nanomagnets, the researchers have implemented a so-called majority logic gate, which could serve as a programmable switch in a digital circuit. They explain the underlying principle with a simple illustration: Think of the way ordinary bar magnets behave when you bring them near each other, with opposite poles attracting and like poles repelling each other. Now imagine bringing several bar magnets together and holding all but one in a fixed position. Their magnetic fields can be thought of as being coupled into one, and the “north-south” polarity of the magnet that is free to flip will be determined by the orientation of the majority of fixed magnets.

Gates made from field-coupled nanomagnets work in an analogous way, with the reversal of polarity representing a switch between Boolean logic states, the binary digits 1 and 0. In the 3D majority gate reported by the TUM-Notre Dame team, the state of the device is determined by three input magnets, one of which sits 60nm below the other two, and is read out by a single output magnet.

The latest in a line of advances

This work builds on capabilities the collaborators have developed over several years, ranging from sophisticated simulations of magnetic behavior to innovative fabrication and measuring techniques. It also represents not an end point but a milestone in a series of advances.

For example, they reported the world’s first “domain wall gate” at last year’s International Electron Devices Meeting. The scientists use focused ion-beam irradation to change the magnetic properties of sharply defined spots on the device. So-called domain walls generated there are able to flow through magnetic wires under the control of surrounding nanomagnets. This 2D device, TUM doctoral candidate Stephan Breitkreutz explains, “enables signal routing, buffering, and synchronization in magnetic circuits, similar to latches in electrical integrated circuits.”

A fork in the industry roadmap

All players in the semiconductor business benefit from one industry-wide cooperative effort: developing long-range “roadmaps” that chart potential pathways to common technological goals. In the most recent issue of the International Technology Roadmap for Semiconductors, nanomagnetic logic is given serious consideration among a diverse zoo of “emerging research devices.” Magnetic circuits are non-volatile, meaning they don’t need power to remember what state they are in. Extremely low energy consumption is one of their most promising characteristics. They also can operate at room temperature and resist radiation.

The potential to pack more gates onto a chip is especially important. Nanomagnetic logic can allow very dense packing, for several reasons. The most basic building blocks, the individual nanomagnets, are comparable in size to individual transistors. Furthermore, where transistors require contacts and wiring, nanomagnets operate purely with coupling fields. Also, in building CMOS and nanomagnetic devices that have the same function – for example, a so-called full-adder – it can take fewer magnets than transistors to get the job done.

Finally, the potential to break out of the 2D design space with stacks of 3D devices makes nanomagnetic logic competitive. TUM doctoral candidate Irina Eichwald, lead author of the Nanotechnology paper, explains: “The 3D majority gate demonstrates that magnetic computing can be exploited in all three dimensions, in order to realize monolithic, sequentially stacked magnetic circuits promising better scalability and improved packing density.”

“It is a big challenge to compete with silicon CMOS circuits,” adds Dr. Markus Becherer, leader of the TUM research group within the Institute for Technical Electronics. “However, there might be applications where the non-volatile, ultralow-power operation and high integration density offered by 3D nanomagnetic circuits give them an edge.”

This research was supported by the German Research Foundation (DFG).

Tessera Technologies, Inc. today announced it has named Craig Mitchell as chief technology officer for Tessera and president of Invensas Corporation, effective immediately. Mr. Mitchell assumes these roles from Simon McElrea, who is leaving the company for a new opportunity.

Mr. Mitchell, who was most recently the senior vice president of business development, joined the company in 1992 and has held a variety of senior roles in technology development, marketing, and licensing. He was a central figure in the development, licensing and technology transfer of the company’s flagship microBGA packaging technology to leading semiconductor manufacturers. Mr. Mitchell is also the named inventor on more than 60 U.S. patents.

In his new role, Mr. Mitchell will drive the development and commercialization of xFD, BVA, and 2.5D/3D interconnect technologies as well as efforts to expand the Invensas portfolio of interconnect technologies.

“Although I have been with the company for over 20 years, I am more excited than ever. The Company’s approach to technical collaboration and partnerships is consistent with our goal of driving enabling technologies, such as xFD and BVA, into high volume production with our customers. I look forward to working with our highly talented technology team to deliver the next generation of game-changing technologies to our customers,” said Mr. Mitchell.

“We are thrilled to have someone of Craig’s experience and abilities assume this important role within the company. Craig has a deep understanding of technology development combined with a collaborative approach to creating value for our customers. His leadership will be instrumental in achieving our future growth initiatives,” said Tom Lacey, Tessera’s CEO. “I would also like to thank Simon for his many contributions to the Company over the past four years. We wish him the very best in his new endeavors.”

Tessera Technologies, Inc. and its subsidiaries generate revenue from licensing to manufacturers and other implementers that use the Company’s technology in areas such as mobile computing and communications, memory and data storage, and 3-D IC technologies.

TSMC today announced that its has successfully produced the foundry segment’s first fully functional ARM-based networking processor with FinFET technology, through its collaboration with HiSilicon Technologies Co, Ltd.

TSMC’s 16FinFET process promises impressive speed and power improvements as well as leakage reduction. All of these advantages overcome challenges that have become critical barriers to further scaling of advanced SoC technology. It has twice the gate density of TSMC’s 28HPM process, and operates more than 40 percent faster at the same total power, or reduces total power over 60% at the same speed.

“Our FinFET R&D goes back over a decade and we are pleased to see the tremendous efforts resulted in this achievement,” said TSMC President and Co-CEO, Dr. Mark Liu. “We are confident in our abilities to maximize the technology’s capabilities and bring results that match our long track record of foundry leadership in advanced technology nodes.”

TSMC’s 16FinFET has entered risk production with excellent yields after completing all reliability qualifications in November 2013. This paves the way for TSMC and customers to engage in more future product tape-outs, pilot activities and early sampling.

Built on TSMC’s 16FinFET process, HiSilicon’s new processor enables a significant leap in performance and power optimization supporting high-end networking applications. By leveraging TSMC’s heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) 3D IC packaging process, HiSilicon integrates its 16-nanometer logic chips with a 28-nanometer I/O chip for a cost-effective system solution.

“We are delighted to see TSMC’s FinFET technology and CoWoS solution successfully bringing our innovative designs to working silicon,” said HiSilicon President Teresa He.”This industry’s first 32-core ARM Cortex-A57 processor we developed for next-generation wireless communications and routers is based on the ARMv8 architecture with processing speeds of up to 2.6GHz. This networking processor’s performance increases by three fold compared with its previous generation. Such a highly competitive product can support virtualization, SDN and NFV applications for next-generation base stations, routers and other networking equipment, and meet our time-to-market goals.”

Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs). Copper pillar bumps are a critical component of many advanced packaging technologies and TSVs provide a means for signals to pass through multiple vertically stacked chips in three dimensional integrated circuits (3DIC). The new SONUS Technology is non-contact and non-destructive, and is designed to provide faster, less costly measurements and greater sensitivity to smaller defects than existing alternatives such as X-ray tomography and acoustic microscopy.

“SONUS Technology meets a critical need for measuring and inspecting the structures used to connect chips to each other and to the outside world,” said Tim Kryman, Rudolph’s director of metrology product management. “Copper pillar bumps and TSVs are critical interconnect technologies enabling 2.5D and 3D packaging. The mechanical integrity of the interconnect and final device performance are directly dependent on tight control of the plating processes used to create copper pillar bumps. Likewise, the quality of the TSV fill is critical to the electrical performance of stacked devices. This new technology allows us to measure individual films and film stacks with thicknesses up to 100µm, and detect voids as small as 0.5µm in TSVs with aspect ratios of 10:1 or greater.”

Kryman added, “SONUS Technology builds on the expertise we developed in acoustic metrology for our industry-standard MetaPULSE systems, which are widely used for front-end metal film metrology. By offering similar improvements in yield and time-to-profitability in high volume manufacturing (HVM), SONUS offers a compelling value proposition to advanced packaging customers.”

Both MetaPULSE and SONUS systems use a laser to initiate an acoustic disturbance at the surface of the sample. As the acoustic wave travels down through the film stack, it is partially reflected at interfaces between different materials. Although the detection schemes are different, the reflected waves are detected when they return to the surface and the elapsed time is used to calculate the thickness of each layer. In the case of SONUS Technology, two lasers are used. The first laser excites the sample and the second probes for the returning acoustics. This decouples excitation and detection allowing SONUS to continuously probe the sample resulting in a much larger film thickness range. So, where MetaPULSE can measure metal films and stacks to ~10 microns, SONUS can measure films in excess of 100 microns. In addition, SONUS Technology’s use of interferometry to characterize the surface displacement provides a rich data set that can be analyzed to not only characterize film thickness, but perform defect detection.

The primary alternatives for such measurements are X-ray based tomographic analysis and acoustic microscopy. SONUS Technology’s ability to detect voids as small as half a micrometer is approximately twice as good as current X-ray techniques, which have a spatial resolution of about 1 micrometer. Acoustic microscopy can make similar measurements, but the sample must be immersed in water, which, though not strictly destructive, does effectively preclude the return of the sample to production. SONUS is both non-contact and non-destructive and is designed for R&D and high-volume manufacturing.

In the run up to the product introduction, Rudolph worked closely with TEL NEXX to develop SONUS-based process control for pillar bump and TSV plating processes. Arthur Keigler, chief technology officer of TEL NEXX, said, “We are attracted by the opportunity SONUS Technology offers our mutual customers in the advanced packaging market. The ability to measure multi-metal film stacks for Cu pillar, and then continue to use the same tool for TSV void detection offers immediate productivity and cost benefits to manufacturing and development groups alike.”

While Rudolph is initially focused on using the technology for copper pillar bump process metrology and TSV inspection, they are also investigating other applications, ranging from detecting film delamination to metrology and process control for MEMS fabrication processes.

Global shutter image sensors


September 9, 2014

Different GS pixel architectures and technologies are presented and performances compared. 

BY GUY MEYNANTS, CMOSIS, Antwerp, Belgium

CMOS image sensors are in widespread use today in many consumer and professional applications. The typical shutter type for most CMOS image sensors is a so-called Rolling Shutter (RS). This is an inherent property of the 4T active pixel and its derived architectures with shared amplifier readout. The main drawback of a RS CMOS imager is that the start and the stop of the exposure is slightly shifted from pixel line to pixel line resulting in object deformation of fast moving objects (FIGURE 1) or the so-called “jello” effect when the camera is vibrating. To avoid this, either a mechanical shutter or a flash is required. Neither of these is accepted in many applications.

FIGURE 1. Rolling shutter image artifacts in the spokes of the turning wheel

FIGURE 1. Rolling shutter image artifacts in the spokes of the turning wheel

The alternative is using a so-called Global Shutter (GS) pixel based image sensor, whereby every pixel of the entire pixel array acquires the image during the same time period. This requires an in-pixel memory element that stores the signal after capture by the photodiode. Interline transfer (IT) CCDs were for many years the technology of choice for GS imagers, due to the combi- nation of global shutter with low read noise through a correlated double sampling (CDS) output stage. However, compared to CMOS image sensors, CCDs are limited to moderate readout speeds, consume more power, and lack on-chip integration of timing and AD conversion circuitry.

The first generation of GS CMOS imagers suffered from high read noise due to the lack of CDS on the charge sense node, and from poor shutter efficiency. Today, several techniques have been proposed to combine CDS with GS functionality. Meanwhile, pixel scaling efforts and microlens designs allow recovering the loss in fill factor caused by the in-pixel storage elements required in GS pixels, and allowed low-noise GS pixel design with good shutter efficiency. Shutter efficiency reports how much the stored pixel value is distorted by incoming light (which will be typically light from an unrelated exposure period which falls on the pixel when awaiting readout). It is calculated as {1 – sensitivity with shutter closed / sensitivity with shutter open} and can typically be wavelength dependent.

FIGURE 2. 5-transistor charge domain global shutter pixel (a) and 7-transistor charge domain global shutter pixel (b).

FIGURE 2. 5-transistor charge domain global shutter pixel (a) and 7-transistor charge domain global shutter pixel (b).

FIGURE 2 shows two global shutter pixels of earlier generations. Fig. 2a is a 5-transistor global shutter pixel, which stores the image on floating diffusion FD after exposure. At readout, the value sampled on FD is read through the source follower when the pixel row is selected. Then the floating diffusion is reset, and a reference level is read from the pixel. This reference level cancels any random fixed offset variations between pixels, which would otherwise cause fixed pattern noise. However, the temporal kTC noise on the floating diffusion sense node is not cancelled, since the reference for each pixel is taken after reading the photosignal, by a new reset of the sense node, which introduces a new random offset error uncorrelated to the signal level. Gate TX2 acts as an anti- blooming drain and is also used to start the exposure. The anti-blooming function is important, since excess charges are not allowed to flow to FD, where the pixel data of the previous exposure is stored.

The shutter efficiency of such pixels is not very good, typically below 99.9% for green light. The reasons why are shown in fig. 3, which is a cross-section of the 5T pixel structure. Photons generate electrons in the substrate, which diffuse through the substrate until they reach the pinned photodiode as shown in green. Some electrons generated deeper in the substrate may be collected directly by an unrelated n+ junction, such as the n+ junctions of the charge drain or the drain of the reset transistor, as shown in orange. These charges do not contribute to the photosignal and result in a loss of quantum efficiency. Some charges may diffuse to the junction of the floating diffusion, rather than by the photodiode, as shown in red. These disturb the signal stored on the floating diffusion and reduce the shutter efficiency.

This diffusion also explains the wavelength dependency of shutter efficiency for this pixel type: blue light is generated close to the surface, the majority of it inside the pinned photodiode. Part of the electrons generated by red or near infrared light are located deeper in the silicon, and have to diffuse first to the photodiode, but may reach the floating diffusion instead, which results in lower shutter efficiency for these longer wavelengths.

Often, a light shield is placed on top of the storage node to improve shutter efficiency and microlenses are used to focus the light onto the photodiode, away from the storage area. Also, a higher doped p-well under the unrelated n+ junctions can be used to reduce the charge diffusion of electrons, thanks to a small potential difference between the epitaxial p- substrate and this higher doped p-well region. A majority of the electrons will prefer to diffuse to the photodiode, where this barrier is not present.

FIGURE 3. Cross-section of a 5T charge domain global shutter pixel

FIGURE 3. Cross-section of a 5T charge domain global shutter pixel

However, a further effect that reduces shutter efficiency and which is not solved by light shields and neither by this p-well, is that some charge may leak from the photodiode through the transfer gate to the floating diffusion during the next exposure time (see Ileak in FIGURE 3). To include this effect in shutter efficiency measurements, it should be measured with constant light in a mode where the pixel integrates the next exposure during readout. Often, shutter efficiency is measured while the photodiode is drained through TX2, which cancels this transfer gate leakage, but which does not match the typical use cases for global shutter pixels in the real world, where a next image is captured during readout of the image. Furthermore, dark leakage current of the floating diffusion junction will also disturb the signal sampled on it and is a further source of noise, hot pixels and non-uniformity. This is especially important since the floating diffusion n+/p junction reaches the surface, where leakage currents will increase due to surface defects present inside the depletion region of the n+/p junction.

Fig. 2b solves the shutter efficiency and dark leakage issues of the storage node by storing the signal in voltage domain on capacitor C behind a first source follower, instead of on the floating diffusion. This capacitor can be larger and be composed of a gate or plate capacitance, which is not capable to collect electrons straight from the substrate, where they are generated by photons. In this way, the shutter efficiency can be improved above 99.98%. The pixel can be operated with double sampling by reading the reset level as a reference after reading the value sampled on C, but it still lacks correlated double sampling, just like the 5T pixel of fig. 2a. And some electrons can be collected from the substrate by the junctions of the switch connecting to the capacitor, which explains why shutter efficiency is not perfect.

For both pixel types of Fig. 2, the full well charge is proportional to the sense node capacitance, and the noise is proportional to the square root of the sense node capacitance. A typical floating diffusion of 1.6 fF, corresponding with a conversion gain of 100 μV/e-, will operate with a voltage swing of 1V. This corresponds with a saturation level of 10,000 e-. The kTC noise on 1.6 fF is 16 e- RMS. This noise appears both on the signal and reference samples, so it is increased by the square root of 2 (sqrt(2)) to 23 e- RMS at the sensor output. The dynamic range is then limited to 53 dB in this example, which is clearly lower than its IT CCD counterparts. Only if the reset level of the floating diffusion before charge transfer is used as a reference for the photosignal, it is possible to cancel the kTC noise of the sense node through CDS and reach similar dynamic range as IT CCDs.

Charge domain global shutter pixels

FIGURE 4. CDS charge domain global shutter pixel and timing


FIGURE 4. CDS charge domain global shutter pixel and timing

FIGURE 4 shows a charge transfer pixel [1] with correlated double sampling and its timing scheme. In addition to the 5T GS pixel structure, two extra transfer gates ø2 and ø3 have been added. The signal is transferred synchronously in all pixels of the array to gate ø2 after exposure. During readout, this charge packet stored under ø2 is transferred to the floating diffusion row-by- row. The floating diffusion is sampled before and after charge transfer in a CDS scheme, and hence reducing read noise. Read noise of 4.8 e- RMS [2] and 3 e- RMS [3] have been reported with this structure. Shutter efficiency of such pixel is limited, since some photo- charges generated in the substrate may be collected directly by the storage gate ø2 rather than by the photo- diode. [3] reports a shutter efficiency of 99.96%, which is again limited by charge diffusion and leakage current under transfer gate ø1.

It is clear that CDS and global shutter require two memory elements in the pixel. In this case, the floating diffusion and gate ø2 are these two memory elements. Variants of this structure have been proposed, mainly to reduce the area required for charge transfer and storage: a combined ø1/ø2 gate with two different potentials under it [2], a compact ‘pump gate’ replacing ø1/ø2 [3] or a structure where ø2 is replaced by a pinned photo-diode [4]. Though offering the best noise performance, the shutter efficiency is not satisfactory for all applications. A second problem remains dark current leakage on the storage node ø2. This storage gate is typically a surface channel device (except in [4] where it is a pinned photodiode). For lowest leakage, the storage device should be a buried channel device. But a buried channel device has lower charge storage capacity per unit area, which may limit the minimum possible pixel size.

Voltage domain global shutter pixel

FIGURE 5 shows a GS pixel structure counting 8 transistors and two in-pixel capacitors. This is a voltage domain global shutter pixel that memorizes not only the signal level but also the reset level of the floating diffusion in the pixel on a capacitor behind the first buffer amplifier. The pixel of Fig. 5 shows two storage capacitors that are connected in series but other configurations can be considered where the storage capacitors are connected in parallel or in cascade. This series connected approach resulted in the most compact pixel design. Timing is also shown in Fig. 5. The image acquisition cycle starts with an exposure of the pinned photo- diode. At the end of the exposure period, the reset level Vreset is first sampled on C2, after which charge is trans- ferred to the floating diffusion FD. Then the signal level Vsignal is sampled on C1. During readout, first the reset level is read out from C2. Then C1 and C2 are shorted. Since C1 and C2 are equal in capacitance, the signal read after shorting both capacitors is (Vsignal + Vreset)/2. The readout circuit, present typically in the column amplifier of the image sensor, calculates the difference between both pixel readings, and amplifies the signal again so that Vsignal – Vreset results.

FIGURE 5. Voltage domain global shutter pixel with CDS

FIGURE 5. Voltage domain global shutter pixel with CDS

Fig.5 shows two timing modes. In mode 1, the S2 pulse remains on during sampling of the second sample Vsignal of the pixel. In mode 2, S2 is opened again before sampling. Mode 1 contains an asymmetric gate-source cross-talk between the two samples.

This causes an extra offset between both readings and increases fixed pattern noise by approx. 30%. However, temporal read noise is lower. It can be shown that the temporal read noise of the pixel is optimum when C1 is equal to C2. In mode 1, the temporal read noise is given by kT/2C where C is the capacitance value of C1 and C2. In mode 2, the read noise is kT/C. A more complex model including noise of in-pixel transistors has been made. Read noise depends strongly on the size of in-pixel capacitors. For larger pixels, a larger capacitance can be made, and lower read noise can be reached. A 5.5 μm pixel with two in-pixel capacitors of 16 fF each has been made, resulting in 13 and 10 e- RMS in modes 2 and 1 respectively. A larger 6.4 μm pixel with two in-pixel 36 fF capacitors reached 8 e- RMS. On a smaller 3.5 μm pixel, only 8 fF was available, resulting in a read noise of 17 e- RMS.

Full well charge of the 5.5 μm pixels is limited by the swing on the floating diffusion sense node, to about 13,500 e-. This results in a dynamic range of 60 dB for the 5.5 μm pixels. The 6.4 μm pixel reaches a full well charge of 15,000 e-, which results, together with its lower noise, in 65 dB dynamic range.

Shutter efficiency of this 8T GS pixel structure is excellent thanks to a variety of reasons:

1) the capacitors C1 and C2 are implemented through gate or metal-isolator-metal capacitors, which are unable to collect charges generated in the substrate. Some small contribution of charges collected from the substrate is still possible, through the source/drain junctions of the in-pixel switches S1 and S2. But these junctions do cover only a very small area of the pixel

2) If such charges are collected from the substrate, there is a similar chance that they are collected on C1 or on C2. This creates a common-mode offset error on both the signal and reference samples stored on both capacitors, which is cancelled after CDS.

3) An electron collected on C1 or C2 has less impact on the voltage signal than an electron present on the floating diffusion, by the ratio of the capaci- tance of the floating diffusion and the storage capacitor. For example, in the 5.5 μm pixels, the floating diffusion is 1.6 fF, and the storage capacitors are 16 fF each. This means that an electron converted on FD causes a signal change of 100 μV, while an electron collected on C1 or C2 causes only a shift of 10 μV.

The reported shutter efficiency for a front-side illumi- nated (FSI) 8T GS pixel is better than 99.999%. Because the pixel does not rely on light shields and the storage nodes are almost not capable of collecting any charges from the substrate, such pixel can also be used in combi- nation with backside thinning.

Backside illumination and global shutter pixels

Today, backside illuminated CMOS image sensors have been widely adapted in consumer applications. This technology was introduced to improve light sensitivity while pixel pitch could be further reduced, to 1.4 μm and below. The same technology can also help to improve quantum efficiency and light sensitivity of global shutter pixels. Backside illumination (BSI) can also increase the light sensitive spectrum into the near and extreme UV spectrum. These wavelengths are blocked on traditional front-side illuminated image sensors due to absorption in the inter-metal dielectric layers on top of the silicon. But these wavelengths get important in more and more machine vision applications, for example semiconductor inspection.

Since with BSI, the photocharges are generated from the backside surface onwards, charge diffuse towards the photodiode gets more important. This is why obtaining good shutter efficiency is more difficult than with front-side illumination. Light shields are not very effective, since they don’t influence charge diffusion. Also, shutter efficiency now becomes worse for shorter wavelength, since these photons are absorbed closer to the surface and generate photocharges further away from the photo-diode. In particular for the charge domain global shutter pixels discussed before, it becomes difficult to avoid diffusion to the charge storage element. A voltage domain global shutter pixel with CDS can keep its good shutter efficiency thanks to the reasons mentioned before, such as the lower impact on the signal when an electron hitting the storage element, and the differential operation of the CDS voltage domain global shutter pixel.

An 8T voltage domain global shutter BSI prototype image sensor has been made and reported [6] with a shutter efficiency of 99.996%, well above the acceptance limit for almost all use cases. Read noise and full well charge, were not changed with backside illumination. QE can be optimized to the desired wavelength range by an optimized anti-reflective coating.

Scaling of global shutter pixels

The 8T pixel structure contains a lot of compo- nents (8 transistors, 2 capacitors) and a signif- icant amount of interconnect routing. The smallest possible pixel pitch in 0.18 μm CMOS is around 5.5 μm. To develop smaller 3.5 μm pixels the following approaches were taken:

1) The IC technology is switched for a smaller geometric node. CMOSIS developed pixels in a process with 110 nm front-end and 90 nm back-end design rules. This process was initially developed for 1.75 μm shared 4T pixels and allows narrow interconnect pitch. Also the height of the interconnect stack is reduced, which improves the optical performance of the pixel such as quantum efficiency and angular pixel response.

2) Pixel sharing is employed to share the first source follower in the pixel. Interconnect routing is shared to select pixels from 2 adjacent rows to 2 vertical column busses.

More details are described in [7]. In spite of the scaling, a dynamic range of 58.5 dB is reached on a 3.5 μm global shutter pixel, with a noise level of 17 e- RMS and a full well charge of 14,800 e-. Quantum efficiency is 46% at 550 nm.

Conclusions

CMOS sensors with global shutter pixels can only compete with IT-CCD devices in case when the pixel allows correlated double sampling (CDS), in order to keep the temporal read noise low. Mechanisms similar to smear in a CCD cause a degradation of shutter efficiency on the global shutter pixels, which must be dealt with effectively in pixel design. One solution is a voltage domain global shutter pixel. Several pixel implementations have been discussed, and pixel specifications of voltage domain pixels are listed in TABLE 1. Charge domain pixels offer lower read noise at the cost of decreased shutter efficiency and are more difficult to use with backside illumination. Future developments in global shutter pixels use CMOS scaling for smaller pixel structures, while aiming to at least maintain performance at the values reached today. Backside illumination can be considered, and has been demonstrated already with voltage domain global shutter pixels.

Screen Shot 2014-09-10 at 10.01.54 AM

References
1. S. Lauxtermann, A. Lee, J. Stevens and A. Joshi, “Comparison of Global Shutter Pixels for CMOS Image Sensors”, 2007 International Image Sensor Workshop, Ogunquit, ME, June 2007 (www.imagesensors.org)
2. M. Sakakibara, et al, “An 83dB-Dynamic-Range Single-Expo- sure Global-Shutter CMOS Image Sensor with In-Pixel Dual Storage”, ISSCC Dig. Tech. Papers, pp. 380-381, February 2012
3. S. Velichko, et al, “Low Noise High Efficiency 3.75 μm and 2.8μm Global Shutter CMOS Pixel Arrays”, 2013 International Image Sensor Workshop, Snowbird, Utah, June 2013 (www. imagesensors.org)
4. K. Yasutomi, et al, “A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode”, IEEE Trans. El. Dev., Vol. 58, No. 3, March 2011
5. G. Meynants, “Global shutter pixels with correlated double sampling for CMOS image sensors”, Adv. Opt. Techn. 2013; (2): pp. 177-187
6. G. Meynants, et al, “Backside illuminated Global Shutter CMOS Image Sensors”, 2011 International Image Sensor Workshop, Hokkaido, Japan, June 2011 (www.imagesensors. org)
7.B.Wolfs,etal,“3.5μmglobalshutterpixelwithtransistor sharing and correlated double sampling”, 2013 International Image Sensor Workshop, Snowbird, Utah, June 2013 (www. imagesensors.org)

Contour Semiconductor, Inc., a developer of non-volatile memory technologies, today announced it has been awarded three new patents to back its Diode Transistor Memory (DTM) technology, the world’s lowest production-cost, non-volatile memory technology.The three new patents recognize Contour’s achievements in the field of low-mask count/reduced process step memory, and bring the company’s total issued patents to 45.

The new patents focus on better and more cost effective approaches to phase-change and resistive non-volatile memory, 3D memory, and embedded memory applications – concepts that are “top of the list” for memory manufacturers and their customers.

“Contour’s patent portfolio seeks to return Moore’s Law to the non-volatile discussion, and enable the next big thing,” said Contour CEO Saul Zales. “DTM technology will overcome production and CapEx challenges that stymie NAND manufacturers, and deliver significant technical advantages over traditional NAND flash memory, to support emerging and future technologies like wearables, Internet connected devices and the Internet of Things.”

Contour estimates the production cost of its DTM to be 60-65 percent lower than today’s NAND memory, while maintaining or improving on NAND’s performance and endurance.

NAND is currently used in a wide range of products from digital photography to smartphones and solid-state drives. However, in recent years, the high costs associated with production tools and fabrication facilities have slowed NAND bit growth rate from 70-80 percent to 25-30 percent annually.

Taiwanese chipmakers, LED manufacturers, and Outsourced Semiconductor Assembly and Test (OSAT) firms will spend firm nearly $24 billion in the next two years on equipment and materials, powering excitement for SEMICON Taiwan 2014, which opened today in Taipei.  Leaders in the industry are convening for the September 3-5 event at the TWTC Nangang Hall.

Driven by consumer demand for tablet, smartphone, and mobile devices, the total semiconductor equipment market is expected to grow 20.8 percent in 2014 (reaching $38.4 billion) and expand another 10.8 percent in 2015 (exceeding $42.6 billion). SEMI forecasts that Taiwan will continue to be the world’s largest spender with $11.6 billion estimated for 2014 and $12.3 billion for 2015.

Nearly 650 exhibitors, 1,400 booths and more than 40,000 attendees are expected at SEMICON Taiwan.  Over 400 will convene for the SEMICON Taiwan Leadership Gala Dinner, one of the most important executive events for the high-tech industry in Taiwan.

SEMICON Taiwan features co-located events and technology theme pavilions focusing on IC design, MEMS, 3D-ICs, advanced packaging/testing, sustainable manufacturing, and secondary equipment.

Business Program Highlights

Facing the fast-changing business environment and global competition, companies must be prepared for unexpected challenges to survive. SEMICON Taiwan covers the critical issues in sessions focusing on market trends to executive forums.

On September 3, Cliff  Hou (VP of TSMC), Charles Kau (chairman of Inotera Memories), Tien Wu (COO of ASE Group), Lip-Bu Tan (president and CEO of Cadence), and Luc Van den hove (president and CEO of imec) will be on the SEMICON Taiwan Executive Forum stage to share their unique perspectives on Taiwan strategic role in the world’s microelectronics industry. Also on September 3, the Market Trends Forum features speakers from Barclays Capital, Gartner, IC Insights, Morgan Stanley, SEMI, TechSearch and TSMC. On September 5, the Memory Executive Summit includes presenters from ITRI/EOL, Lam Research, Micron, MXIC, and more while the CFO Executive Summit features speakers from DBS Bank (Taiwan), EQUVO, Micron, and TSMC.

Technology Programs Highlights

Wednesday, September 3

  • Advanced Packaging Technology Symposium: Presenters will cover market trends, product applications, packaging/assembly solutions (wire bond/flip chip/hybrid) to advanced equipment and material development, and testing and reliability. With experts involved from the entire supply chain, the seminar will cover the most advanced technology development directions for 3D-IC.
  • Sustainable Manufacturing Forum: Showcasing companies and speakers from around the world involved in the manufacture of semiconductors, FPD, PV, High-Brightness LEDs, MEMS, and other high tech products, experts will address a wide variety of environment, health, safety (EHS) and sustainability topics that affect high-tech manufacturing.

Thursday, September 4

  • SiP Global Summit 2014: With a strong focus on heterogeneous integration through System-in-a-Package (SiP) technology, SEMI will host the 4th annual SiP Global Summit on September 3-5.  The event features more than 20 industry leaders who will share their insights and solutions on 3D-IC, Through Silicon Via (TSV), 2.5D-IC with silicon interposer, and embedded substrate technologies. More than 500 industry professionals from around the world are expected to attend.  
  • MEMS Forum:  With a focus on “MEMS for Smart Living,” the September 4 forum will discuss the opportunities as well as challenges.

Friday, September 5

  • Embedded Technology Forum (SiP Global Summit 2014): With demand for wearable/portable devices booming, small form factor has become critical for embedded technology. The Forum reviews product applications and development progress in process and materials to give attendees a comprehensive understanding of embedded technology.
  • Litho & Mask Technology Symposium: In this symposium, exploratory lithography technologies are addressed — directed self assembly (DSA), nanoimprint technologies, multiple e-beam, and extreme ultraviolet lithography (EUV).

For more information and online registration, visit the SEMICON Taiwan website: www.semicontaiwan.org

Intel Corporation today announced two new technologies for Intel Custom Foundry customers that need cost-effective advanced packaging and test technologies.

Embedded Multi-die Interconnect Bridge (EMIB), available to 14nm foundry customers, is a breakthrough that enables a lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package. Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost.

“The EMIB technology enables new on-package functionality that may have been too costly to pursue with previous solutions,” said Babak Sabi, Intel vice president and director, Assembly and Test Technology Development.

Intel also announced the availability of its revolutionary High Density Modular Test (HDMT) platform. HDMT, a combination of hardware and software modules, is Intel’s test technology platform that targets a range of products in diverse markets including server, client, system on chip, and Internet of Things. Until now, this capability was only available internally for Intel products. Today’s announcement makes HDMT available to customers of Intel Custom Foundry.

“We developed the HDMT platform to enable rapid test development and unit-level process control. This proven capability significantly reduces costs compared to traditional test platforms. HDMT reduces time to market and improves productivity as it uses a common platform from low-volume product debug up to high-volume production,” said Sabi.

EMIB is available to foundry customers for product sampling in 2015 and HDMT is available immediately.

When ClassOne Technology introduced its new Solstice electroplating systems at SEMICON West last month they didn’t expect to actually sell their first production unit off the show floor, but that’s what happened. The company reported that the Washington Nanofabrication Facility (WNF) at the University of Washington purchased the Solstice Model LT plating tool for installation at its facility in Seattle, Washington. The WNF is a national user center that is a part of the National Nanotechnology Infrastructure Network (NNIN). WNF is a full-service micro and nanotechnology user facility and the largest public-access fabrication center in the Pacific Northwest. It provides 15,000 sq ft of laboratories, cleanrooms, and user spaces focused on enabling basic and applied research, advanced R&D and prototype production.

“The Solstice LT was exactly what we’ve been looking for,” said Michael Khbeis, Ph.D., Associate Director of the WNF. “It’s a very flexible development tool with the capabilities we need to serve our customers and perform a range of advanced processes — Through Silicon Via (TSV) plating and MEMS are particularly important to us. Plus, the LT price was within our budget, so we made our purchase commitment right there at the show.”

“And WNF wasn’t the only one,” noted Kevin Witt, ClassOne’s VP of Technology. “The customer interest in Solstice at SEMICON was unprecedented in my experience. We had high-level discussions with more than a dozen serious potential buyers, and many of those look like they will turn into purchase orders in the coming weeks.”

To date, ClassOne has announced two Solstice models: The semi-automated Solstice LT features 1 or 2 chambers for development and pilot lines and starts at $350k. The fully-automated, cassette-to-cassette Solstice S8 provides up to 8 process chambers, throughputs up to 75 wph and starts at $1M — which is less than half the cost of equivalent 300mm tools from the large manufacturers.

ClassOne Technology, founded in early 2013, produces new wet processing tools; and its stated mission is to offer more affordable alternatives to the large systems from larger equipment manufacturers. The company specifically focuses on the needs of cost-conscious smaller-substrate users in emerging technologies such as MEMS, LEDs, Power Devices, RF Communications, Interposers, Photonics and Microfluidics. In addition to electroplating systems, ClassOne Technology also provides advanced Spin Rinse Dryers (SRDs), Spray Solvent Tools (SSTs) and more.

“We’ve been very gratified by the overwhelming customer response we received at SEMICON,” said Byron Exarcos, President of ClassOne. “We describe what we do as ‘advanced wet processing tools for the rest of us,’ and it’s evident that users are really understanding — and appreciating — the concept.”

MEMSIC, Inc., a MEMS sensing solution provider, announced today the availability of its MXC400xXC, the world’s first monolithic 3D accelerometer, and also the first 3D accelerometer to utilize WLP technology. The technology breakthrough in combining the 3D IC sensor with full WLP translates directly to a 60% reduction in cost and a 50% reduction in size, enabling a new generation of mobile consumer devices including phones, tablets, toys and wearable devices.

The key to this breakthrough is MEMSIC’s proprietary and patented thermal accelerometer technology, in which the MEMS sensor structure is etched directly into standard CMOS wafers, enabling the world’s only CMOS monolithic solution. This technique uses thermal convection of heated gas molecules inside a sealed cavity to sense acceleration or inclination, and has been used for many years in MEMSIC’s products for automotive stability control and rollover detection, digital cameras, projectors and many other applications. MEMSIC’s designers have now taken the technology to a new level by combining 3D sensing with full WLP while keeping the same small size and low cost.

The MXC400xXC offers a number of benefits to system designers of space- and cost-sensitive consumer devices. In addition to offering the world’s lowest cost, the device provides 12-bit resolution on all three axes, programmable FSR of ±2g/±4g/ ±8g, an 8-bit temperature output, plus orientation/shake detection. With a package size of 1.2 x 1.7 mm, board space is reduced by 50% over industry-standard 2×2 mm solutions. And like all MEMSIC thermal accelerometers, the MXC400xXC has no moving parts, making the sensor structure extremely robust to shock and vibration (withstands shock in excess of 200,000g with no change in sensor performance). This is critically important to wearable and many consumer applications.

Dr. Yang Zhao, MEMSIC CEO and Founder, commented “While we have been supplying thermal accelerometers for more than a decade, the MXC400xXC is a real breakthrough in sensor design, signal processing architecture and MEMS WLP. This is the industry’s first and only monolithic 3D accelerometer with full WLP technology, enabling us to achieve a new level of size and cost, which are critical for mobile consumer devices.”