Category Archives: 3D Integration

Applied Materials, Inc. today introduced the Endura Ventura PVD system that helps customers reduce the cost of fabricating smaller, lower power, high-performance integrated 3D chips. The system incorporates Applied’s latest innovations to its industry-leading PVD technology that enables the deposition of thin, continuous barrier and seed layers in through-silicon-vias (TSVs). Demonstrating Applied’s precision materials engineering expertise, the Ventura system also uniquely supports the use of titanium in volume production as an alternate barrier material for lower cost. With the launch of the Ventura system, Applied is expanding its comprehensive toolset for wafer level packaging (WLP) applications, including TSVs, redistribution layer (RDL) and Bump.

TSVs are a critical technology for vertically fabricating smaller and lower power future mobile and high-bandwidth devices. Vias are short vertical interconnects that pass through the silicon wafer, connecting the active side of the device to the back side of the die, providing the shortest interconnect path between multiple chips. Integrating 3D stacked devices requires greater than 10:1 aspect ratio TSV interconnect structures to be metallized with copper. The new Ventura tool solves this challenge with innovations in materials and deposition technology to manufacture TSVs more cost-effectively than previous industry solutions.

“Building on 15 years of leadership in copper interconnect technology, the Ventura system enables fabrication of robust high-aspect ratio TSVs, with up to 50 percent barrier seed cost savings compared to copper interconnect PVD systems,” said Dr. Sundar Ramamurthy, vice president and general manager of Metal Deposition Products at Applied Materials. “These innovations deliver a higher-performance and more functional, yet, compact chip package with less power consumption to meet leading-edge computing needs. Customers are realizing the benefits of this new PVD system and are qualifying it for volume manufacturing.”

Supporting the manufacture of high-yielding 3D chips, the Ventura system introduces advances in ionized PVD technology that assure the integrity of the barrier and seed layers that are critical to superior gap-fill and interconnect reliability. These developments significantly improve ion directionality to enable the deposition of thin, continuous and uniform metal layers deep into the vias to achieve the void-free fill necessary for robust TSVs. With the improvement in directionality, higher deposition rates can be achieved, while the amount of barrier and seed material needed can be reduced. These attributes of the Ventura system and the adoption of titanium as an alternate barrier are expected to improve device reliability and reduce the overall cost of ownership for TSV metallization.

Applied Materials, Inc. provides equipment, services and software to enable the manufacture of advanced semiconductor, flat panel display and solar photovoltaic products.

­Ziptronix Inc. and EV Group today announced they have successfully achieved submicron post-bond alignment accuracy on customer-provided 300mm DRAM wafers. The results were achieved by implementing Ziptronix’s DBI Hybrid Bonding technology on an EVG Gemini FB production fusion bonder and SmartView NT bond aligner. This approach can be used to manufacture fine-pitch 3D ICs for a variety of applications including stacked memory, advanced image sensors and stacked systems-on-chip (SoCs).

“The performance of DBI Hybrid Bonding technology is not limited by connection pitch, but requires the right alignment and placement tool with an ability to scale that has been a challenge to find until now,” said Paul Enquist, CTO and VP Engineering at Ziptronix. “EVG’s fusion bonding equipment has been optimized to achieve consistent submicron post-bond alignment accuracy. This advancement in alignment accuracy provides a clear path to high-volume manufacturing (HVM) of our technology.”

Pitch scaling on next-generation 3D technologies is expected to continue for many years to come. Fine-pitch hybrid bonding is already in use in high-performance 3D memory products, and has been announced for HVM of 3D image sensors. DBI Hybrid Bonding can be used at the die or wafer level; however, wafer-level bonding enables a great cost benefit by bonding all the die at once. With much of the processing for DBI Hybrid Bonding taking place at wafer scale, there is the added benefit of low cost-of-ownership.

“Demonstrating submicron accuracy is critical to achieving fine-pitch connections in HVM for a wider variety of applications,” said Paul Lindner, Executive Technology Director at EVG. “As the industry pushes to realize 3D ICs, joint efforts such as our work with Ziptronix to develop manufacturing approaches offer customers a tremendous value-add.”

Ziptronix Direct Bond Interconnect Hybrid Bonding is a conductor/dielectric bonding technology that includes a variety of metal/oxide and/or nitride combinations, does not use adhesives and is currently the most suitable for volume manufacturing in the marketplace. It allows for strong, room temperature dielectric bonding, low temperature conductive bonding and finer-pitch interconnect over Cu/Cu or other metal bonding because the bond occurs between both the dielectric and the conductive surfaces, which effectively bonds the entire substrate interface area.

EVG’s SmartView Automated Bond Alignment System for Universal Alignment offers a proprietary method of face-to-face wafer-level alignment, which is key to achieving the required accuracy in multiple wafer stacking for leading-edge technologies. In addition to improving alignment capabilities on its SmartView bond aligner to reach submicron accuracies, EVG has optimized it so that surfaces can be prepared simultaneously for bonding, electrical connectivity and mechanical strength.

SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, today announced the launch of its Rapier XE system for 300mm wafer silicon etching. The new module offers significant advantages over competing systems as well as improved etch rate over the 1st generation Rapier in applications where “blanket” etching or removing a large exposed area of silicon is required, such as via reveal processing.

In 3D-IC applications, via reveal processing occurs after the through silicon vias (TSVs) are formed, to prepare the vias for redistribution metallization.  After completion of front-side wafer processing, the wafer is temporarily bonded, face down, onto a carrier wafer. The active silicon is then ground typically to within 5-10 μm of the TSV nodes. The silicon is then dry etched in a process that ‘reveals’ the vias to a step height typically in the range 2-5µm. To maximize yield, it is critical that all vias are revealed to a uniform height, which can be extremely challenging if the incoming wafer thickness varies across a wafer or from one wafer to the next.  In the 1st generation Rapier and now the new Rapier XE system, issues of wafer-to-wafer silicon thickness variation is overcome with the use of the ReVia endpoint system.

Dave Thomas, SPTS’ marketing director for etch products, explained: “While the dual-source design of our 1st generation Rapier proved useful for tailoring the cross-wafer etch profile, coupled with our in-situ ReViaTM endpoint system to deal with wafer-to-wafer non-uniformities, we saw the need to improve etch rates for more cost effective high volume production. Our engineering and R&D teams worked closely together to develop a solution that  delivers a blanket silicon etch rate on 300mm wafers 3 to 4 times faster than competing dry etch systems, with a cross-wafer uniformity of ≤+/- 3%.  This enhanced design is also available to existing Rapier customers as an upgrade which can be retrofitted in the field.”

Kevin Crofton, president and COO of SPTS added, “With this new etch product, and our other processes like low temperature PECVD, we believe we offer our production customers the best throughput and process control for 300mm via reveal processing currently available on the market.  We continue to be committed to helping our customers improve throughputs and device yields while reducing costs, wherever possible, to remain competitive.”

SPTS will be showcasing its range of etch, deposition and thermal processing as well as advanced packaging solutions at ECTC 2014 at Walt Disney World Swan and Dolphin Resort, 27-30 May, 2014.

The 17th annual IITC will be held May 21 – 23, 2014 in conjunction with the 31st AMC at the Doubletree Hotel in San Jose, California, representing an annual series of meetings devoted to leading-edge research in the field of advanced metallization and 3D integration for ULSI IC applications. It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” today, Tuesday, May 20.

The 2014 IITC/AMC will focus on innovative developments in the critically important field of interconnections for electronic systems, presenting papers on all aspects of interconnects for device, circuit board and system-level applications. Topics include both fundamental and applied research, as well as issues related to introduction of enabling technologies into manufacturing. This year’s conference intends to provide a forum for open discussions ranging from basic science to industrial application, targeting material scientists, process and integration engineers and PhD students active in the areas of semiconductor processing, advanced materials, equipment development, and interconnect systems.

CLICK HERE TO LAUNCH SLIDESHOW

Further details are available at the conference website: http://www.ieee.org/conference/iitc

Although on-chip interconnects have not been scaling at the same speed as other parts of the chip, new capabilities enabled by graphene and CNTs, among other materials, could soon change that.

By Pete Singer

Transistor speed used to be the limiting factor for chip performance, but increasingly on-chip or Back End of Line (BEOL) interconnects have become a limiting factor. While transistors and other aspects of ICs have been continually made smaller, inter- connect scaling essentially stopped at the 20nm node. In part, this decision was made to save costs (i.e., reuse masks and avoid more complex lithog- raphy steps). There was also concern about imple- menting too many major changes at the same time. “When you have ten layers of metal and let’s say six layers of those are close to minimum pitch, it gets very expensive once you start doing double patterning,” said Dr. Deepak Chandra Sekar, general co-chair of the upcoming 2014 IITC/AMC joint conference. “With the interconnect layers, people want to save litho costs. That’s one reason they are not scaling as much as they used to.”

The major reason is that it’s difficult to make interconnects much smaller without introducing significant increases in resistivity. “If you scale down and your resistivity goes up exponentially, it can be a problem,” Sekar said. “Copper resistivity shoots up when you scale it down because of surface scattering, grain boundary scattering and interface roughness.” It’s well known that the electrical resistance (R) of the wires, or lines, increases as they are made thinner. It also arises because capacitive coupling (C) can occur among adjacent lines spaced very closely together. Speedor frequency is directly related to the inverse of the RC time constant (fc = 1/2πRC).

FIGURE 1. Work at IBM and Applied Materials showed a 10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi- layer SiN cap, cobalt cap and wrap-around cobalt liners.

FIGURE 1. Work at IBM and Applied Materials showed a 10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi- layer SiN cap, cobalt cap and wrap-around cobalt liners.

Two upcoming conferences are worthy of special note: IITC/AMC and IRPS. The 17th annual Inter- national Interconnect Technology Conference (IITC) will be held May 21 – 23, 2014 in conjunction with the 31st Advanced Metallization Conference (AMC) at the Doubletree Hotel in San Jose, California (http://www.ieee.org/conference/ iitc). It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: schemes are shown to provide a 1000x improvement in electromigration lifetimes. The paper is titled “Advanced Metal and Dielectric Barrier Cap Films for Cu Low k Interconnects.”

Graphene and CNTs

Further out, it appears is if graphene hold tremendous promise as a possible replacement for copper. In work reported earlier this year by Georgia Institute of Technology, it was shown that electrical resistance in nanoribbons of epitaxial graphene changes in discrete steps following quantum mechanical principles (FIGURE 2). The research shows that the graphene nanoribbons act more like optical waveguides or quantum dots, allowing electrons to flow smoothly along the edges of the material. In ordinary conductors such as copper, resistance increases in proportion to the length as electrons.

FIGURE 2. Conceptual drawing of an electronic circuit comprised of interconnected graphene nanoribbons (black atoms) that are epitaxially grown on steps etched in silicon carbide (yellow atoms). Electrons (blue) travel ballistically along the ribbon and then from one ribbon to the next via the metal contacts. Electron flow is modulated by electrostatic gates. (Courtesy of John Hankinson, Georgia Tech).

FIGURE 2. Conceptual drawing of an electronic circuit comprised
of interconnected graphene nanoribbons (black atoms) that are epitaxially grown on steps etched in silicon carbide (yellow atoms). Electrons (blue) travel ballistically along the ribbon and then from one ribbon to the next via the metal contacts. Electron flow is modulated by electrostatic gates. (Courtesy of John Hankinson, Georgia Tech).

Where are we now and where do we go from here?” on Tuesday, May 20. The International Reliability Physics Symposium (IRPS) will be held June 1-5 at the Hilton Waikoloa Village, Waikoloa, Hawaii (http://www.irps.org).

Reliability is important because it’s another challenge to scaling of interconnects. Both time- dependent-dielectric-breakdown (TDDB) and electromigration lifetimes for interconnects drop rapidly when scaled.

At both IITC/AMC and IRPS, a variety of papers will be presented that look at new materials that could enable continued scaling of conventional interconnects, while also addressing reliability challenges. These range from tweaks to existing processes to radically new strategies that could provide a viable alternative to copper/low-k.

At IITC/AMC, for example, IBM and Applied Materials will present a multi-layer SiN cap process is developed that shows higher breakdown and lower leakage compared to conventional SiCNH caps (FIGURE 1). Selective cobalt caps in combination with the multi-layer SiN cap are shown to provide a 10x improvement in electromigration lifetimes. Wrap-around cobalt liners in combination with the cap layer encounter more and more impurities while moving through the conductor.

The ballistic transport properties, similar to those observed in cylindrical carbon nanotubes, exceed theoretical conductance predictions for graphene by a factor of 10. The properties were measured in graphene nanoribbons approximately 40nm wide that had been grown on the edges of three-dimensional structures etched into silicon carbide wafers. “This work shows that we can control graphene electrons in very different ways because the properties are really exceptional,” said Walt de Heer, a Regent’s professor in the School of Physics at the Georgia Institute of Technology. “This could result in a new class of coherent electronic devices based on room temperature ballistic transport in graphene. Such devices would be very different from what we make today in silicon.”

Sekar also highlighted a number of papers that will be presented this year that focus on new materials that could lead to reduced resistivity and enable further interconnect scaling. “There
is a lot of excitement about carbon and carbon- copper composites eventually replacing copper,” he said. “At IITC this year, we have a couple of papers, one on graphene showing lower resistivity than copper, and then one on carbon nanotubes showing good resistivity as well. They are

still a bit far out in the sense that there’s 
a lot more process integration work that needs to be done because these are proof of concept demos, but they show that there might be more beyond copper.”

In a paper from AIST, titled “Sub 10nm wide intercalated multi-layer graphene interconnects with low resistivity,” work will be presented that demonstrates 8nm wide 6.4nm thick graphene intercon- nects with a resistivity of 3.2uohm-cm (FIGURE 3), which is significantly better than copper with similar dimensions. This milestone for graphene inter- connect research is expected to motivate the process integration research that is required to take the technology to the next level.

FIGURE 3. Work 8nm wide graphene interconnects.

FIGURE 3. Work 8nm wide graphene interconnects.

Carbon nanotubes (CNTs) have been explored as a material for vertical inter- connects for many years since they can handle higher current densities than copper and offer ballistic transport. A paper from imec titled “Electron Mean Free Path for CNT in Vertical Intercon- nects Approaches Copper,” work will be presented that demonstrates a 5x improvement in electron mean free path for CNTs compared to previous work (FIGURE 4). The CNT mean free path of 24-74nm approaches copper. Contact resistance is improved significantly compared to previous work as well.

FIGURE 4. Carbon Nanotube (CNT) vias in integrated structures.

FIGURE 4. Carbon Nanotube (CNT) vias in integrated structures.

Of course, an alternative to making everything smaller by scaling is
to go 3D. That will be
addressed by a variety of papers, including one from CEA-Leti focused on 3D monolithic integration. While most of today’s through-silicon vias (TSVs) are in the 5μm range, monolithic 3D technologies offer TSVs in the 50nm range, which allows dense connectivity between different layers in a 3D-IC.
In the Leti paper, such dense connectivity is
shown to provide 55% area reduction and 47% energy-delay product improvement for a 14nm FPGA design (FIGURE 5). Transistor technologies that allow monolithic 3D integration are experimentally demonstrated. “When you make the TSVs smaller and smaller, you can reduce the length of on-chip wires as well by taking what’s on a single now and stacking them into two layers,” Sekar said. “That might save a lot of power and area. There’s been a lot of talk about monolithic 3D, but these are some of the first few experimental demonstrations showing that it’s possible.”

FIGURE 5. Monolithic 3D-ICs produced by Leti.

FIGURE 5. Monolithic 3D-ICs produced by Leti.

Through Silicon Vias (TSVs), an important component of 3D chip stacking technology, typically have a “keep-out zone” around them, where transistors are not placed. This is due
to co-efficient of thermal expansion mismatch between the copper TSVs and silicon, which introduces tensile stresses in the silicon and changes transistor performance. These keep-out zones are typically >7μm, which adds constraints for design and leads to die size penalties.

Perhaps the ultimate ways of sending signals
is not with electrons but with photons. Optical interconnects are already in use in telecommunications, and have been implemented at the backplane level on computer systems. Someday, we could see chip-to-chip level
optical communication,
and perhaps even
on-chip.

In work from GLOBALFOUNDRIES, a CMP 
stop layer is specially designed such that it introduces compressive stresses on the silicon and compensates for the tensile stresses introduced due to copper TSVs (FIGURE 6). The result is a near-zero keep-out zone for TSV technology, that is validated with simulations as well as experiments.

FIGURE 6. Copper shrinkage results in tensile stress in the silicon while CMP stop layer shrinkage results in compressive stress in the silicon.

FIGURE 6. Copper shrinkage results in tensile stress in the silicon while CMP stop layer shrinkage results in compressive stress in the silicon.

At IITC, the first talk after the plenary talk is title “Nanophotonic
and Interconnects – Status and Future Directions,” and will be delivered by
one of the original pioneers in the field, David A.B. Miller, who runs the Ginzton Laboratory at Stanford University.

“Optical interconnects at progressively shorter distances and higher communications densities demand novel optics and very low operating energies. Optoelectronics with femtojoule or lower energies and compact custom and self-designing optics may enable the lower energy per operation and higher bandwidth density required for continued scaling of information processing, with significant potential impact for systems,” Miller says in his summary.

FIGURE 7. At the VLSI Symposium, Micron Technology will describe the first monolithic silicon-photonics-on-bulk-CMOS process flow to connect distant distributed memories.

FIGURE 7. At the VLSI Symposium, Micron Technology will describe the first monolithic silicon-photonics-on-bulk-CMOS process flow to connect distant distributed memories.

The upcoming Symposia on VLSI Technology & Circuits (http://www. vlsisymposium.org/), scheduled for Honolulu from June 9-12 (Technology) and June 10-13 (Circuits). Of particular note is a highlighted paper from researchers at Micron Technology describing the first monolithic silicon- photonics-on-bulk-CMOS process flow to connect distant distributed memories (FIGURE 7). Features include deep- trench isolation, polysilicon waveguides, grating couplers, filters, modulators, and detectors. Fully functional on-chip CMOS enables transmit/receive operation while minimizing interconnect parasitics. With the addition of an external 1280-nm light source, a fully functional optical link (5 Gb/s with 2.8 pJ/b), capable of WDM (wavelength division multiplexing), has been demonstrated. In addition to the polysilicon resonant detector used in the link, a monolithically integrated SiGe-based photodetector using selective epitaxial growth was also developed.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

The research focuses on integrating extra layers of transistors on a vertically integrated 3D monolithic chip using printing of semiconductor “inks” as compared to the current method of chip-stacking through 3D interconnect solutions.

The new process technology could help semiconductor manufacturers develop smaller and more versatile components that are less expensive and higher performing by enabling cost-effective integration of additional capabilities such as processing, memory, sensing and display. The low-temperature process is also compatible with polymer substrates, enabling potential new applications in wearable electronics and packaging.

Current efforts on 3D integration have used transfer of thin single crystal semiconductor layers, polycrystalline silicon deposited by chemical vapor disposition, or other growth techniques to realize integrated devices.

“Compared to these approaches, we believe our approach is simpler and potentially with significantly lower cost,” said Vivek Subramanian, professor of Electrical Engineering and Computer Sciences at UC Berkeley. “Our goal in this work is to maximize performance, with the hope that this will make the cost versus performance tradeoff worthwhile relative to other approaches.”

Specifically, the UC Berkeley team is developing directly-printed transparent oxide transistors as a path to realizing additional layers of active devices on top of CMOS metallization.

To fabricate such devices, new material and process methodologies are needed for depositing nanoparticles for semiconductors, dielectrics and conductors. The research is particularly focused on solution-based processing due its low temperature compatibility with CMOS metallization as well as the potential for lower cost manufacturing.

“Initial results from the Berkeley team show that reasonably high performance can be obtained from ink-jet printed devices with process temperatures that are compatible with post-CMOS metallization, thus enabling a new route to monolithic 3D integration,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

Ziptronix Inc., a provider of patented, low-temperature direct bonding technology for 3D integration, today announced a limited exclusive patent licensing agreement with IO Semiconductor (IOsemi) for application of its ZiBond technology for use in RF front-end devices for consumer mobile products. The agreement also marks a new high-volume application market for Ziptronix’s proprietary ZiBond technology.

IOsemi’s ZEROcap CMOS technology is based on a mature 0.18µm CMOS process. It provides RF performance with lower insertion loss and better linearity than other available technologies. This performance is achieved while delivering smaller footprints and lower cost than competitive devices. Implementing ZiBond further enables the low-cost manufacture of RF switches using standard CMOS processes. Because the bond itself is as strong as or stronger than the bulk material, it stands up better to post-bond processes than other bonding technologies.

“Licensing ZiBond for use in RF front-end applications adds a highly manufacturable, high-volume bond to our technology arsenal,” said Mark Drucker, CEO of IO Semiconductor. “It provides a key enabling technology that has allowed IOsemi to deliver better-performing, lower-cost RF solutions than our competitors. We have implemented this process with a top-tier manufacturing partner and have achieved world-class yields and reliability.”

Ziptronix’s proprietary ZiBond process allows for the formation of low-temperature, direct, nonadhesive wafer-to-wafer and die-to-wafer bonds in a wide variety of semiconductor materials by using a very thin layer of materials such as silicon oxide or nitride to facilitate direct bonding. Already established in volume production for back-side illumination (BSI) image sensors, the license agreement with IOsemi takes ZiBond into high-volume manufacturing for RF front-end devices as well, further proving its value to the consumer mobile market.

Tessera Technologies, Inc. announced today that Invensas Corporation and South Korea-based STS Semiconductor & Telecommunications, a semiconductor assembly and test solution provider, have entered into an agreement to validate high volume manufacturing capability for Invensas’ Bond Via Array (BVATM) technology for next generation smartphone and tablet customers.

BVA is a proven advanced package-on-package (PoP) technology for System on Chip (SOC) and memory integration in mobile devices. Styled as a “Bridge Technology to 3DIC,” it is a unique solution that utilizes established wire-bond assembly techniques to enable low power and high-bandwidth (1000 IO+) packaging in an ultra-small form factor, ideal for mobile devices. STS’s state of the art engineering and worldwide high-volume capabilities provide an ideal platform for high volume manufacturing of BVA.

“We are delighted to partner with Invensas on BVA,” stated Chang-Bum Shim, Chief Operating Officer and Executive Vice President for STS. “STS understands the critical need to increase interconnect bandwidth for the growing Package-on-Package mobile SOC market, without increasing product size or the cost to the end user. Our engineering and manufacturing capabilities are ideally suited to the commercialization of BVA.”

“STS is an ideal partner for BVA,” said Simon McElrea, CTO of Tessera Technologies, Inc. and President of Invensas. “Their continual investment in cutting-edge packaging technology and associated manufacturing capability, coupled with their growth model in mobile and communication devices, is perfectly aligned for BVA commercialization.”

With the SOI business decreasing, the 3D TSV stack beginning, and the competitive environment changing with EV Group, Applied Materials, Tokyo Electron and many new entrants. Yole Développement analyzes the permanent bonding market & technology trends and announces today its new study: Permanent Wafer Bonding report.

Permanent bonding technology is a key process for a wide range of applications in the semiconductor industry such as MEMS, advanced packaging, LED devices, and SOI substrate applications.

Screen Shot 2014-04-18 at 12.02.59 PM

“These have been the 4 main leading applications for permanent bonding for several years. Permanent bonding processes are increasingly more importance within the semiconductor industry”, announces Amandine Pizzagalli, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement (Yole).

Under this Permanent Wafer Bonding report, Yole’s analysts give an overview of technical characteristics for each existing permanent bonding processes and related applications. They review key technical insight into future permanent bonding technologies trends and challenges. Yole’s experts also analyze the market trends and provide a clear mapping of this industry including market metrics & dynamic from 2013 and 2019.

The permanent bonding market is evolving, and currently dominated and fragmented by three main permanent bonding equipment suppliers: EV Group, SUSS MicroTec, and Tokyo Electron.
“These three vendors today account for almost 80 percent of the permanent bonding equipment market by focusing on MEMS and Advanced Packaging applications including BSI CMOS Image Sensors, CIS capping WLP, and 3D stack TSV,” ensures Amandine Pizzagalli, from Yole Développement.

EV Group is still the market leader in permanent bonding technology with more than 70 percent of market share, but will be challenged by the merging of Tokyo Electron and Applied Materials, two of the largest semiconductor equipment suppliers in the world.

The entrance of aggressive new players is likely to challenge established players in the permanent bonding market:

  • Some players have recently entered the market with low barriers of entry such as Mitsubishi Heavy Industry; mainly with customers involved in the R&D sector.
  • Other big equipment suppliers have created a challenging environment and stimulate technology innovation for further improvements in the advanced packaging area.
  • Tokyo Electron has gained more market share in 2013 from permanent bonding technologies – with significant market share achieved due to their deep involvement in 3D TSV stack bonding technology performed at room temperature.

    The merger of Tokyo Electron and Applied Materials questions the involvement of permanent bonding equipment suppliers in future development.
    In parallel, SUSS MicroTec, who provided automatic bonders for production for 10 years, stopped making them in 2013. This demonstrates that the permanent bonding market is very challenging. This big change in the permanent bonding market environment will create a new battle in this field, which is going to be very interesting in the next five years.

    Yole Développement’s report provides an in-depth competitive analysis of key permanent bonding equipment suppliers, with profiles of the main equipment vendors, and their future in the permanent bonding market. More info. on www.i-micronews.com, reports section.

By Dr. Phil Garrou – Contributing Editor

The annual IMAPS Device Packaging Conference in Ft. McDowell, AZ is always a source for the latest packaging information.

Ron Huemoeller, Sr VP at Amkor indicated that they are seeing customer programs using 2.5D silicon interposers to create mixed node modules, i.e. only the circuits that require it are moving to 14nm while the rest of the circuits are remaining on a separate chip using a legacy 28nm process. Reportedly this results in a lower cost solution.

Speaking of lower cost, Tezzaron / Novati CTO Bob Patti addressed the interposer cost issue head on during a panel session when he commented that silicon interposers at Novati today will cost you 25 cents per sq. mm but they see a path to eventually get the cost down to 2 cents per sq mm.

During Qualcomm’s Steve Bezuk keynote talk on mobile packaging he noted that 7B smartphones are expected to be shipped between 2013 and 2017. With handset thickness quickly approaching 6mm and the battery and screen not shrinking, the package and board must absorb all the z direction miniaturization. Thinner substrates have been achieved so far by using thinner cores . To avoid warpage suppliers have used lower and lower CTE core materials. Since that has now run out of steam they will now be looking for low CTE materials with higher modulus to maintain stiffness.

Bzuk’s comment on 2.5/3D that “…we are not yet sure what the substrate material should be (Si, laminate or glass) or where it will be coming from…” is a sober reminder that mobile will likely not be the initial driver for TSV based technologies.

Bryan Black, Sr Fellow at  AMD brought some good news for the 3D community when he stated “Die stacking is catching on in FPGAs, Power Devices, and MEMs but there is nothing in mainstream computing CPUs, GPUs, and APUs …HBM Stacked DRAM will change this!” He predicts that we will see 3X the bandwidth/watt using stacked memory.

AMD

As we have mentioned in previous blogs Black predicts the SiP of tomorrow will be separately optimized / manufactured  functions  stacked on an interposer. While the busses needed to connect these functions will be complex, Black is convinced that this is doable . Black indicates that AMD and partner Hynix are currently looking  for partners to develop such products.

AMD 2

Brandon Prior of Prismark reported a major move to 0.4mm pitch by 2018 (28% of all CSP/WLP) but notes that challenges remain for assembly yield and PCB routing for 0.35mm and below.  Prismark predicts that performance DDR will adopt flip chip at all of the major memory suppliers with 5B units being shipped by 2018.

Prismark