Category Archives: 3D Integration

By Ed Korczynski, Senior Technical Editor, SST/SemiMD

With anticipated economic limits to the continuation of Moore’s Law now on the horizon, it seems that moving into the 3rd dimension (3D) by stacking multiple layers of integrated circuits (IC) will be the ultimate expression of CMOS technology. Whether stacking heterogeneous chips using through-silicon vias (TSV), or monolithic approaches to forming multiple active IC layers on a single silicon substrate, 3D ICs should be both smaller and faster compared to functionally equivalent 2D chips and packages.

However, 3D ICs will likely always cost more than doing it in 2D, due to more step being needed in manufacturing. A recent variation of 2D IC packaging with some of the benefits of 3D is the use of silicon interposers containing TSV.

Current state-of-the-art electronic design automation (EDA) tools exist to handle complex IC systems, and can therefore handle complex 3D designs as long as the software has the proper inputs from a foundry’s Process-Design Kit. Figure 1 shows the verification flow for a multi-chip system using the “3DSTACK” capability within Mentor Graphics’ Calibre platform. Leading IC foundries GlobalFoundries and TSMC as well as 3D IC specialty foundry Tezzaron have all qualified 3DSTACK for their 2.5D and 3D design verifications.

FIGURE 1: “3DSTACK” functionality integrates with existing 2D Design Rule Check (DRC) modules within the Calibre platform. (Source: Mentor Graphics).

EDA tools have evolved in complexity such that Design-For-Test (DFT) methodologies and technologies now exist to tackle 3D ICs. Steve Pateras, product marketing director, DFT, Design to Silicon Division of Mentor Graphics advised, “If you’re stacking multiple die together, you need to work with known good die. The ROI basically changes for stacking, such that you need to get into a different regime of test.” In a die stack we have to think about not just known good die, but die known to be good after they are stacked, too. The latter condition mandates standards for DfT to allow test signals to flow between layers.

The IEEE 1838 working group on 3D interface standards is intended for heterogeneous integration, allowing for different IC process technologies, design set-ups, test, and design-for-test approaches. The standard defines test access features that enable the transportation of test stimuli and responses for both a target die and its inter-die connections.

Figure 2 shows the extra die interfaces that must be physically verified within a 3D IC system stack. Die interfaces can be mis-aligned due to translation or rotation during assembly, and with die from different fabs at different geometries it can be non-trivial to ensure that the rights pins are connected.

FIGURE 2: Schematic cross-section of a 3D IC system showing the die interfaces that require new Physical Verification (PV) checks. (Source: Mentor Graphics).

3D memory stacks are somewhat in their own category since they are primarily designed and manufactured by IDMs, though often with a logic layer on the bottom they are mostly homogenous, and since memory usually runs cooler than logic they generally have no cooling issues. For these reasons 3D memory stacks using wire-bonds have been in volume production for years, Micron leads the development of the Hybrid Memory Cube using TSV, and Samsung leads in growing multiple memory layers on a single silicon chip.

Future Demand for 3D Logic

So far, the only known commercial logic chips shipping with TSV are the Xilinx Virtex-7 product, where four 28nm node FPGAs (as reported by Phil Garrou in 2011 in his IFTLE blog) are connected to a silicon interposer. Xilinx has shown that much of the motivation for using 2.5D packaging was to improve yield when working with the maximum number of logic gates in the smallest available process node, and when foundry yields improve with learnings for a given node we would expect that the FPGA would be made using a single-chip 2D solution.

It appears that 2.5D is not so much a stepping-stone to 3D, as it is a clever variant on established 2D advanced packaging options. Silicon interposers with TSV offer certain advantages for integration of high-speed logic in 2D, but due to relatively greater cost compared to other WLP methods will likely only be used for high-margin parts like the Virtex-7. Also, Out-Sourced Assembly and Test (OSAT) companies have been offering both “fan-out” and “fan-in” wafer-level packaging (WLP) options, and heterogeneous integration can certainly be done using these approaches. “We have customers planning on using interposers, but they’re planning on lower-cost substrates,” commented Michael Buehler-Garcia, senior marketing director for Calibre, Design to Silicon Division of Mentor Graphics.

If high volume CMOS logic will always be most cost-effectively integrated in a single 2D slice of silicon, and heterogeneous integration of CMOS can be done in 2D using FD-SOI substrates, then what remains as the demand driver for future 3D logic stacks? What logic products require heterogeneous integration for basic functionality, would be band-width-limited by 2D packages, and also are anticipated to be shipped in sufficiently high-volume to allow for amortization of the integration costs?

Several vendor have recently launched 100G C form-factor pluggable (CFP) modules to increase speeds while reducing costs in communicating between data servers. ClariPhy produces a CFP SoC using a 28nm CMOS process that is packaged with laser diode chips from Sumitomo Electric Industries’ (SEI). “By combining ClariPhy’s SoC with SEI’s world class indium phosphide optics technology and deep experience in volume manufacturing of pluggable optical modules, we will deliver the benefits of coherent technology to metro and datacenter networks,” said Nobu Kuwata, general manager of the Technology and Marketing Department of Sumitomo Electric Device Innovations (SEDI). “We will provide first samples of our 100G coherent CFP next quarter.”

Even greater cost and power savings could derive from a revolution in the interconnections used not just between servers but inside the server farms that provide the ubiquitous “cloud computing” we are all coming to enjoy. “It’s still a couple of years out, but we’re doing research on DARPA projects now,” says Buehler-Garcia in reference to work Mentor Graphics is doing to bring the automation of its Calibre platform to this application space.

The EDA industry’s ability to handle system-on-chip (SoC) and system-in-package (SiP) layouts means that the differences between designing for 2D, 2.5D, and 3D logic should be minimal. “We don’t charge extra for 3D,” explained Buehler-Garcia, “it’s already part of the deal.” ‑E.K.

This article originally appeared on SemiMD, part of the Solid State Technology network

By Ron Press, Mentor Graphics

Three-dimensional (3D) ICs, chips assembled from multiple vertically stacked die, are coming. They offer better performance, reduced power, and improved yield. Yield is typically determined using silicon area as a key factor; the larger the die, the more likely it contains a fabrication defect. One way to improve yield, then, is to segment the large and potentially low-yielding die into multiple smaller die that are individually tested before being placed together in a 3D IC.

But 3D ICs require some modification to current test methodologies. Test for 3D ICs has two goals: improve the pre-packaged test quality, and establish new tests between the stacked die. The basic requirements of a test strategy for 3D ICs are the same as for traditional ICs—portability, flexibility, and thoroughness.  A test strategy that meets these goals is based on a plug-and-play architecture that allows die, stack, and partial stack level tests to use the same test interface, and to retarget die-level tests directly to the die within the 3D stack.

A plug-and-play approach that Mentor Graphics developed uses an IEEE 1149.1 (JTAG) compliant TAP as the interface at every die and IEEE P1687 (IJTAG) networks to define and control test access. The same TAP structure is used on all die, so that when doing wafer test on individual die, even packaged die, the test interface is through the same TAP without any modifications.

When multiple die are stacked in a 3D package, only the TAP on the bottom die is visible as the test interface to the outside world, in particular to the ATE. For test purposes, any die can be used as the bottom die. From outside of the 3D package, for board-level test for example, the 3D package appears to contain only the one TAP from the bottom die.

Each die also uses IJTAG to model the TAP, the test access network, and test instruments contained within the die. IJTAG provides a powerful means for the test strategy to adjust to and adopt future test features. It is based on and integrates the IEEE 1149.1 and IEEE 1500 standards, but expands beyond their individual possibilities.

Our test methodology achieves high-quality testing of individual die through techniques like programmable memory BIST and embedded compression ATPG with logic BIST. The ATPG infrastructure also allows for newer high-quality tests such as timing-aware and cell-aware.

For testing the die IO, the test interface is based on IEEE 1149.1 boundary scan. Bidirectional boundary scan cells are located at every IO to support a contactless test technique which includes an “IO wrap” and a contactless leakage test.  This use of boundary scan logic enables thorough die-level test, partially packaged device test, and interconnect test between packaged dies.

The test methodology for 3D ICs also opens the possibilities of broader adoption of hierarchical test. Traditionally, DFT insertion and pattern generation efforts occurred only after the device design was complete. Hierarchical DFT lets the majority of DFT insertion and ATPG efforts go into individual blocks or die. Patterns for BIST and ATPG are created for an individual die and then retargeted to the larger 3D package. As a result, very little work is necessary at the 3D package-level design. Also, the DFT logic and patterns for any die can be retargeted to any package in which the die is used. Thus, if the die were used in multiple packages then only one DFT insertion and ATPG effort would be necessary, which would then be retargeted to all the platforms where it is used.

Using a common TAP structure on all die and retargeting die patterns to the 3D package are capabilities that exist today. However, there is another important new test requirement for a 3D stack— the ability to test interconnects between stacked dies. I promote a strategy based on the boundary scan bidirectional cells at all logic die IO, including the TSVs. Boundary scan logic provides a standard mechanism to support die-to-die interconnect tests, along with wafer- and die-level contactless wrap and leakage tests.

To test between the logic die and Wide I/O external memory die, the Wide I/O JEDEC boundary scan register at the memory IO is used. The addition of a special JEDEC controller placed in the logic die and controlled by the TAP lets it interface to the memory. Consequently, a boundary scan-based interconnect test is supported between the logic die and external memory. For at-speed interconnect test, IJTAG patterns can be applied to hierarchical wrapper chains in the logic die, resulting in an at-speed test similar to what is used today for hierarchical test between cores.

Finally, for 3D IC test, you need test and diagnosis of the whole 3D package. Use the embedded DFT resources to maximizes commonalities across tests and facilitate pre- and post-stacking comparisons. To validate the assembled 3D IC, you must follow an ordered test suite that starts with the simplest tests first, as basic defects are more likely to occur than complex ones. It then progressively increases in complexity, assuming the previous tests passed.

Industry-wide, 3D test standards such as P1838, test requirements, and the types of external memories that are used are still in flux. This is one reason I emphasized plug-and-play architecture and flexibility. By structuring the test architecture on IJTAG and existing IJTAG tools, you can adapt and adjust the test in response to changing requirements. I believe that test methodologies that develop for testing 3D ICs will lead to an age of more efficient and effective DFT  overall.

Figure 1. The overall architecture of our 3D IC solution. A test is managed through a TAP structure on the bottom die that can enable the TAPs of the next die in the stack and so on. A JEDEC controller is used to support interconnect test of Wide I/O memory dies.

Figure 1. The overall architecture of our 3D IC solution. A test is managed through a TAP structure on the bottom die that can enable the TAPs of the next die in the stack and so on. A JEDEC controller is used to support interconnect test of Wide I/O memory dies.

More from Mentor Graphics:

Model-based hints: GPS for LFD success

Reducing mask write-time – which strategy is best?

The advantage of a hybrid scan test solution

Ron Press is the technical marketing director of the Silicon Test Solutions products at Mentor Graphics. He has published dozens of papers in the field of test, is a member of the International Test Conference (ITC) Steering Committee, and is a Golden Core member of the IEEE Computer Society, and a Senior Member of IEEE. Press has patents on reduced-pin-count testing and glitch-free clock switching.

North America-based manufacturers of semiconductor equipment posted $1.28 billion in orders worldwide in January 2014 (three-month average basis) and a book-to-bill ratio of 1.04, according to the January EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.04 means that $104 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in January 2014 was $1.28 billion. The bookings figure is 7.2 percent lower than the final December 2013 level of $1.38 billion, and is 19.1 percent higher than the January 2013 order level of $1.08 billion.

The three-month average of worldwide billings in January 2014 was $1.24 billion. The billings figure is 8.3 percent lower than the final December 2013 level of $1.35 billion, and is 27.9 percent higher than the January 2013 billings level of $968.0 million.

“Both bookings and billings are at values higher than reported one year ago and are good indications of growth in the 2014 equipment market,” said Denny McGuirk, president and CEO of SEMI. “Device makers are investing in 20nm technology and advanced device structures, while leading packaging houses focus their investments on flip chip, wafer-level, and 3-D packaging.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
August 2013

1,081.9

1,063.9

0.98
September 2013

1,020.9

992.8

0.97
October 2013

1,071.0

1,124.5

1.05
November 2013

1,113.9

1,238.0

1.11
December 2013 (final)

1,349.7

1,380.8

1.02
January 2014 (prelim)

1,238.0

1,281.9

1.04

Source: SEMI, February 2014
The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the SEMI Equipment Market Data Subscription (EMDS).

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains.

Semiconductor Manufacturing International Corporation, China’s largest and most advanced semiconductor foundry, and Jiangsu Changjiang Electronics Technology Co., Ltd., the largest packaging service provider in China, jointly announced today a joint venture for 12″ bumping and related testing. JCET will also build advanced back-end package production lines nearby. The two parties will use this as a base to jointly set up and develop an IC manufacturing supply chain within China to provide a high-quality, efficient and convenient one-stop-shop service for global customers focusing on the China market.

Bumping is a necessity for wafer yield testing of advanced front-end IC manufacturing technologies, and the basis for the 3D wafer level packaging technology development. With the rapid growth of mobile market in China, and increasing adoption of advanced 40nm and 28nm process technologies, IC chips and their demand for bumping are anticipated to grow rapidly in the next few years

By establishing Bumping and nearby advanced flip-chip packaging capabilities, along with SMIC’s front-end 28nm process technology offerings, the first complete 12″ advanced IC manufacturing local supply chain in China will be formed. This supply chain can greatly reduce the cycle time between FEOL (Front-end of Line) and MEOL (Middle-end of Line) / BEOL (Back-end of Line), and effectively control the intermediate costs. More importantly, it is closer to the end market in China, therefore it can shorten the time to market for fabless customers while focusing on China’s mobile market.

Using this as a foundation, both sides will also strengthen the co-operation in the 3D wafer level packaging field.

“Collaborating with China’s largest packaging service provider meets SMIC’s long-term strategy of cultivating China’s IC ecosystem,” said Dr. Tzu-Yin Chiu, Chief Executive Officer & Executive Director of SMIC. “By jointly cooperating in the bumping line and having JCET’s advanced package process next door, we will be able to provide an one-stop-shop service with mutual benefits, and establish the first 12″ advanced IC manufacturing local supply chain in China. It is a strategic and necessary step for SMIC to take to provide more value-added services to customers.”

“In combination with SMIC’s strong capabilities of front-end wafer manufacturing and technology R&D, and JCET’s experience in core semiconductor packaging technologies, this joint venture has complementary advantages for both sides,” said Mr. Wang Xinchao, Chairman of JCET. “Together, we will devote our efforts to build a supply chain which is the most suitable for meeting customers’ requirements, and to elevate and enhance the level and competitiveness of China’s IC manufacturing eco-system.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled its most advanced 300-mm photoresist processing system for logic and memory high-volume manufacturing (HVM) — the EVG150XT resist coating and developing system.  Leveraging EVG’s XT Frame platform utilized across the spectrum of the company’s industry-leading systems, the EVG150XT is optimized for ultra-high throughput and productivity — bringing the company’s expertise in lithography processing to HVM environments.  The EVG150XT is designed for processing resists, spin-on dielectrics and thick films for mid-end-of-line (MEOL) and back-end-of-line (BEOL) semiconductor applications, including through silicon via (TSV) formation, wafer bumping, redistribution layer and interposer manufacturing for 2.5 and 3D-IC packaging.

As 2.5/3D packaging moves closer to production reality in the semiconductor industry in order to integrate increasing amounts of chip functionality in smaller form factors for mobile devices and other consumer electronic products, new manufacturing and cost requirements must be addressed across the wafer fabrication process—particularly in the MEOL and BEOL segments.  Smaller pitches, copper pillars, the formation of redistribution layers to enable chip-to-chip connections utilizing under bump metallization, and the connection of dies produced with different design-node processes, have led to tighter standards in process uniformity.  As the industry ramps to volume production on these devices, the wafer processing equipment used to manufacture these devices will require both enhanced throughput and processing capabilities.

The EVG150XT features nine process modules that can operate simultaneously for multi-parallel wafer processing.  Smart scheduling software for throughput-optimized handling sequences has also been incorporated, along with pumps and dispense systems tailored for thick film applications.  In addition, an in-line metrology module has been integrated into the EVG150XT that can detect a variety of process irregularities and defects to enable real-time process corrections to reduce defects, increase yields and lower production costs.  These and other software and hardware enhancements optimize the EVG150XT for high-volume manufacturing environments.

“For the past 30 years, EV Group has built up significant process know-how in both lithography and HVM processing working closely with our customers and turning their feedback into new capabilities built into our next-generation products.  With our latest product introduction — the EVG150XT — we’ve successfully combined both areas of expertise to provide our customers with the industry’s first true HVM resist processing system that can meet their most demanding requirements for mid-end and back-end-of-line applications,” stated Paul Lindner, executive technology director at EV Group.

Media and analysts interested in learning more about EVG’s latest developments in photoresist and lithography processing, as well as other high-volume manufacturing solutions, are invited to visit the company’s booth #1264 in Hall C at the COEX Convention and Exhibitor Center in Seoul, Korea at the SEMICON Korea show on February 12-14.

By Dr. Phil Garrou, Contributing Editor

SEMI’s second annual European 3D TSV Summit was held in Grenoble in late January. 320 attendees met to discuss the status of 2.5/3DIC and other advanced packaging technologies.

Mark Stromberg, principle analyst for Gartner, projects TSV wafer production will be > 500K 300mm equiv wafers/month or > 750MM units / yr by 2016, with a CAGR between 2013 – 2018 of 107%. By 2016 they are predicting theTSV equipment market will approach $1B.  They are also predicting that similar to the lower transistor nodes, only top tier IDM/Foundries/OSATS will participate due to the significant capex requirements.

GlobalFoundries (GF) has been detailing their imminent commercialization of 2.5/3D IC for several years. Michael Thiele, Sr. section manager for packaging reported that Rev 0.5 of their design manual and process design kit would be ready in Mach of this year with Rev 1.0 coming out in the 3Q.   The proposed GF supply chain is shown below:

GF

Miekei Leong, VP of TSMC reported on their plans to validate high bandwidth memory (HBM) on their chip-on-wafer-on substrate ,CoWoS interposer  technology by 4Q 2014 and details on vertical stacking of memory on 28nm logic.

Eric Beyne of IMEC took a look at the cost breakdown for wafer level 3D integration for a fully loaded balanced line producing 5x 50um TSV.

beyne

By Zvi Or-Bach, President and CEO of MonolithIC

A recent SEMI report titled SEMI Reports Shift in Semiconductor Capacity and Equipment Spending Trends reveals an important new trend in semiconductors: “spending trends for the semiconductor industry have changed. Before 2009, capacity expansion corresponded closely to fab equipment spending.  Now more money is spent on upgrading existing facilities, while new capacity additions are occurring at a lower pace, to levels previously seen only during an economic or industry-wide slowdown”.

Looking at the semi-equipment booking should be the first step in any attempt to assess future semiconductor trends. While talking is easy, spending billions of dollars is not. Vendors look deeply into their new design bookings and their future production needs before committing new dollars to long lead purchases for their manufacturing future needs. In the past decade it was relatively simple, as soon as a new process node reached production maturity vendors would place new equipment orders knowing that soon enough all new designs and their volume will shift to the new process node. But the SEMI report seems to tell us that we are facing a new reality in the semiconductor industry – a Paradigm Shift.

A while ago VLSI Research Inc. released the following chart with the question: Is Moore’s Law slowing down?

Zvi1Jan27

The chart above indicates a coming change in the industry dynamic, and 2013 might be the year that this turns out to be a Paradigm Shift.

 Just few weeks ago at the SEMI ISS conference, Handel Jones of IBS presented many very illuminating charts and forecasts. The following chart might be the most important of them and it is the revised calculation of per gate cost with scaling.

 Zvi2Jan27

Clearly the chart reveals an unmistakable Paradigm Shift as 28nm is the last node for which dimensional scaling provides a per gate cost reduction. It makes prefect sense for the vendors and their leading edge customers to respond accordingly. Hence it easy to understand why more equipment is being bought to support 28nm and older nodes.

The following table, also from Jones, illustrates this new reality.

 Zvi3Jan27

In the equipment business, more than 50% of demand comes from the memory segment where the dollars per sold wafer are much lower than in logic. It seems that the shift there has already taken place. Quoting Randhir Thakur, Executive Vice President, General Manager, Silicon Systems Group, Applied Materials, Inc -as was recently published in The shift to materials-enabled 3D: ” our foundry/logic and memory customers that manufacture semiconductors are migrating from lithography-enabled 2D transistors and 2D NAND to materials-enabled 3D transistors and 3D NAND”…”Another exciting inflection in 2014 is our memory customers’ transition from planar two-dimensional NAND to vertical three-dimensional NAND. 3D technology holds the promise of terabit-era capacity and lower costs by enabling denser device packing, the most fundamental requirement for memory”. Which fits nicely with the following illustration made by Samsung as part of their 3D-NAND marketing campaign.

Zvi4Jan27

As for the logic segment, the 3D option is yet to happen. But as we wrote in respect to 2013 IEDM – More Momentum Builds for Monolithic 3D ICs.

The following chart from CEA Leti illustrates the interest for monolithic 3D-

 Zvi5Jan27

 It should be noted that monolithic 3D technology for logic is far behind in comparison to memory. Given that the current issues with dimensional scaling are clearly only going to get worse, we should hope that an acceleration of the effort for logic monolithic 3D will take place soon. In his invited paper at IEDM 2013, Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is the most effective path for the semiconductor future: “Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” As illustrated by his Fig. 17 below.

 Zvi6Jan27

So, in conclusion, our industry is now going thru a paradigm shift. Monolithic 3D is shaping up as one of the technologies that would revive and sustain the historically enjoyed growth and improvements well into the future. The 2014 S3S conference scheduled for October 6-9, 2014 at the Westin San Francisco Airport will provide both educational opportunities and cutting edge research in monolithic 3D and other supporting domains. Please mark your calendar for this opportunity to contribute and learn about the new and exciting monolithic 3D technology.

Compiled by Pete Singer, Editor-in-Chief; Edited by Shannon Davis, Web Editor

Internet of Things

We asked leading industry experts and analysts to give us their perspectives on what we can expect in 2014. All expect it to be a banner year for the semiconductor industry, as the world’s demand for electronics continues unabated. However, most believe we are seeing an era of unprecedented change, driven by a shift to mobile computing, the Internet of Things, higher wafer costs and difficult technical challenges. To address these challenges, new levels of innovation and collaboration will be needed.

Click to launch slideshow

Dr. Phil Garrou, Contributing Editor

At the recent Georgia Tech Global Interposer Technology (GIT) Workshop in Atlanta, the pervasive theme appeared to be whether a change in substrate is required to lower overall costs and help drive HVM (high volume manufacturing) applications. Certainly conference chair Rao Tummala, industry visionary whose name is synonomous with microelectronic packaging, feels the time is right to take a serious look at glass interposers both for their superior electrical performance and their promise of lower costs. The PB substrate manufacturers are also taking a serious look at this market and proposing that they can drive their technology to the required dimensions and electrical performance, though many skeptics (including me) are taking a “show me” attitude about these claims.

The Yole Developpement presentation pointed out that while 2.5D silicon interposer technology was fully underway at TSMC and GLOBALFOUNDRIES, UMC and SPIL supposedly are near initiation, all of the rumored “driver applications,” like the Apple A7, the next gen Qualcomm phone, the Sony PS4, ST Micro’s “Wioming” application processor, wide IO memory and the next generation Altera FPGA (see discussion below) have been, at the very least, postponed. While no one would openly reveal what the current and proposed future costs are, it is believed that all of these postponements are due to cost which certainly is not yet meeting the mobile phone requirements of less than 1 cent per sq mm proposed by Qualcomm’s Matt Nowak (i.e., this is roughly $550 for a 300mm wafer of interposers).

While Yole has identified at least 10 products moving towards commercialization, all of them currently require so called high density interposers (i.e. 1 µ m L/S and as small as 10 µ m TSV). Currently these dimensions can only be fabricated using front end dual damascene type processing available only at silicon foundries and more recently the OSAT, SPIL.

While Yole is still projecting a greater than $1B in revenue from 2.5D TSV activity by 2017 (activity revenues including TSV etching, filling, RDL, bumping, wafer test & wafer level assembly), these projections only hold if the current “postponed applications” are quickly commercialized.

During the Amkor presentation Ron Huemoeller indicated that lowering cost could come from elimination of backside RDL on the interposers by arranging pin out on the top side high density interconnect.

Huemoeller sees high end applications being dominated by silicon, mid end applications like graphics possibly using glass and the low end applications (yet unidentified) being wide open. He sees GPU + HBM (high bandwidth memory) being adopted in 2015 and tablets and processors adopting interposer solutions the following year.

In terms of organic “interposers” he indicates that Shinko and Semco are in limited sampling of 2/2 (L/S) and Kyocera 5/5. He labels Unimicron as in “early development.”

After making the standard argument that 2.5/3DIC was needed to combat the costs of continued scaling and that system level cost savings could pay for interposer costs, Dave McCann of GLOBALFOUNDRIES indicated that GF was achieving near 100% yields with reticle sized interposers having 4 layers of high density interconnect.

McCann predicted we would see voltage regulator function on future interposers. He also described a program between Global (chip and silicon interposer), Open-Silicon (design), Cadence (EDA tools) and Amkor (assembly and test), which produced a functional processor vehicle featuring two 28nm ARM Cortex-A9 processors connected on a 2.5D silicon interposer built on a 65nm manufacturing flow. The program demonstrated first-time functionality of the processor, interposer, substrate and the die-to-substrate assembly process. The design tools, process design kit (PDK), design rules, and supply chain are now in place for other activities.

Inherently most believe that all things being equal, glass should be a lower cost interposer solution since it can be processed in large format. However, one interesting question from the audience was “Why are silicon and glass wafer the same price?”

Although the data from experts like Professor Kim from KAIST confirms that glass is a better electrical performance solution, especially for RF applications, the major issue is that a complete infrastructure is not yet in place to manufacture such glass interposers. •

ANDREW HO, Global Industry Director, Advanced Semiconductor Materials, Dow Corning, Hong Kong.

New technology eliminates the need for specialized equipment for wafer pre- or post-treatment.

Advances in three-dimensional (3D) through-silicon via (TSV) semiconductor technology promise to significantly improve the form factor, bandwidth and functionality of microelectronic devices by enabling once-horizontal chip structures to be fabricated as vertical architectures. The challenges to implementing 3D-IC TSV integration are not trivial, and the search for a solution has prompted exploration of several schemes. These are frequently labeled as via-first, via-middle or via-last depending on the position where the 3D TSV fabrication takes place.

3D_1
Figure 1: A thing silicon wafer on diving frame after successful debonding from a silicon carrier wafer at imec, using Dow Corning’s silicon-based temporary bonding solution. Image courtesy of and copyright owned by imec

In via-first integration, TSVs are formed before processing the front-end-of the line (FEOL) layers, which enables high thermal budget processing for TSV insulation and filling. In via-middle schemes, TSVs are added between FEOL and back-end-of-the-line (BEOL) stacking to allow several copper-based interconnections. In a via-last approach, fabrication of TSVs occurs after completion of FEOL and BEOL processing, either from a wafer’s front or back side. This approach generally addresses applications in which low density 3D interconnections are adequate.

In all these approaches, however, TSV fabrication is problematic without thinning the active silicon wafer down to 50µm or less (FIGURE 1) – about half the thickness of a standard piece of printer paper – and therein lies the challenge. In order to handle such ultra-thin wafers, the industry requires solutions that can easily, cost-effectively and temporarily bond and debond active wafers to carrier wafer systems for subsequent wafer thinning and TSV fabrication.

Temporary bonding solutions: A primer

Wafer thinning is already widely applied for IC manufacturing, as well as the manufacture of power devices and image sensors. Depending on process requirements and applications, wafer bonding can be divided into several techniques including direct bonding, anodic bonding and thermo-compression adhesive bonding and others. For 3D-IC integration, however, the most commonly explored approach is attaching device wafers to a carrier wafer for support with the use of polymer-based temporary adhesives. As shown in FIGURE 2 A typical process flow for the use of such temporary bonding solutions first applies a release and an adhesive layer, either on the device or the carrier wafer. After this the device and carrier wafers are bonded together. Subsequent steps, in sequence, involve wafer thinning, TSV reveal or fabrication, formation of redistribution layers and wafer interconnect fabrication, debonding and cleaning of the processed ultra-thin device wafer and, lastly, 3D stacking of the thinned device wafers.

3D_2
Figure 2: A typical process flow for temporary bonding and debonding solutions.

Central to the success of this approach is the polymer adhesive, which must protect the ultra-thin wafer while withstanding the harsh chemicals and thermal stresses imposed by wafer thinning and 3D-IC TSV integration processes. Specifically, temporary bonding/debonding (TB/D) solutions must demonstrate excellent thermal and chemical stability to withstand the plasma processes as well as the solvents, bases and acids used by 3D-IC TSV processes. In addition to delivering excellent adhesive properties to withstand the mechanical stress of the wafer thinning process, temporary adhesives must also be able to maintain global high uniformity of the adhesive layer as characterized by a low total thickness variation (TTV) across the device wafer through all processing steps to reach a typical target of 2 µm TTV on the thin device wafer (FIGURE 3). In addition, these materials must enable low-temperature debonding compatible with different interconnect technologies using solder bumps or copper pillars, and offer a simple wafer cleaning process that will damage neither the underlying layers of the processed device wafer nor the tape on which the thinned wafer stands after debonding.

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Figure 3: Measurements of a temporarily bonded active water (post-thinning) show total thickness variation to be approximately 4µm.

The potential of polymer-based TB/D solutions has prompted exploration of several material technologies coupled with various equipment platforms and wafer treatments. As development of these and other TB/D solutions advance, 3D-IC TSV integration has yet to become a mainstream technology due to its additional costs and challenges on thin wafer handling. These costs derive not only from the sophisticated materials used, but also the multiple pre-treatment steps that temporary bonding and debonding processes have traditionally required. While these painstaking steps help to ensure high yields and protect the high value of fully functional device wafers, they also hinder 3D-IC TSV integration from moving to volume production and, ultimately, they contribute to a higher total cost of ownership.

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Figure 4: Wafers spin-coated with the temporary adhesive and then cured tested the materials chemical resistance by soaking it in phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. The temporary bonding material showed negligible weight loss or gain for all chosen chemicals.

Minimizing total cost of ownership is essential for all semiconductor manufacturing applications. But it is a critical enabler for next-generation technologies, such as 3D-IC TSV integration. Recent innovations by Dow Corning and industry collaborators have shown promising development of a simpler, more cost-effective temporary bonding solution based on silicone adhesive and release layers. Importantly, this new solution enables room-temperature bonding and room-temperature mechanical debonding of active and carrier wafers using conventional, high-volume manufacturing methods.

A new bilayer temporary bonding/debonding concept

At the center of this new approach is a simple bilayer concept based on two silicone materials that serve as the temporary bonding materials during the fabrication of thin wafers for 3D-IC TSV integration. It applies a process flow that greatly simplifies the temporary bonding/debonding process, and reduces costs associated with special equipment for pre- or post-process treatments of the device wafer such as plasma, ultra-violet, preferential zone treatment and others.

The first step in the process flow is the spin coat of the temporary bonding materials. This step is critical to minimizing delays in process time, as the total thickness variation (TTV) of the spin coated material can contribute to the TTV of the bonded pair and, later, transfer to the thin wafer during the wafer thinning and post processing of bonded wafer pairs. Thus it is important to start with a low TTV for spin coated films. Notably, the process described here targets TTV for coatings on the device wafer to a range of within 1 percent.

The spin coat step first applies a continuous release layer onto the front side of the device wafer, ensuring the layer entirely covers any micro-structures present. Next, comes spin coat application of a silicone-based adhesive layer of a few tens of microns in thickness – depending on the device wafer’s topography – on top of the release layer. The adhesive layer developed for this process is designed to obtain excellent uniformity and planarization over high bump topographies. It allows single-layer thicknesses between 10 and 110 µm to provide process simplicity.

After application of both layers, the device and carrier wafer are bonded. The carrier wafer can be either silicon or glass, and it does not require any particular pre-processing. Prior to the bonding step, application of vacuum assures no air bubbles are trapped in the adhesive, which is viscous. After degassing, the carrier is dropped onto the device wafer.

Importantly, bonding occurs at room temperature, which greatly improves the opportunity for increased throughput. Also, the silicone-based adhesive is still in its wet state at this point. So, no force is required to bond the pair. Thus, this technology offers the potential to accommodate fragile ultra-low dielectric constant materials used within advanced copper interconnects that are very sensitive to the application of force. The total time for this step takes a couple of minutes, followed by a post-bonding bake on a hotplate – typically at 150° C for a few more minutes – to cure the adhesive layer.

Wafer processing now proceeds with backgrinding and associated process control. Following post-bonding, the bonded pair is mechanically debonded at room temperature along the release to adhesive layer interface. The thinned device wafer remains on a tape on a frame, available for release layer cleaning followed by dicing, pick-and-place and stacking steps. The carrier wafer, still covered with adhesive, is processed for chemical recycling.

Able to withstand real-world processes

Candidate TB/D materials must deliver excellent thermal stability to ensure that the bond remains strong during the various processing steps involved in the copper nail reveal step and formation of redistribution layers on the device wafer. It is also critical that candidate materials do not outgas during post-bond processing, as this can lead to voids or delamination that, ultimately, can contribute to device failures.

Thermal analysis of both the release and adhesive materials used in this new approach heated the thinned bonded pair to 200° C on a hot plate in air for 20 minutes; and then to 200° C in air for three hours, where it passed solder bump reflow conditions at 260° C for 10 minutes; and finally to 200° C for three hours under vacuum. Scanning acoustic microscopy analysis after each test showed no voids or delamination.

These results underscore that both TB/D materials developed for the approach described above can not only hold up under the rigors of conventional backgrinding processes, they can also deliver the thermal stability necessary to withstand the plasma processes applied to the wafer pair during the fabrication of 3D-IC TSV architectures.

Strong chemical resistance is also critical for candidate TB/D materials to ensure they can perform reliably without delaminating or swelling when exposed to the several wet processes that thinned wafers undergo. Testing of the release and adhesive layer materials began by spin coating a wafer with the temporary adhesive, curing it using described protocols and then soaking it in phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. The temporary bonding material showed negligible weight loss or gain for all chosen chemicals (FIGURE 4).

One of the most important enablers of broader adoption of TB/D solutions is the ability to debond thinned device wafers from carrier wafers, and clean any residues from the device wafer without adversely affecting device yields. The new bilayer TB/D concept described above leverages a room-¬temperature peel debond, and has been demonstrated on several conventional, commercially available debonding platforms from leading equipment providers.

The process begins by first mounting the thinned wafer pair onto a dicing tape and holding it in place on a vacuum chuck while peeling off the thick carrier wafer. Because the solvent dissolvable release layer is applied to the thin device wafer with dicing tape exposed, no harsh silicone removers or other strong acids need be applied. The entire debond process takes less than five minutes, including clean-up of the device wafer.

Conclusion

While TB/D materials and equipment continue to evolve in sophistication, broader adoption of this technology and the 3D-IC TSV integration that it enables cannot advance at the expense of simple processing, device yields or total cost of ownership. The emergence of Dow Corning’s simple, bilayer TB/D bonding solution achieves all these goals by eliminating the need for specialized equipment for wafer pre- or post-treatment.

Comprising an adhesive and release layer, the technology has demonstrated excellent spin coating and room temperature bonding performance with low TTV, even for very thick layers up to 110 µm. Proven on commercially available high-volume production equipment, it has shown excellent chemical stability when exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. In addition, the bonding solution and paired wafers showed good thermal stability when exposed to the 300° C temperatures common to post-bonding 3D TSV processes. •

ANDREW HO is the Global Industry Director, Advanced Semiconductor Materials, Dow Corning. E-mail: [email protected].