Category Archives: 3D Integration

The discovery of what is essentially a 3D version of graphene – the 2D sheets of carbon through which electrons race at many times the speed at which they move through silicon – promises exciting new things to come for the high-tech industry, including much faster transistors and far more compact hard drives. A collaboration of researchers at the U.S Department of Energy (DOE)’s Lawrence Berkeley National Laboratory (Berkeley Lab) has discovered that sodium bismuthide can exist as a form of quantum matter called a three-dimensional topological Dirac semi-metal (3DTDS). This is the first experimental confirmation of 3D Dirac fermions in the interior or bulk of a material, a novel state that was only recently proposed by theorists.

“A 3DTDS is a natural three-dimensional counterpart to graphene with similar or even better electron mobility and velocity,” says Yulin Chen, a physicist from the University of Oxford who led this study working with Berkeley Lab’s Advanced Light Source (ALS) . “Because of its 3D Dirac fermions in the bulk, a 3DTDS also features intriguing non-saturating linear magnetoresistance that can be orders of magnitude higher than the materials now used in hard drives, and it opens the door to more efficient optical sensors.”

Chen is the corresponding author of a paper in Science reporting the discovery. The paper is titled “Discovery of a Three-dimensional Topological Dirac Semimetal, Na3Bi.” Co-authors were Zhongkai Liu, Bo Zhou, Yi Zhang, Zhijun Wang, Hongming Weng, Dharmalingam Prabhakaran, Sung-Kwan Mo, Zhi-Xun Shen, Zhong Fang, Xi Dai and Zahid Hussain.

Two of the most exciting new materials in the world of high technology today are graphene and topological insulators, crystalline materials that are electrically insulating in the bulk but conducting on the surface. Both feature 2D Dirac fermions (fermions that aren’t their own antiparticle), which give rise to extraordinary and highly coveted physical properties. Topological insulators also possess a unique electronic structure, in which bulk electrons behave like those in an insulator while surface electrons behave like those in graphene.

“The swift development of graphene and topological insulators has raised questions as to whether there are 3D counterparts and other materials with unusual topology in their electronic structure,” says Chen. “Our discovery answers both questions. In the sodium bismuthide we studied, the bulk conduction and valence bands touch only at discrete points and disperse linearly along all three momentum directions to form bulk 3D Dirac fermions. Furthermore, the topology of a 3DTSD electronic structure is also as unique as those of topological insulators.”

The discovery was made at the Advanced Light Source (ALS), a DOE national user facility housed at Berkeley Lab, using beamline 10.0.1, which is optimized for electron structure studies. The collaborating research team first developed a special procedure to properly synthesize and transport the sodium bismuthide, a semi-metal compound identified as a strong 3DTDS candidate by co-authors Fang and Dai, theorists with the Chinese Academy of Sciences.

At ALS beamline 10.0.1, the collaborators determined the electronic structure of their material using Angle-Resolved Photoemission Spectroscopy (ARPES), in which x-rays striking a material surface or interface cause the photoemission of electrons at angles and kinetic energies that can be measured to obtain a detailed electronic spectrum.

“ALS beamline 10.0.1 is perfect for exploring new materials, as it has a unique capability whereby the analyzer is moved rather than the sample for the ARPES measurement scans,” Chen says. “This made our work much easier as the cleaved sample surface of our material sometimes has multiple facets, which makes the rotating-sample measurement schemes typically employed for ARPES  measurements difficult to carry out.”

Sodium bismuthide is too unstable to be used in devices without proper packaging, but it triggers the exploration for the development of other 3DTDS materials more suitable for everyday devices, a search that is already underway. Sodium bismuthide can also be used to demonstrate potential applications of 3DTDS systems, which offer some distinct advantages over graphene.

“A 3DTDS system could provide a significant improvement in efficiency in many applications over graphene because of its 3D volume,” Chen says. “Also, preparing large-size atomically thin single domain graphene films is still a challenge. It could be easier to fabricate graphene-type devices for a wider range of applications from 3DTDS systems.”

In addition, Chen says, a 3DTDS system also opens the door to other novel physical properties, such as giant diamagnetism that diverges when energy approaches the 3D Dirac point, quantum magnetoresistance in the bulk, unique Landau level structures under strong magnetic fields, and oscillating quantum spin Hall effects. All of these novel properties can be a boon for future electronic technologies. Future 3DTDS systems can also serve as an ideal platform for applications in spintronics.

This research was supported by the DOE Office of Science and by the National Science Foundation of China.

Today, at the SEMI European 3D TSV Summit, nanoelectronics research center imec and Besi, a global equipment supplier for the semiconductor and electronics industries, announced they are joining forces to develop a thermocompression bonding solution for narrow-pitch die-to-die and die-to-wafer bonding with high accuracy and high throughput. Through this collaboration, imec and Besi will pave the way to industrial adoption of thermocompression bonding for 3D IC manufacturing.

3D IC technology, stacking multiple dies into a single device, aims to increase the functionality and performance of next-generation integrated circuits while reducing footprint and power consumption. It is a key technology to enable the next generation of portable electronics, such as smartphones and tablets, which require smaller ICs that consume less power.

One of the key challenges to making 3D IC manufacturing a reality is the development of high-throughput automated process flow for narrow-pitch, high-accuracy die-to-die and die-to-wafer bonding. Flip chip and reflow soldering, which are currently combined for bonding, require lenient bonding accuracy on large bump pitches (around 150-50µm bump pitch). Bump pitches need to further scale down to 40-10 µm to realize a sufficiently high performance. This needs high accuracy in bonding within the range of 1-2um @3sigma. Moreover, an automatic process flow is essential for industrial adoption. Thermocompression bonding is a method that enables this high bonding accuracy on narrow bump pitches, although with this comes long cycle times due to temperature and pressure profiles and processing methods which hinder industrial adoption of this technology up to now.

Imec and Besi will conduct joint research to develop a high-throughput thermocompression bonder in an automated process flow, with high accuracy and shorter cycle times, paving the way to enabling a manufacturable 3D, 2.5D and 2.5D/3D hybrid technology.

“We are excited to work with a key research center such as imec and leverage its expertise in fine pitch bonding materials and processes to increase the yield and reliability of our equipment ,” said Richard Blickman, CEO at Besi. “This collaboration will enable us to benchmark our Chameo tool to meet the industrial needs of the semiconductor industry, offering our customers a viable and effective solution for 2.5D/3D IC manufacturing.”

Intel vs. TSMC: An Update


January 21, 2014

By Zvi Or-Bach, President and CEO of MonolithIC 3D

On January 14, 2014 we read on the Investors.com headlines page – Intel Seen Gaining Huge Pricing Advantage Over TSMC. Just three days later comes the responding headline: TSMC: We’re “Far Superior” to Intel and Samsung as a Partner Fab.

These kinds of headlines are not seen too often in the semiconductor business domain and it is not clear what the objectives are for such. It will be hard to believe that this is an attempt to manipulate the investor community, yet there are only a handful of super high volume design wins that are driving the leading edge devices, and for those wins the fight should be taking place in the ‘board’ room. So, let’s dive a bit into the details behind these headlines.

The first headline relates to Jefferies analyst Mark Lipaci releasing an analysis report stating: “Intel will have a die size and transistor cost advantage over Taiwan Semiconductor (TSM) for the first time by fourth-quarter 2014, which could lead to a 50% pricing advantage in processors in 12 months, and a 66% pricing advantage in 36 months.” We can find more information in the blog titled: Intel: Primed for Major Phone, Tablet Share on Cheaper Transistors, Says Jefferies. Quoting Lipaci: “At the same time that Intel has started focusing on computing devices in mobile form factors, it appears that TSMC is hitting a wall on the transistor cost curve. The chart below was presented by TSMC’s CTO. We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC for the first time ever in 4Q14. We believe Intel extends that cost lead 24 months after than in 2016.”

Lipaci then used the following chart to illustrate the build up of Intel advantage vs. TSMC.

Chart 1

The Jefferies report goes further and provides the following charts for 14nm and 10nm.

Chart 2 Chart 3

Clearly, the primary advantage that the report is pointing out is the lack of the double margin associated with the foundry model vs. the IDM model. It seems that this argument has clearly been disproven by now. In the early days of the foundry industry most IDMs would argue that the foundry model would not work because of the double margin aspect – the foundry would need about 50% gross margin and then the fables company would need an additional 50% gross margin – which would make it completely uncompetitive vs. the IDM. Twenty years later it was proven, again, that there is no “free lunch.” The chip fabrication business needs a margin to be sustainable and the design business needs a margin to be sustainable. And the better business model is to have those managed by different companies as each could build excellence in its own value proposition. Intel did enjoy for many years effective exclusivity in the Windows based processors. Intel has not been able so far to show much success in mobile or any other non-Windows market. Since Intel is now trying to position themselves as a better foundry than TSMC, then clearly for their potential foundry customers this double margin argument is moot.

The charts above also compare Intel’s cost advantage vs. TSMC older nodes (Intel’s 14nm vs. TSMC’s 20 nm and Intel’s 10nm vs. TSMC’s 16nm). It is not clear that Intel is so far ahead. Intel 14nm had been delayed to the first quarter of 2014 and TSMC has committed to be in volume production in the later part of 2014. But the real competition is on the ability to bring fabless companies to volume using one’s advanced process node. Key to this is the availability of libraries, EDA full tool set support, and major IP such as ARM processors. It is far from being clear that Intel is really far ahead of TSMC in this critical area. And then, these days it is not so clear that using a more advanced process node buys one an end-device cost advantage. In fact, the foundries have already made it clear that beyond the 28nm node they do not see cost reduction, due to the extra cost associated with advanced node lithography and other issues. Even Intel admitted at their latest analyst day that advanced nodes are associated with escalating depreciation and other costs, as illustrated by the following Intel chart – see the left most graph.

Chart 4

We should note that the Y axes of these graphs are logarithmic which indicate a significant increase of deprecation costs. However, Intel claims it will more than neutralize this increase of costs by accelerating the dimensional scaling when going to 14nm and 10nm, as is presented with the middle graph above. This would lead to an overall sustaining of the historical cost per transistor reduction as is illustrated by the rightmost graph above. Note: the asterisk (*) on those graphs indicates that numbers relating to 14nm and 10nm are forecasts only. Since Intel is committed to be in volume production at the 14nm node any day now, the number associated with 14nm should not be a forecast anymore and we hope to see them released soon.

The simple indication of technology node effective transistor density these days would be the bit cell size. As we have presented many times before, modern SoC device area is dominated by the embedded 6T SRAM. At IEDM 2013, TSMC made public their 6T SRAM bit cell area for 16nm: 0.07 sq. micron. We could not find any Intel public release for their 14nm 6T SRAM bit cell size. We did find an Intel chart for older nodes. This 6T bit cell size chart was presented at IDF2012:

Chart 5

Accordingly, the 14nm node 6T SRAM size for conventional dimensional scaling should be 0.092 * (14/22)² = 0.037 sq. micron. And if Intel can really scale more aggressively to compensate for the extra capital costs then their 6T SRAM at 14nm should be about 0.03 sq. micron or even smaller. As we don’t have any official number we could wait until their early production devices of the 14nm node get analyzed or to the eventual release of their number. But short of an official number, we did find a 2013 presentation from the TRAMS project, of which Intel is a partner, as illustrated in the following charts:

Chart 6 Chart 7

It is now clear that EUV will not be available for the 14nm node, and accordingly the bit cell size from the chart above is 0.062 sq. micron. This is a bit better than that of TSMC but a far cry from 0.03 sq. micron.

If Intel does have a really good number, it would be reasonable to expect that they will make it public soon, to entice the high volume fabless companies such as Qualcomm and Apple to explore Intel’s foundry option.

As for the Jefferies analyst assertion “We believe that due to Intel’s larger R&D budget, its recent focus on the mobile/tablet market, and its higher R&D spend relative to TSMC, that it will produce a lower cost transistor than TSMC”, it is not clear if Intel’s R&D budget is truly larger. TSMC’s R&D budget is dedicated to the foundry side of the business while Qualcomm, Apple, ARM and many other fabless vendors R&D budgets support the design part of any new product release. The total ecosystem behind TSMC and ARM is clearly not smaller than that of Intel. In this month’s SEMI ISS Conference, IC Insights provided very interesting numbers regarding the record of 2013 as was reported in a blog titled: Is Intel the Concorde of Semiconductor Companies?

Top 10 CAPEX Spenders in 2013:

  1. Samsung $12B
  2. TSMC $11.2B
  3. Intel $10.5B
  4. GF $5.5B
  5. SK Hynix $3.7B
  6. Micron $3B
  7. Toshiba $2.9B
  8. UMC $1.5B
  9. Infineon $880M
  10. 10.ASE (OSAT) $770M

Yes, Samsung and TSMC both outspent Intel. Just wait until you see the capacity numbers and you will know why.

Top 10 IC Wafer Capacity Leaders in 2013:

  1. Samsung 12.6%
  2. TSMC 10%
  3. Micron 9.3%
  4. Toshiba 8%
  5. SK Hynix 7%
  6. Intel 6.5%
  7. ST 3.5%
  8. UMC 3.5%
  9. GF 3.3%

10.TI 3.0%

Clearly, Intel is not larger than TSMC as a foundry and it is not clear why would it have a sustainable per transistor cost advantage.

Cost is important but it is far from being the only parameter when choosing a foundry partner. Selecting a foundry partner is truly selecting a partner. The design of leading edge devices is a very costly and lengthy effort, and has a pivotal effect on the business success for the fabless customer. TSMC had built trustful relationships for many years with its fabless customers. It is not clear how easy it is going to be for Intel to become a trustful foundry partner. So far it seems that Intel is still a proud IDM that insists that its customer will support its branding like the “Intel Inside” campaign or the recent announcement of Branding the cloud: Intel puts its stamp on cloud services across the globe. Intel’s repeating emphasis of their transistor cost advantage vs. that of TSMC suggests that Intel considers TSMC as their main competition for the mobile and tablet business. But then their consistent offering of SoC products for the space, as illustrated by the recent Intel chart below, and the Jefferies’ cost analysis above, suggests that Intel is actually an IDM competing with the likes of Qualcomm in this space. It may create concerns in the minds of potential fables customers.

Chart 8

And as a final note, we don’t know how much better the Intel process at 14nm and 10nm is vs. that of TSMC. We do know that when we ask someone for directions, if he says ‘make a right turn’ but with his hand he is pointing left, we should go ahead and turn left. So along with all of these confusing statements we learned just this week that Intel Cancels Fab 42, which was supposed to be the most advanced large capacity fab effort of Intel. I wonder if it should be considered as the hand pointing….

The market for 3DICs globally is forecast to reach USD 7.52 billion by 2019, according to a new market report published by transparency market research. The market growth is expected to be driven by increased demand for devices with exceptional speed, low power consumption, smaller chip size, and reduced response time. Information and communication technology (ICT) and consumer electronics are seen as emerging sectors for adoption of 3DICs and are expected to support the market growth during the forecast period 2013 – 2019.

Globally, 3DICs market was valued at USD 2.40 billion in 2012 and is forecast to grow at 18.1 percent CAGR from 2013 – 2019. Different end-use industry sectors such as consumer electronics, ICT, transport (automotive and aerospace), military and others (biomedical applications and R&D), are getting benefitted by 3DIC integration technology. The global 3DICs market in 2012 was dominated by the ICT sector, which accounted for 24.2 percent revenue share. The bandwidth requirement for high performance networking equipment and storage capacity of devices rises in every new generation. So, to address bandwidth and memory challenges, the emerging ICT sector is expected to adopt 3DIC integration technology for its high chip density and high bandwidth advantages. SOI (silicon-on-insulator) wafers are widely preferred for 3DIC fabrication as it reduces unwanted heat production and parasitic capacitance.

Various industry products such as MEMS and sensors, optoelectronics and imaging, RF SiP, memories, logic (3D SiP/SoC) and HB LED are expected to deploy 3DIC integration. Among these products MEMS and sensor, logic (3D SiP/SoC) and memories (3D Stacks) together accounted for approximately 67.6 percent of market revenue share in 2012. Continuous demand for devices with less expensive storage and higher capacity are the key factors for driving NAND and DRAM memory market. With the increasing demand for consumer electronic products, sales of image sensor and MEMS devices are estimated to grow in the forecast period. This in turn is expected to support adoption of 3D ICs in various devices. Geographically, Asia Pacific is expected to remain largest market for 3D IC technology due to the emerging ICT and consumer electronics sector in this region. Asia Pacific’s revenue share in 2012 was 40.7 percent.

Driven by emerging opportunities and high growth potential, various players from semiconductors and packaging are entering 3D IC integration space, making the competition intense. Among these, players such as Taiwan Semiconductor Manufacturing Company Ltd. (TSMC), Xilinx Inc., Samsung Electronics Co. Ltd., have dominant position in the market, collectively accounting for more than 54.5% of the market in 2012, with TSMC being the leader. New entrants are expected to face stiff competition from existing players, and will have to focus on high investments on R&D and comprehensive ecosystem for IC integration and testing so as to sustain growth in the long run. Other vendors in the market are: 3M Company, Micron Technology Inc., (Elpida Memory Inc.), Ziptronix, Inc., MonolithIC 3D Inc., Tezzaron Semiconductor, STATS ChipPAC Ltd. and United Microelectronics Corporation (UMC) among others.

SEMI today announced that two teams — from the University of Florida and Xilinx — are recipients of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer and the University of Florida team was recognized for developing a cornerstone of the modern era of computational modeling of CMOS fabrication process with the Florida Object-Oriented Process Simulator, FLOOPS.  Liam Madden  accepted the award on behalf of the Xilinx team, and Mark Law and Kevin Jones (University of Florida) accepted their awards during a banquet at the 2014 SEMI Industry Strategy Symposium (ISS) yesterday in Half Moon Bay, Calif.

The University of Florida team of Mark Law and Kevin Jones developed a cornerstone of the modern era of computational modeling of CMOS fabrication process with the Florida Object-Oriented Process Simulator (FLOOPS) which was introduced in 1990. FLOOPS has developed into a widely used, flexible code for multi-dimensional modeling for advanced IC fabrication processes.  The proliferation of the use of FLOOPS as a vital component of process development activities enabled the continued advances in CMOS transistor performance throughout the last decade. The 3D nature of FLOOPS proved especially valuable as CMOS transistor design shifted from planar to multi-gate forms.

Law directed the FLOOPS code development and Jones led an extensive process characterization program, providing a detailed understanding of the relevant dopant-defect interactions needed to validate the specific models used in the FLOOPS code. The robust flexibility of FLOOPS serves as a valuable operational model for other efforts as IC development becomes increasingly dependent on efficient and accurate computational modeling capabilities in all areas of IC device fabrication and operation.  There are now over 200 registered users of the FLOOPS code, including many SEMI member companies. In addition, the team works with graduates who enrich the global talent pool of many SEMI member companies.

The team at Xilinx — Trevor Bauer, Liam Madden, Kumar Nagarajan, Suresh Ramalingam, Steve Trimberger, and Steve Young — is recognized for commercialization of the silicon interposer which provides more than two orders of magnitude increase in die-to-die bandwidth per watt. This achievement effectively addressed both challenges of decreasing power and increasing bandwidth for advanced digital ICs. It also decreased latency to only 20 percent for standard input/output connections. Initially announced in 2011 and first shipped in 2012, the incorporation of a silicon interposer, also called 2.5D technology, delivers performance and power requirements dramatically improved compared to standard packaging.

 

When Xilinx used a silicon interposer in their packaging of advanced FPGA, it represented a major innovation in assembly and packaging technology and provides a learning curve for the many of the technologies that will be needed for high-volume production of 3D-stacked die. The product was realized by dividing their advanced FPGA into four die using 28nm technology and mounting the die side by side using microbumps on a silicon interposer. These die are connected to each other using a 65nm generation redistribution layer on the interposer and, in-turn, to the package substrate using through silicon vias (TSV) in the silicon interposer. The elements of redistribution layers on silicon, TSVs, and microbumps were already available but never combined to provide this high bandwidth, low power packaging solution.

“SEMI is proud to honor both Xilinx and the University of Florida with a SEMI Award.  In addition to developing a key component of CMOS fabrication process with FLOOPS, the University of Florida has contributed valuable time and effort into workforce development for SEMI member companies for many years,” said Karen Savala, president, SEMI Americas.  “Xilinx’s contribution is not only the design of the FPGA packaging using four die, but working with leaders in the foundry, assembly and packaging industries to develop a supply chain enabling volume production.”

“The FLOOPS technology enabled movement of some process development from the factory to the computer decreasing time and cost to implement new device designs,” said Bill Bottoms, chairman of the SEMI Award Advisory Committee. “The commercialization of the TSV based silicon interposer for high performance digital circuits and establishing the supply chain will also substantially accelerate the commercialization of full 3D integration.”

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The award is the highest honor conferred by SEMI. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry. Nominations are accepted from individuals of North American-based member companies of SEMI. For a list of past award recipients, visit www.semi.org/en/About/Awards/AwardNorthAmerica/P037176.

On January 13, SEMI also recognized two individuals — Rick Wallace, CEO and president of KLA-Tencor, and L.T. Guttadauro, executive director of the Fab Owners Association — who have  provided outstanding support to the SEMI Foundation  through donations, vision and volunteer efforts.  The SEMI Foundation was created in 2001 to support education in the area of science, technology, engineering and math (STEM). A key program of the SEMI Foundation is High Tech U (HTU), a hands-on STEM career exploration program that is industry driven and supported through the generosity of SEMI member companies worldwide. For more information, visit www.semi.org/en/About/SEMIFoundation.

Imec celebrates 30 years


January 14, 2014

Nanotechnology research and development center imec, today announced the celebration of its 30th anniversary. Founded in 1984 as a non-profit organization, imec has grown to be a multi-disciplinary expertise center in the fields of semiconductor chips and systems, electronics for life sciences, body area networks, energy, photovoltaics, sustainable wireless communication, image sensors and vision systems, and flexible electronics and displays. Through innovations in nanoelectronics, imec has collaborated with numerous partners from universities, research institutes and top companies, creating solutions and developing emerging technology for a sustainable environment.

In the domain of semiconductor technologies, imec has enabled notable advancements in global semiconductor chip manufacturing in the three decades since its founding.  At the forefront in advancing immersion lithography, EUV, double patterning imec has driven lithography as a key solution to overcome the challenges in scaling down features in silicon chips. In 2013, imec and ASML broadened their partnership with the launch of a Patterning Center. When complete, this Center will offer the global semiconductor ecosystem the most advanced patterning knowledge for sub-10nm technologies, crucial to addressing future scaling and infrastructure challenges. This Center will be extended through partnerships with other suppliers into a “Suppliers Hub,” to collaborate on the development of next generation process technology solutions.

Launched in 2003, imec’s research platform addressed the needs of the semiconductor value chain during the crucial transition from 200mm to 300mm silicon wafers as a manufacturing standard. The platform allows companies to collaborate on advanced process module and device research, targeting technology generations two to three nodes ahead of state-of-the-art IC production. Today, this initiative has evolved to a global collaboration platform with global industry leaders such as Intel, Samsung, TSMC, GLOBALFOUNDRIES, Micron, SK Hynix, Toshiba, SanDisk, Panasonic, Sony, Qualcomm, Altera, Fujitsu, nVidia, Xilinx, and others, driving semiconductor industry innovations.
Imec’s main achievements in semiconductor process technology research include:

1)      Development of sub-22nm process technologies: From silicides to copper (Cu), to the introduction of low-k and high-k/metal gates, imec’s R&D has explored techniques to overcome interconnect metallization issues. In 2013, imec demonstrated the world’s first 3D compound semiconductor FinFET. Integrating III-V and silicon materials on the same 300mm silicon wafer through a unique silicon fin replacement process, imec demonstrated progress toward continued CMOS scaling at 7nm and below, enabling future hybrid CMOS-RF and CMOS-optoelectronics.

2)      Contributions to manufacturability and circuit performance of advanced devices: Imec’s outstanding cleaning expertise has resulted in wafer cleaning solutions with high particle removal efficiency and minimal chemical use. The Rotagoni cleaning method, developed in 2001, solved the challenges faced by single-wafer wet cleaning. Also, imec pioneered research on 3D integrated circuits as a potential road to build more complex, more powerful and more cost-effective electronic systems, combining different types of functionalities on an ever smaller footprint. In 2008, imec demonstrated, for the first time ever, 3D integrated circuits.

Imec’s innovation in nanoelectronics has been a driver for developments in many other domains including healthcare, energy, photovoltaics, communications, and mobility, where imec has applied its semiconductor technology expertise. In 2013, imec’s life science research gained momentum by forging new R&D collaborations with Johns Hopkins University, Janssen Pharmaceutica, Pacific Biosciences, Panasonic, JSR, and others. Such collaborations will lead to breakthroughs in healthcare with the development of the next generation of “lab-on-chip” concepts, powerful supercomputers for life sciences research, and sensor array tools to advance neuroscience research.

“It’s our ambition to further position imec as a unique innovation hub for Europe and the world, where disruptive technology ideas are generated and come to fruition,” stated Luc Van den hove, president and chief executive officer at imec. “We welcome scientists, researchers and engineers from companies of various fields to collaborate with us as they advance and tune their innovations. Imec has proven to be the birthplace of new discoveries, and we confidently look forward to the next 30 years of innovation that will be the backbone of the solutions that will help make the world a better, more sustainable place.”

Nanoelectronics research center imec and AlixPartners, a global business advisory firm, announced today that the two companies are co-developing a cost modeling solution to assess the cost of advanced semiconductor technology options. The work is aimed at assisting the semiconductor industry in improving the operational intelligence around costs of future technology nodes.

This modeling will assess the cost of various patterning options for N10/N7 nodes, advanced packaging solutions and 3D NAND memory – all topics with big impacts on the price-tag of future consumer electronics. Imec and AlixPartners will be comparing the “should-be” cost of lithography-patterning from a system perspective and will assist in providing this information to industry suppliers and materials providers to better provision the development of extreme ultraviolet (EUV) lithography and/or 193inm multi-patterning lithography solutions. This model, designed to address advanced patterning costs, will also be crucial for fabless semiconductor companies (those that outsource their manufacturing) that are defining product strategy in close collaboration with foundries.

Economics today are challenging Moore’s law as the costs associated with node progression have been rising significantly. Below the 28nm node, the semiconductor industry is struggling to maintain its historical 30-percent cost savings per logic gate node over node. At the same time, consumer markets today are demanding cheaper smartphones and other devices, including for the Internet of Things (IoT).

Related news: CES 2014 Highlights

“More than ever, decisions on future technologies must be driven by economics, and this collaborative effort is designed to be a giant step toward providing granular visibility into the costs that drive the semiconductor ecosystem. With this visibility, industry leaders will have the decision support needed to make smart choices on breakthrough technologies, with their available resources”, said Nord Samuelson, managing director at AlixPartners and leader of the firm’s North American High Technology and Semiconductor Practice.

As part of this joint effort, imec and AlixPartners will also work with interested parties who have new ideas on how to reduce semiconductor design, development and manufacturing costs, thereby assisting with the building of corresponding cost models via imec’s existing Industrial Affiliation Program (IIAP).

An Steegen, senior vice president of Process Technologies at imec, said: “Over the last years, we have been pushed by our partners to find new ways to revive Moore’s law from a cost perspective and identify new technologies that can significantly reduce processing cost. We are excited about our collaboration with AlixPartners as it will help us to precisely quantify and compare the cost of different options considered –and in this way prioritize our R&D efforts- and assist in strategizing a product’s roadmap.”

Scott Jones, a director in AlixPartners’ High Technology and Semiconductor Practice, said, “AlixPartners’ business has been built on helping a wide variety of industries to overcome complex operational challenges, uncover new opportunities, minimize risk and maximize value. As the semiconductor industry continues to see rapidly-changing market dynamics, we’re pleased to work with an innovation catalyst such as imec to develop a model designed to help the industry successfully generate next-generation mass-market solutions and products.”

Micron Technology surged 130 percent in revenue during the third quarter as it finally closed its acquisition of bankrupt Elpida Memory of Japan, a vigorous ascent that also propelled the total market for dynamic random access memory (DRAM) to its best performance yet in 11 quarters, according to a new DRAM Dynamics brief from IHS Inc.

Micron ended the third quarter with sales of $2.63 billion, up a sizzling 131.3 percent from $1.14 billion in the earlier quarter, to give the Idaho-based maker 27.4 percent market share. Micron remains at No. 3 overall behind top-ranked Samsung, but Micron is now within striking distance of second-ranked SK Hynix.

Samsung still has a commanding lead with 36.8 percent market share of DRAM, but SK Hynix, with 27.8 percent share, is now just four-tenths of a percentage point ahead of Micron.

Micron’s market share had been hovering in the 10 to 15 percent range for the last several years, but the addition of Elpida’s revenue to its column has made a significant difference. The closing of the Elpida acquisition, more than a year in the making and a formidable rival of Micron in the past, will now more than double Micron’s DRAM manufacturing capability. This means Micron will now claim 25 to 30 percent market share from this point forward.

Micron’s market share in the third quarter received an additional bump because of the company’s high exposure to the PC DRAM space, which has seen prices appreciate considerably since November 2012. Nearly 35 percent of Micron’s revenue came from sales of PC DRAM, IHS estimates.

Overall the global DRAM market continued its blistering pace of expansion in the third quarter, with revenue up 10 percent sequentially to reach $9.59 billion. Not since the third quarter of 2010 has industry revenue climbed so high when the market’s takings then hit $10.68 billion. Industry revenues had hovered at the $6 billion to $7 billion range for seven quarters beginning in the third quarter of 2010 and then breached the $8 billion mark in the second quarter, before making another substantial push this time to end up in rarefied territory.

Growth for the latest period was driven by an increase in shipments and average selling prices (ASP). Shipments are up 5 percent, while ASPs have jumped nearly 7 percent to reach $1.00 per gigabyte.

The DRAM industry is currently on a tear, helped by industry consolidation—including the Micron acquisition of Elpida—that has now left just three major producers, resulting in greater stability and higher prices because of controlled production, benefiting the remaining players.

Samsung expands shipments after SK Hynix suffers a fire

SK Hynix suffered a setback after a fire broke out at its Wuxi, China, plant, notably impacting the company’s DRAM shipments in the third quarter. After growing nearly 40 percent in the second quarter, SK Hynix saw only a 4 percent uptick in revenue in the most recent period because of the fire. The impact of the disaster will be felt through the end of 2013, IHS predicts, but the company should be back to near normal by the end of the year.

Meanwhile, Samsung—already the undisputed leader of DRAM—took advantage of the SK Hynix calamity to grow its own shipments by nearly 15 percent on the quarter, along with a 7 percent hike in ASP. Such results could put Samsung on track to reap record earnings in the fourth quarter—Samsung’s peak quarterly revenue was $4.35 billion in the third quarter of 2010.

For the fourth quarter, total DRAM shipments and prices are forecast to keep climbing. While signs suggest that prices have now reached their current peak with the spot market starting to soften, long-term prospects continue to look positive. And companies that outgrow the market average, such as Micron and Samsung, could well see revenues continue to go up.

Also see: Micron ships first samples of Hybrid Memory Cube

By Dr. Phil Garrou – Contributing Editor

3DIC memory, and therefore all of 2.5/3D technology, took one step closer to full commercialization last week with the HBM joint development announcement from AMD and Hynix at the RTI 3D ASIP meeting in Burlingame CA.

Suh Black, Kirby

Hynix Minsuk Suh, AMDs Byran Black and Microns Kyle Kirby debate the merits of HBM vs HMC at the 2013 RTI ASIP Conference

Bryan Black, Sr Fellow and 3D program manager at AMD noted that while die stacking has caught on in FPGAs and image sensors “..there is nothing yet in mainstream computing CPUs, GPUs or APUs” but that “HBM (high bandwidth memory) will change this.”  Black continued,  “Getting 3D going will take a BOLD move and AMD is ready to make that move.” Black announced that AMD is co-developing HBM with SK Hynix which is currently sampling the HBM memory stacks and that AMD “…is ready to work with customers.”

Minsuk Suh, principle engineer at Hynix confirmed that they are reading both 3D stacked memory for main memory and 3D stacked HBM for networking and graphics applications.   JEDEC specifications for these products are “mostly finalized.”

AMD Hynix 1

Suh indicated that the first application for HBM would be GPUs and that it will next move to networking and HPC applications. Initial details on the HBM processing sequence show a standard vias middle /carrier bonding / thin and via reveal / backside process / stack . TSV are on 40 micron pitch. HBM stacks show a 30% power reduction and a 37X size reduction over standard DDR4.

More details coming in future IFTLE blogs…

Micron Technology, Inc. today announced the availability of 45nm Serial NOR Flash memory samples in 512Mb, 1Gb, and 2Gb densities with a standard SPI interface. These new MT25Q SPI NOR devices offer a cost-effective solution with high performance, enhanced security and drop-in compatibility with legacy NOR devices, enabling high-density SPI NOR adoption in consumer, automotive, industrial and networking applications.

Micron’s MT25Q devices satisfy embedded application requirements with best-in-class 2 MB/s programming speed. In addition, MT25Q devices offer improved erase performance and 66 MB/s read performance, enabling fast updates and boot performance for embedded systems. The MT25Q family also offers the industry’s first serial NOR 2Gb device in a 6mm x 8mm BGA package, which is the smallest package available in the market today.

“The introduction of our new SPI NOR family reconfirms Micron’s commitment to NOR technology and further enables us to continuously meet customer needs,” said Jeff Bader, vice president of Micron’s Embedded Solutions Marketing. “As customers increasingly move to higher-density NOR designs, our MT25Q product line, with 2 MB/s programming speed, supports the need for improved performance, higher manufacturing efficiency and a small footprint.”

MT25Q SPI NOR devices will also maximize design flexibility and minimize redesigns thanks to Micron’s long lifecycle support.

Micron partners with major ecosystem players to enable the MT25Q SPI NOR solutions and help make them the best choice for new and existing application designs.

Samples of the MT25Q devices are available today in BGA and SO16W packages.