Category Archives: 3D Integration

GLOBALFOUNDRIES today unveiled details of a project that demonstrates the value of its open and collaborative approach to delivering next-generation chip packaging technologies. The company, in partnership with Open-Silicon (chief architect) and Amkor Technology, Inc. (assembly and test), jointly exhibited a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded ARM processors, connected across a 2.5D silicon interposer. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications and the viability of the Foundry 2.0 collaborative enablement model.

While some semiconductor manufacturers are approaching next-generation packaging technologies through internal development, GLOBALFOUNDRIES is enabling an open supply chain through collaboration with ecosystem partners and customers. This approach allows GLOBALFOUNDRIES’ customers to choose their preferred supply chain partners, while leveraging the experience of ecosystem partners who have developed deep expertise in design, assembly and test methodologies. When combined with GLOBALFOUNDRIES’ leading-edge manufacturing capabilities, this open and collaborative model is expected to deliver lower overall cost and less risk in bringing 2.5D technologies to market.

“As the fabless-foundry business model evolves to address the realities of today’s dynamic market, foundries are taking on increasing responsibility for enabling the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs,” said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. “To help address these challenges, we are driving our ‘Foundry 2.0’ collaborative supply chain model by engaging early with ecosystem partners like Open-Silicon and Amkor to jointly develop solutions that will enable the next wave of innovation in the industry.”

The test vehicle features two ARM Cortex-A9 processors manufactured using GLOBALFOUNDRIES’ 28nm-SLP (Super Low Power) process technology. The processors are attached to a silicon interposer, which is built on a 65nm manufacturing flow with through-silicon-vias (TSVs) to enable high-bandwidth communication between the chips.

Open-Silicon provided the processor, interposer, substrate, and test design, as well as the test and characterization of the final product. GLOBALFOUNDRIES provided the PDKs, interposer reference flow and manufactured both the 28nm ARM processors and the 65nm silicon interposer with embedded TSVs. Amkor provided the package-related design rules and manufacturing processes for back-side integration, copper pillar micro-bumping, and 2.5D product assembly. GLOBALFOUNDRIES and Amkor collaborated closely throughout the project to develop and validate the design rules, assembly processes, and required material sets.

The companies demonstrated first-time functionality of the processor, interposer, and substrate designs, and the die-to-substrate (D2S) process used by the supply chain resulted in high yields. The design tools, process design kit (PDK), design rules, and supply chain are now in place and proven for 2.5D interposer products from GLOBALFOUNDRIES, Amkor, and Open-Silicon.

“This project is a testament to the value of an open and collaborative approach to innovation, leveraging expertise from across the supply chain to demonstrate progress in bringing a critical enabling technology to market,” said Ron Huemoeller, senior vice president of advanced product development at Amkor Technology. “This collaborative model will offer chip designers a flexible approach to 2.5D SoC designs, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.”

“We are pleased to be at the forefront of making 2.5D a reality with our foundry and OSAT partners,” said Dr. Shafy Eltoukhy, vice president of technology development at Open-Silicon. “This approach will allow designers to choose the right technology for each function of their SoC while simultaneously enabling finer grain and lower power connectivity than traditional packaging solutions along with reduced power budgets for next-generation electronic devices.”

SUSS MicroTec, a global supplier of equipment and process solutions for the semiconductor industry and related markets, has successfully installed an ELP300 excimer laser stepper to support next generation advanced packaging and 3D IC laser debonding applications at the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin. The ELP300 excimer laser platform is designed for high volume manufacturing and processing of 100mm to 300mm wafers. The platform provides two novel manufacturing technologies to Fraunhofer IZM used in advanced packaging and 3D applications: 1) Excimer ablation provides the means to directly create vias and microstructures to combat technical limitations of traditional photo-dielectrics and photolithography approaches and 2) laser debonding of 3D ICs and MEMS for a stress free, non-thermal and very cost efficient method to debond thin wafers off a carrier. The Excimer laser stepper enables the development of higher performance packages in the manufacturing of next generation semiconductor devices, but also provides a significant cost savings potential.

As part of the Fraunhofer-Gesellschaft, Fraunhofer IZM specializes in applied and industrial contract research. Fraunhofer IZM’s focus is on electronic packaging technology and the integration of multifunctional electronics into systems. With the new ELP laser system the Fraunhofer IZM will broaden his expertise in the field of thinfilm polymers. These polymers are an important building block in all wafer level packages. Currently the need of photosensitivity has limited the application of new polymers which are required for thinner devices and 3D stacking applications. With laser ablation completely new polymer systems can be used with enhanced mechanical, physical and chemical properties like lower curing temperature, lower stress, and lower thermal coefficient of expansion. In addition the laser system will give a much higher flexibility for temporary wafer bonding. Ultrathin wafers can be handled safely without damage even at processes which require temperatures above 300 C.

“The ELP 300 will revolutionize technology in wafer level packaging and 3-D integration” says Dr. Michael Toepper manager of WLP at Fraunhofer IZM. “The need of photosensitivity for thinfilm polymers has been a strong barrier for better mechanical properties which are essential for high reliability of electronic systems. In addition the whole process becomes much cheaper and also much more environmentally friendly due to less consumption of organic solvents and TMAH.

“We see high growth potential for this technology, especially in our core market of advanced packaging and the future growth market for 3D ICs,” says Frank P. Averdung, president and CEO of SUSS MicroTec.

By Zvi Or-Bach, President & CEO of MonolithIC 3D

The assertion that Moore made in April 1965 Electronics paper was:

“Thus there is a minimum cost at any given time in the evolution of the technology. At present, it is reached when 50 components are used per circuit. But the minimum is rising rapidly while the entire cost curve is falling (see graph below).”

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“The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.”

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Clearly Moore’s law is about cost, and Gordon Moore’s observation was that the optimum number of components (nowadays – transistors) to achieve minimum cost will double every year.

The reduction of cost per component for many years was directly related to the reduction in feature size – dimensional scaling. But many other technology improvements made important contributions as well, such as increasing the wafer size from 2″ all the way to 12.”

But many observers these days suggest that 28nm will be the optimal feature size with respect to cost for many years to come. Below are some charts suggesting so:

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And more analytical work by IBS’ Dr. Handel Jones:

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Graphically presented in the following chart:

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Recently EE Times reported that EUV Still Promising on IMEC’s Road Map. IMEC provided a road map to transistor scaling all the way to 5nm, as illustrated in the following chart:

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Yes, we probably can keep on scaling but, clearly, at escalating complexity and with completely new materials below 7nm. As dimensional scaling requires more advanced lithography it is clear that costs will keep moving up, and the additional complexity of transistor structures and all other complexities associated with these extreme efforts will most likely drive the costs even higher.

Looking at the other roadmap chart provided by IMEC and focusing on the SRAM bit cell in the first row, the situation seems far worse:

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Since at 28 nm SRAM bit cell is already 0.081μm2, this chart indicates that future transistor scaling is barely applicable to the SRAM bit cell, which effectively is not scaling any more.

Unfortunately, most SoC die area is already dominated by SRAM and predicted to be so even more in the future, as illustrated by the following chart:

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Source:. Y. Zorian, Embedded memory test and repair: infrastructure IP for SOC yield, in Proceedings the International Test Conference (ITC), 2002, pp. 340–349

Dimensional scaling was not an integral part of Moore’s assertion in 1965 – cost was. But dimensional scaling became the “law of the land” and, just like other laws, the industry seems fully committed to follow it even when it does not make sense anymore. The following chart captures Samsung’s view of the future of dimensional scaling for NV memory, and it seems relevant to the future of logic scaling just as well.

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At the recent ECTC conference, various presentations addressed silicon interposers for 2.5D (Shinko), CoWoS reliability (TSMC) and microbumping (imec).

Dr. Phil Garrou, Contributing Editor

Shinko and CEA Leti detailed their presentation entitled “Warpage Control of Silicon Interposer for 2.5D Package Applications.”

Large silicon-interposers when attached to an organic substrate can cause significant warpage problems. Shinko/Leti examined several warpage control techniques including:

  • Using a “chip first process” where chips are mounted on the interposer first vs “chip last process” where the silicon-interposer is mounted on the organic substrate first and chips are mounted onto the interposer last.
  • Using various underfill resins.
  • Using Sn-57Bi solder and thus lowering peak temperature 45-90 degree C. This reduced warpage after reflow to 75% of that using SAC305.

Warpage of silicon-interposer using three types of underfills for 0 level assembly (micro bumps) were investigated. Maximum warpage using U.F. A1, A2 and A3 were 108, 123 and 132mm, respectively. The lowest warpage was obtained at using U.F. A1. With U.F.A3, solder bump open failures were observed. The authors conclude that “using underfill material with low Tg and high storage modulus for 0 level leads to high reliability.”

TSMC and customer Xilinx presented “Reliability Evaluation of a CoWoS-enabled 3D IC Package” which used FEA to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Focus was especially on the fatigue failures of the C4 and BGA joints. Experimental data collected on CoWoS test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme.

Results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid. While a thicker lid has the higher stiffness and better co-planarity, the higher constraint from the thicker lid induces higher stress inside the package which negatively impacts C4 bump fatigue and the micro-bump Ti/Al delamination.

C4 bump layer underfill with Tg of 70°C or 120°C, were studied. The underfill with lower Tg has higher driving force to C4 bump fatigue. When temperature is above Tg, the underfill has much lower Young’s Modulus which has much lower capability to protect C4 bump; and therefore the underfill with lower Tg has higher driving force to C4 bump fatigue. On the contrary, the underfill with lower Tg has lower driving force to Ti/Al delamination in the micro-bump structure. The C4 underfill with lower stiffness can play as a buffer layer and results in lower driving force to Ti/Al delamination in microbump.

imec reported on “Key Elements for Sub-50μm Pitch Micro Bump Processes.” Scaling the microbump pitch from hundreds to a few tens of microns is not straightforward. Several process parameters need to be taken into account to allow a reliable Cu(Ni)Sn ubumping process. One of the challenges for fine pitch Cu(Ni)Sn stacking is to obtain a high bump uniformity. The non-uniformity prevents Cu and Sn from having good contact and subsequent intermetallic formation and increases the risk of underfill entrapment.

A bump scheme that offers better margin for alignment error is better based on a scheme where the size of top die bumps is smaller than the size of the bottom pads. For example it is better to achieve 20μm pitch with 7.5μm bump on 12.5μm pad than with 10μm bump and pad because equal bump and pad diameter can tolerate only 2μm misalignment whereas the 7.5μm/12.5μm bump/pad can tolerate 5μm. This is a significant difference when working close to the stacking tool’s limit of alignment accuracy.

Details on the plasma treatments necessary when attempting to plate into these fine featured plating resists are also discussed.

KEIBOCK LEE, Park Systems, Santa Clara, CA.

3D atomic force microscopes can measure critical dimensions, line edge roughness and sidewall roughness in a way that is highly accurate, non-destructive and cost-effective.

One of the most challenging features in the semiconductor industry is the continuous research and the subsequent fabrication of integrated circuits with enduringly smaller critical dimensions (CDs). As shown in FIGURE 1, CDs must be measured at the top, middle and bottom of features, as well as various parameters such as line edge roughness (LER), the line width roughness (LWR) and the sidewall roughness (SWR).

The characterization of such factors that determine the shape and the roughness of the device patterns for device manufacturers is of utmost importance due to the fact that they directly affect the device performance. Optical measurement techniques, which are limited in terms of resolution. Therefore, the existing prevalent method for measuring these factors prior was primarily the scanning electron microscopy (SEM) with its image analysis software. Despite the fact that this technique offers substantial advantages such as automation and compatibility with standard critical dimension SEM tools, it cannot provide the user with high resolution LER data due to the fact that SEM resolution is reaching its limits, therefore 3D AFM offers a highly desirable solution. Leading manufacturers have implemented AFM that can measure resist profile, LER and SWR in a way that is highly accurate, non-destructive and cost-effective. The precise and full characterization of such features is extremely essential during the pattern transfer process as it offers the possibility of imaging all surfaces of the pattern.

figure1
FIGURE 1. LER, LWR and SWR are the limiting factors of resolution in optical lithography.

What is non–contact 3D AFM?
The basic principle of non-contact 3D-AFM is that a cantilevered beam rapidly oscillates just above the surface of the imaging sample. This offers several advantages, as compared to the traditional contact and intermittent modes. One of the advantages is that there is no physical contact between the tip and the surface of the sample. Moreover, as depicted in FIGURE 2, the Z-scanner, which moves the tip, is decoupled from the XY scanner, which solely moves the sample, thus, offering flat scanning and an additional benefit of improved Z-scan bandwidth. Furthermore, by tilting the Z-scanner, the sidewall of the nanostructures can be accessed and roughness measurements performed along the sidewall of photoresist lines. At the same time, measurements of the critical dimensions of top, middle, and bottom lines can be made.

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FIGURE 2. The independent tilted Z-scanner enables measurements of the sidewalls of features.
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FIGURE 3. Combination of the three acquired images for 3D AFM pattern reconstruction.

Data acquisition is performed by a conical tip in predefined tilted angles, typically 0º, a, and -aº. Consequently, and by combining these three scans (a method called image stitching), the 3D pattern can be constructed, as shown in FIGURE 3. This provides an excellent and extremely accurate method that takes advantage of the interference pattern of the standing waves in order to measure features such as the total height, the top, middle, and bottom width. 3D AFM is capable of advanced three-dimensional imaging of both isolated, and dense line profiles. It is less costly than the alternative techniques (CD-SEM and focused ion beam (FIB)) for imaging and measuring parameters of line profiles since the preparation of the sample is by far simpler.

Noise levels in 3D-AFM
A critical requirement when dealing with metrology tools is associated with constraining the level of noise in the manufacturing environment. A study of noise levels on a 300 mm wafer (FIGURE 4) shows the overall 3D AFM system noise at levels are lower than 0.05 nm (0.5 angstrom).

Roughness measurements
Roughness can be transferred into the final etched profile, thus, roughness measurements can describe and determine the quality of the patterns. The tilted Z scanner in combination with the low noise levels that are prevalent during the AFM process can provide accurate results in terms of sidewall roughness measurements. FIGURE 5 depicts the 3D AFM imaging of a photoresist semi-dense line pattern and the respective grainy structure of its sidewall. The precision with which the SWR was measured is validated by the high repeatability (0.08nm 1 sigma for 5 sites wafer mean) for the sidewall roughness of about 6.0 nm.

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FIGURE 4. 3D AFM noise levels on a 300 mm wafer. The system noise level is less than 0.05 nm at every position and typically 0.02~0.03 nm RMS.
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FIGURE 5. 3D AFM image of a photoresist semi-dense line pattern imaged with Z-scanner tilt. The bottom figure clearly depicts the grainy structure of the sidewall.

It needs to be noted that roughness depends, amongst others, on the aerial image contrast (AIC) or in other words the physics of exposure. AIC is determined as the quotient between the subtraction and the addition of the maximum and minimum image intensities.

Several consequent series of images with variable exposure reveal that LER significantly increases when the AIC is decreased, a fact that underlines that AIC is a controlling factor for LER. Moreover, and as depicted in FIGURE 6, reduced levels of AIC produced line profile images of the resist that were more blunted, and also smaller sidewall angles (SWA).

figure6
FIGURE 6. Park 3D AFM line profiles at different AIC levels reveal the proportionate relationship between SWA and AIC.
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FIGURE 7. A 3D AFM image of a 300 nm photoresist line pattern yields full information regarding the morphology of the sidewall (top) Side-wall Roughness is different at different AIC levels, a fact that indicates the connection between LER and SWR (bottom).

FIGURE 7 illustrates the capability of Park 3D AFM to image all surfaces of the pattern, in contrast to the conventional AFM or the SEM, which cannot fully characterize the surface data, and obtain information such as base, top and both sidewall roughness from sidewall characterization. A 300 nm photoresist line pattern was imaged and the respective line profiles were obtained that clearly showed a substantial difference in terms of SWR between 97% and 40% AIC. More specifically, the lower the value of AIC, the more increased was the measured roughness. This intense decrease of roughness is underlying the fact that LER and the measured sidewall roughness are clearly correlated.

Finally, it needs to be emphasized the role of non-contact 3D AFM in terms of preserving the tip sharpness of the cantilever. In an independent study, researchers performed 150 consecutive measurements using the same tip and the tip wearing proved to be minimal. This is a prominent feature of AFM that prevents the continuous costly replacement of the tip but also ensures that the sample will be viable and not damaged by the AFM cantilever. The preservation of the tip sharpness allows for continual measurements of high resolution roughness data.

Conclusions
The potentialities of the innovative, non-destructive imaging technique of 3D AFM has several advantages compared to conventional SEM systems. An independent and tilted Z-scanner overcomes the disadvantages of alternative metrology tools and measure parameters such as detailed sidewall morphology and roughness, and sidewall angle characterization that render the optimization and evaluation process easier and far more detailed. •

KEIBOCK LEE is president and general manager of Park Systems, Santa Clara, CA.

By Tom Morrow, chief marketing officer, SEMI

While the number of materials used in semiconductor logic will increase approximately 50 percent in the transition from 32nm to 22nm production, the materials revolution in memory will be even more pronounced, challenging developers, manufacturers, equipment, and materials suppliers, according to experts speaking at the SEMI Strategic Materials Conference 2013, held in Santa Clara on October 16-17.  The revolution is being sparked by immediate challenges in DRAM, NAND, 3D and embedded memory at 20nm, and possible scaling limitation of that NAND and NOR flash memory beyond 20 nm. Beyond that node, the industry is looking at new nonvolatile memory structures such as PCRAM, ReRAM, STT-RAM with novel material-sets targeted for high-volume production by 2015-2017.  Further out, magnetic tunneling devices and nanoscale multiferroics may be emerging faster than you think.

“You are going to see an explosion of materials in memory,” said Gregg Bartlett, senior VP and CTO of GLOBALFOUNDRIES, closing the two-day SMC.  Bartlett also noted that materials were eclipsing equipment as the largest cost contributor.

Graphic_1_Tom_SMC_(GlobalFoundries)_PDF

Materials Innovation of Technology Node. Source: Bartlett, GLOBALFOUNDRIES, SEMI Strategic Materials Conference 2013

One area of immediate and comprehensive change is addressing the scaling and performance challenges of 3D stacked memories.  Michel Koopmans, packaging integration manager at Micron, discussed Micron’s 3D stacked DRAM roadmap and the key challenges currently being addressed in R&D and process development. Micron is currently providing samples of a substrate-based TSV and 3D stacked hybrid memory cube.  The HMC Gen 2 product offers the bandwidth (160 GB/s) power (6-8 pJ/bit) and density specifications (2GB & 4GB) that can only be achieved with TVS 3DI solutions, but Micron’s goal is to eliminate the laminate based substrates to further reduce packaging material cost, form factor and power requirements.  According to Koopmans, new technologies are being developed to overcome various wafer level and package level manufacturing challenges and introduce all silicon cubes. From silicon interposers to known good stacked devices in an all silicon form factor, enabling future packaging solutions will require improved and revolutionary materials.

MICRON_graphic_2_Tom_SMC_

Micron All-Silicon HMC Cube. Source: Koopmans, Micron, SEMI Strategic Materials Conference 2013

Manufacturing challenges for all silicon cubes include the need for new processes and assembly technologies, but also for new materials. Koopmans outlined detailed material requirements for TSV liners, TSV seed/barriers, plating chemistries, bump/pillars photo resists, carrier adhesives, backside dielectrics, and wafer level underfill needed for future generations of 3D memory. Besides modified wafer level encapsulation techniques, protecting the all silicon cube may also require new technologies such as spin-on epoxy’s or conformal films.  Enabling this new future, will also require a new level of collaboration between fabs, design and assembly operations.

Unlike the recent past, memory manufacturers today are increasingly on highly divergent development paths with highly specialized materials requirements and process implications. Er-Xuan Ping, Ph.D. and managing director at Applied Material’s Silicon Systems Group, also presented at the Strategic Material Conference.  Dr. Ping sees materials innovation and associated process developments accelerating for both current and new memory technologies.  In NAND scaling, sub 40nm technologies including silicon-oxide-nitride-oxide-silicon (SONOS), TANOS (TaN-Al2O 3-nitride-oxide- silicon) and MONOS (metal-ONOS) structures are all in development. SRAM transistors are migrating mobility channel solutions from Si to SiGe, Ge, and III-V, contact technologies from NiPtSi, to TiSi and MIS, and backend of line technologies from Cu to Ru. Embedded flash is moving to low temperature processing and high K metal gates to meet immediate scaling challenges. Future embedded NVM may utilize submicron nano dots to achieve floating gate operations at required densities and performance.

The dramatic changes in memory technology may be just around the corner. Non-charge based memories, such as phase change memory (PCRAM), spin-transfer torque switching (STT-RAM) and resistive random-access memory (RRAM or ReRAM) are in early adoption with enormous challenges in material and process improvement required to enable high volume manufacturing.  Dr. Ping discussed ReRAM improvement paths include top electrode materials, MeOX modification and MeOX stack; PC RAM current reduction developments using materials modification, thermal efficiency and reduced volumes; and STT RAM low current paths including dual and perpendicular magnetic tunnel junctions (MTJs), among other topics, and their unique process requirements in ALD, PVD, and RIE, IBE processing.

The recognition that scaling limitations are fast approaching has created heightened interest in beyond-CMOS technologies.  Stuart Parkin, Ph.D. and IBM Fellow at IBM’s Almaden Research Center discussed the latest developments in using atomically engineered magnetic heterostructures to create spin-polarized electron currents in new devices typically referred to as spintronics. He discussed a new Racetrack Memory concept utilizing novel three dimensional technology to store information as a series of magnetic domain walls in nanowires, manipulated by spin polarized currents.  Spintronic devices may even allow for “plastic” devices that mimic synaptic switches in the brain, thereby allowing for the possibility of very low power computing devices.

In another long-term possibility, professor Greg P. Carman, Ph.D., director of translational applications of multiferroic systems at UCLA, described recent discoveries that suggest that a ferromagnetic material’s intrinsic magnetization can be manipulated with an electric field, enabling new memory, antenna and motor devices. One multiferroic approach relies on mechanically coupling a single crystal piezoelectric material to a magnetostrictive material where an electric field induces a strain to reorient the material’s magnetization state.  Using physical phenomenon present in nanoscale magnetic elements significantly enhances the electric field induced magnetic changes with efficiencies that could approach 60 percent.

The two-day SEMI Strategic Materials Conference offered presentations from leading market analysts, leading manufacturers, industry consortiums, top suppliers and academic researchers, along with an innovative interactive format designed to facilitate business contacts and networking.  In addition to these insights into memory developments, SMC also provided forecasting information and R&D insights from the materials perspective on logic, carbon-based materials, MEMs, and printed/organic electronics.  This multi-market perspective allows the annual SMC to uncover technology synergies and business cross over opportunities among various materials-enabled devices and industries. This year’s keynotes were provided by Gregg Bartlett, senior VP and CTO, GLOBALFOUNDRIES, and Jo de Boeck, Ph.D., senior VP and CTO, imec.  For information on SEMI, visit www.semi.org.

CEA-Leti, Fraunhofer IPMS-CNT and three European companies — IPDiA, Picosun and SENTECH Instruments — have launched a project to industrialize 3D integrated capacitors with world-record density.

The two-year, EC-funded PICS project is designed to develop a disruptive technology through the development of innovative ALD materials and tools that results in a new world record for integrated capacitor densities (over 500nF/mm2) combined with higher breakdown voltages. It will strengthen the SME partners’ position in several markets, such as automotive, medical and lighting, by offering an even higher integration level and more miniaturization.

The fast development of applications based on smart and miniaturized sensors in aerospace, medical, lighting and automotive domains has increasingly linked requirements of electronic modules to higher integration levels and miniaturization (to increase the functionality combination and complexity within a single package). At the same time, reliability and robustness are required to ensure long operation and placement of the sensors as close as possible to the “hottest” areas for efficient monitoring.

For these applications, passive components are no longer commodities. Capacitors are indeed key components in electronic modules, and high-capacitance density is required to optimize – among other performance requirements – power-supply and high decoupling capabilities. Dramatically improved capacitance density also is required because of the smaller size of the package.

IPDiA has for many years developed an integrated capacitors technology that out performs current technologies (e.g. tantalum capacitors) in terms of stability in temperature, voltage, aging and reliability. Now, a technological solution is needed to achieve higher capacitance densities, reduce power consumption and improve reliability. The key enabling technology chosen to bridge this technological gap is atomic layer deposition (ALD) that allows an impressive quality of dielectric.

The PICS project consortium will address all related technological challenges and set up a cost-effective industrial solution. Picosun will develop ALD tools adapted to IPDiA’s 3D trench capacitors. SENTECH Instruments will provide a new solution to more accurately etch high-K dielectric materials. CEA-Leti and Fraunhofer IPMS-CNT will help the SMEs create innovative technological solutions to improve their competitiveness and gain market share. Finally, IPDiA will manage the industrialization of these processes.

About PICS The PICS project has received funding from the European Union’s Seventh Framework Program managed by REA-Research Executive Agency http://ec.europa.eu/rea (FP7/2007-2013) under grant agreement n° FP7-SME-2013-2-606149.

The PICS Project will last for two years and the consortium consists of three SMEs: IPDiA (France, coordinator), Picosun (Finland) and Sentech Instruments (Germany), and two leading research organizations: Fraunhofer IPMS-CNT (Germany) and CEA-Leti (France). Project objectives are to bring to mass production high density and high voltage capacitors based on ALD and etching development. Further information is available at www.fp7-pics.eu

 

About IPDiA IPDiA is a preferred supplier of high performance, high stability and high reliability silicon passive components to customers in the medical, automotive, communication, computer, industrial, and defense/aerospace markets. The company portfolio includes standard component devices such as silicon capacitors, RF filters, RF baluns, ESD protection devices as well as customized devices. IPDiA headquarters are located in Caen, France. The company operates design centers, sales and marketing offices and a manufacturing facility certified ISO 9001 / 14001 / 18001 / 13485 as well as ISO TS 16949 for the Automotive market. For further information, please visit www.ipdia.com

About Picosun Picosun is the world leading provider of ALD solutions for global industries. Picosun’s pioneering, unmatched expertise in ALD equipment design and manufacturing reaches back to the invention of the technology itself. Today, PICOSUN™ ALD systems are in daily production use in numerous prominent industries around the globe. Picosun is based in Finland, it has its subsidiaries in USA and Singapore, and world-wide sales and support network. For more information, visit www.picosun.com.

 

About SENTECH Instruments SENTECH Instruments GmbH develops, manufactures, and sells worldwide advanced quality instrumentation for Plasma Process Technology, Thin Film Measurement, and Photovoltaics. The medium-sized company founded in 1990 has grown fast over the last decades and has today 60 employees. SENTECH is located in Berlin, capital of Germany, and has moved to its own company building in 2010 in order to expand its production facilities.

SENTECH plasma etchers and deposition systems including ALD support leading-edge applications. They feature high flexibility, reliability, and low cost of ownership. SENTECH’s plasma products are developed and manufactured in-house and thus allow for customer-specific adaptations. More than 300 units have been sold to research facilities and industry for applications in nanotechnology, micro-optics, and optoelectronics. More information: www.sentech.de

About Fraunhofer IPMS-CNT Fraunhofer IPMS-CNT is a German research institute that develops advanced 300 mm semiconductor process solutions for Front-End and Back-End-of Line applications on state-of-the-art process- and analytical equipment. Research is focused on process development enabling 300 mm production, innovative materials and its integration into Systems (SoC/SiP) as well as nanopatterning through electron beam lithography. Fraunhofer is largest application-oriented research organization in Europe with 66 institutes and 22,000 employees. More information:  www.cnt.fraunhofer.de

About CEA-Leti By creating innovation and transferring it to industry, Leti is the bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. Backed by its portfolio of 2,200 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched more than 50 startups. Its 8,000m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. Leti’s staff of more than 1,700 includes 200 assignees from partner companies. Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Visit www.leti.fr for more information.  

By Zvi Or-Bach, President & CEO of MonolithIC 3D Inc.

In the 1960s, James Early of Bell Labs proposed three-dimensional structures as a natural evolution for integrated circuits. Since then many attempts have been made to develop such a technology. So far, none have been able to overcome the 400°C process temperature limitation imposed by the use of aluminum and copper in modern IC technologies for the underlying interconnects without great compromises. The “Holy Grail” of 3D IC has been the monolithic 3D, also known as sequential 3D, where a second transistor layer could be constructed directly over the base wafer using ultra-thin silicon – less than 100nm – thus enabling a very rich vertical connectivity.

Accordingly the industry developed a 3D IC technology based on TSV (Thru Silicon Via) where each strata (wafer) could be independently processed, then after thinning at least one wafer, place in a 3D configuration, and then connect the strata with TSV using a low temperature  (<400°C) process. This independent (parallel) processing has its own advantages; however, the use of thick layers (>50 µm) greatly limits the vertical connectivity, requires development of all new processing flows, and is still too expensive for broad market adoption. On the other hand, monolithic 3D IC provides a 10,000x better vertical connectivity and would bring many additional benefits as was recently presented in the IEEE 3D IC conference.

The semiconductor industry is always on the move and new technologies are constantly being introduced making changes the only thing that is constant. For the most part dimensional scaling has been associated with introducing new materials and challenges, thereby making process steps that were once easy far more complex and difficult. But not so in respect to monolithic 3D IC.

The amount of silicon associated with a transistor structure was measured in microns in the early days of the IC industry and has now scaled down to the hundreds and the tens of nano-meters. The new generation of advanced transistors have thicknesses in nanometers as is illustrated in the following ST Micro slide.

Fig 1

Dimensional scaling has also brought down the amount of time used for transistor activation/annealing, to allow sharper transistor junction definition, as illustrated in the following Ultratech slide

Fig 2

Clearly the amount of heat associated with transistor formation has reduced dramatically with scaling as less silicon gets heated for far less time.

And unlike furnace heating or RTP annealing, with laser annealing the heat is coming from the top and directed only on small part of the wafer as illustrated below.

Fig 3

Fig 4

The following illustrates Excico pulsed excimer laser which can cover 2×2 cm2 of the wafer.

Fig 5

Worth noting that this week we learned of good results when utilizing Excico laser annealing for 3D memory enhancement – Laser thermal anneal to boost performance of 3D memory device.

These trends help make it practical to protect the first strata interconnect from the high temperature process required for the second strata transistor formation. As the high temperature is on small amount of silicon for a very short time and for a small part of the wafer, the total amount of thermal energy required for activation/annealing is now very small.

One of the three most newsworthy topics and papers included in the 2013 IEDM Tip Sheet for the “Advances in CMOS Technology & Future Scaling Possibilities” track was a monolithic 3D chip fabricated using a laser (reported by Solid State magazine “Monolithic 3D chip fabricated without TSVs“). Quoting: “To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.”

Furthermore, in last two weeks we presented in the IEEE 3D IC and IEEE S3S conferences an alternative simulation based work. We suggested to use a smart-cut® for the formation of the second strata (and not amorphous silicon crystallization) with innovative shielding layers to protect the first strata interconnect, as illustrated below.

Fig 6

Currently there are at least three different laser annealing systems offered on the market. The shielding layers could be adjusted according to the preferred choice of the laser annealing system. Our simulations show that if an excimer laser such as one offered by Excico is used, then even without these shielding layers the first strata routing layers are not adversely impacted by the laser annealing process.

Summary: In short, dimensional scaling is becoming harder and yet it makes monolithic 3D easier. We should be able to keep scaling one way or the other (or even both), and keep enjoying the benefits.

Note: smart-cut® s a register TM of Soitec

Nanoelectronics research center imec and Excico have successfully demonstrated the application of laser thermal anneal (LTA) to boost the current in vertical polysilicon channel devices for 3D memory. Due to the larger grain size of the laser recrystallized polycrystalline channel material, up to 10 times higher read current and 2.5 times steeper sub-threshold slope could be obtained as compared to conventional polysilicon channel. This technique provides a way to higher stacking and therefore higher bit density in 3D memory.

Three-dimensional vertical poly-Si channel devices are considered prominent alternatives for many technologies and in particular for new generation nonvolatile memory applications. In such solutions, vertical poly-Si channel transistors are used both as memory cells and as string select transistors. Because devices are typically fabricated with a gate-first, channel-last approach, the formation of single-crystal silicon channel is complicated or even prohibitive. As a result, electron conduction is dominated by scattering at grain boundaries and interface defects of the polycrystalline channel material, significantly decreasing the drive current needed for the read operation.

As a result, grain size engineering is required to obtain larger grains and hence less grain boundaries. Imec and Excico researchers have accomplished this by channel formation with amorphous Si deposition followed by pulsed laser annealing (Excico LTA series, wavelength λ=308 nm, pulse duration < 200 ns). LTA dose needs proper adjustment in order to optimally crystallize the channel (too low doses are not effective whereas too high doses compromise device integrity). Grain structure was inferred from TEM analysis, showing increasingly larger grains from as-deposited, to furnace, to laser recrystallized polysilicon.

In LTA recrystallized polycrystalline channel material, up to 10 times higher read current and 2.5 times steeper sub-threshold slope, could be obtained as compared to other polysilicon channel. Larger grains are obtained that result in less grain boundaries which in turn leads to higher effective mobility, less temperature activation of the conduction mechanism.

Also memory operation was evaluated in cells with ONO (oxide-nitride-oxide) memory stack as well as in macaroni-type cells with a dielectric filler in the center (not shown). Main memory characteristics such as program/erase characteristics, endurance and room temperature retention on fresh and program/erase cycled devices were independent of crystallization thermal treatment, proving that optimized LTA does not impact memory operation. This observation is crucial for the successful fabrication of advanced vertical memory stacks using LTA.

These results were achieved in the framework of imec’s Industrial Affiliation Program on Advanced Memory Devices, with imec’s memory core partners including Intel, Micron, Samsung, SK Hynix, GLOBALFOUNDRIES, Panasonic, as well as Toshiba and SanDisk.

By Sandra Winkler, Senior Industry Analyst, New Venture Research

Small form factor, high speed and performance, and high bandwidth capability with low battery consumption are desired traits for many packaging solutions for integrated circuits (ICs).  High demand for handheld and high performance electronic devices is the driving factor behind the IC packaging needs.

IC packages with an array layout, as opposed to a perimeter layout, allow for more I/O density in a smaller form factor, meeting the needs outlined above.  Thus demand for array packages is on the rise, as additional I/O connections are fit beneath the package than traditional leadframe packages, providing them with form factor benefits.  BGA and FBGA package solutions also reach into I/O levels which are unreachable by traditional leadframe packages, as the substrate can be enlarged to fit a large number of solder balls, land pads, or columns beneath it to attach to the PCB.

Array packages include the PGA, BGA, FBGA, Fan-in QFN, and Fan-out WLPs.  The pin grid array, or PGA, is a through-hole package with pins which attach it to the PCB.  The other packages have more options.

BGA / FBGA

Ball grid arrays (BGAs) and their smaller cousins, fine-pitched ball grid arrays (FBGAs) generally have solder balls on the underside of the substrate for attachment to the printed circuit board (PCB).  The balls provide a self-centering effect during reflow, as well as a standoff for flexibility during electrical surges.

Removing these solder balls makes these packages land grid arrays, or LGAs, which allow for a shorter package in the “z” dimension.  This is important in thinner products, although the package placement to the PCB must be of greater accuracy and thus have a slower throughput.

Columns can take the place of solder balls, which allow for finer pitch and greater density of I/O connections.  These are known as column grid arrays, or CGAs.  These are more expensive to produce than the BGA or LGA package solutions.

The forecasts of each of these segments are provided in New Venture Research’s newly published report, The Array IC Packaging Market, 2013 Edition.

Fan-In QFN Package Solutions

The quad flatpack no-lead, or QFN, is a newer package introduced onto the market in 2008.  A new twist has been added to the QFN to add additional rows to this leadframe package, turning it into a leadframe version of an array package, and one that can reach even further into the market which would otherwise be covered by the larger QFP.  Additional rows are “fanned in” from the traditional perimeter-style leadframe, making this package unique.

Demand for both the traditional QFN and Fan-in QFNs are on the rise, shown in Table 1.

Table 1 Fan-In QFN

 

2012

2013

2014

2015

2016

2017
QFN Percentage of Total IC Packages

12.4%

12.7%

13.2%

13.8%

14.4%

14.8%
Growth Rate of Fan-In QFN and QFP

184.5%

15.4%

25.9%

11.9%

10.5%

9.9%
As a Percentage of Total QFN Market

3.4%

3.6%

4.1%

4.2%

4.3%

4.3%

Fan-Out WLPs

Wafer Level Packages, or WLPs, are the smallest package solution on the market, being die sized.  This unique package is formed while the die are still part of an uncut wafer, the only package to be created or assembled in this manner.  WLPs are array packages by nature, but since all the solder balls or bumps then must fit beneath the die itself, this limits the number of I/O which is on these packages.

The solution to this is the Reconfigured or Fan-out wafer-level packages (Fan-out WLP), for which the available surface available for I/O interface to the PCB is expanded beyond the perimeter of the die by virtue of a backside overmold.  All these processes are done on an uncut wafer, so that manufacturing efficiencies are maximized.

Like the Fan-in QFN, demand for both the WLP and the Fan-out WLP are on the rise.  This is displayed in Table 2.

Table 2 Fan-Out WLP

 

2012

2013

2014

2015

2016

2017
WLP Percent of WW IC Packaging Market

5.3%

5.5%

5.7%

5.9%

6.0%

6.1%
Growth Rate for Fan-out WLPs

60.1%

19.0%

17.0%

16.6%

6.8%

6.1%
Fan-out WLP Percent of total WLPs

9.5%

10.1%

10.8%

11.5%

11.7%

11.6%