Category Archives: 3D Integration

Inside the Hybrid Memory Cube

September 18, 2013

The HMC provides a breakthrough solution that delivers unmatched performance with the utmost reliability.

Since the beginning of the computing era, memory technology has struggled to keep pace with CPUs. In the mid 1970s, CPU design and semiconductor manufacturing processes began to advance rapidly. CPUs have used these advances to increase core clock frequencies and transistor counts. Conversely, DRAM manufacturers have primarily used the advancements in process technology to rapidly and consistently scale DRAM capacity. But as more transistors were added to systems to increase performance, the memory industry was unable to keep pace in terms of designing memory systems capable of supporting these new architectures. In fact, the number of memory controllers per core decreased with each passing generation, increasing the burden on memory systems.

To address this challenge, in 2006 Micron tasked internal teams to look beyond memory performance. Their goal was to consider overall system-level requirements, with the goal of creating a balanced architecture for higher system level performance with more capable memory and I/O systems. The Hybrid Memory Cube (HMC), which blends the best of logic and DRAM processes into a heterogeneous 3D package, is the result of this effort. At its foundation is a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon -vias (TSVs), as depicted in FIGURE 1. An energy-optimized DRAM array provides access to memory bits via the internal logic layer and TSV – resulting in an intelligent memory device, optimized for performance and efficiency.

By placing intelligent memory on the same substrate as the processing unit, each system can do what it’s designed to do more efficiently than previous technologies. Specifically, processors can make use of all of their computational capability without being limited by the memory channel. The logic die, with high-performance transistors, is responsible for DRAM sequencing, refresh, data routing, error correction, and high-speed interconnect to the host. HMC’s abstracted memory decouples the memory interface from the underlying memory technology and allows memory systems with different characteristics to use a common interface. Memory abstraction insulates designers from the difficult parts of memory control, such as error correction, resiliency and refresh, while allowing them to take advantage of memory features such as performance and non-volatility. Because HMC supports up to 160 GB/s of sustained memory bandwidth, the biggest question becomes, “How fast do you want to run the interface?”

The HMC Consortium
A radically new technology like HMC requires a broad ecosystem of support for mainstream adoption. To address this challenge, Micron, Samsung, Altera, Open-Silicon, and Xilinx, collaborated to form the HMC Consortium (HMCC), which was officially launched in October, 2011. The Consortium’s goals included pulling together a wide range of OEMs, enablers, and tool vendors to work together to define an industry-adoptable serial interface specification for HMC. The consortium delivered on this goal within 17 months and introduced the world’s first HMC interface and protocol specification in April 2013.
The specification provides a short-reach (SR), very short-reach (VSR), and ultra short-reach (USR) interconnection across physical layers (PHYs) for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs, such as high-performance networking and computing along with test and measurement equipment.

FIGURE 1. The HMC employs a small logic layer that sits below vertical stacks of DRAM die connected by through-silicon-vias (TSVs).

The next goal for the consortium is to develop a second set of standards designed to increase data rate speeds. This next specification, which is expected to gain consortium agreement by 1Q14, shows SR speeds improving from 15 Gb/s to 28 Gb/s and VSR/USR interconnection speeds increasing from 10 to 15–28 Gb/s.

Architecture and Performance

Other elements that separate HMC from traditional memories include raw performance, simplified board routing, and unmatched RAS features. Unique DRAM within the HMC device are designed to support sixteen individual and self-supporting vaults. Each vault delivers 10 GB/s of sustained memory bandwidth for an aggregate cube bandwidth of 160 GB/s. Within each vault there are two banks per DRAM layer for a total of 128 banks in a 2GB device or 256 banks in a 4GB device. Impact on system performance is significant, with lower queue delays and greater availability of data responses compared to conventional memories that run banks in lock-step. Not only is there massive parallelism, but HMC supports atomics that reduce external traffic and offload remedial tasks from the processor.

As previously mentioned, the abstracted interface is memory-agnostic and uses high-speed serial buses based on the HMCC protocol standard. Within this uncomplicated protocol, commands such as 128-byte WRITE (WR128), 64-byte READ (RD64), or dual 8-byte ADD IMMEDIATE (2ADD8), can be randomly mixed. This interface enables bandwidth and power scaling to suit practically any design—from “near memory,” mounted immediately adjacent to the CPU, to “far memory,” where HMC devices may be chained together in futuristic mesh-type networks. A near memory configuration is shown in FIGURE 2, and a far memory configuration is shown in FIGURE 3. JTAG and I2C sideband channels are also supported for optimization of device configuration, testing, and real-time monitors.

HMC board routing uses inexpensive, standard high-volume interconnect technologies, routes without complex timing relationships to other signals, and has significantly fewer signals. In fact, 160GB/s of sustained memory bandwidth is achieved using only 262 active signals (66 signals for a single link of up to 60GB/s of memory bandwidth).

FIGURE 2. The HMC communicates with the CPU using a protocol defined by the HMC consortium. A near memory configuration is shown.

FIGURE 3.A far memory communication configuration.

FIGURE 2. The HMC communicates with the CPU using a protocol defined by the HMC consortium. A near memory configuration is shown.

A single robust HMC package includes the memory, memory controller, and abstracted interface. This enables vault-controller parity and ECC correction with data scrubbing that is invisible to the user; self-correcting in-system lifetime memory repair; extensive device health-monitoring capabilities; and real-time status reporting. HMC also features a highly reliable external serializer/deserializer (SERDES) interface with exceptional low-bit error rates (BER) that support cyclic redundancy check (CRC) and packet retry.

HMC will deliver 160 GB/s of bandwidth or a 15X improvement compared to a DDR3-1333 module running at 10.66 GB/s. With energy efficiency measured in pico-joules per bit, HMC is targeted to operate in the 20 pj/b range. Compared to DDR3-1333 modules that operate at about 60 pj/b, this represents a 70% improvement in efficiency. HMC also features an almost-90% pin count reduction—66 pins for HMC versus ~600 pins for a 4-channel DDR3 solution. Given these comparisons, it’s easy to see the significant gains in performance and the huge savings in both the footprint and power usage.

Market Potential

HMC will enable new levels of performance in applications ranging from large-scale core and leading-edge networking systems, to high-performance computing, industrial automation, and eventually, consumer products.

Embedded applications will benefit greatly from high-bandwidth and energy-efficient HMC devices, especially applications such as testing and measurement equipment and networking equipment that utilizes ASICs, ASSPs, and FPGA devices from both Xilinx and Altera, two Developer members of the HMC Consortium. Altera announced in September that it has demonstrated interoperability of its Stratix FPGAs with HMC to benefit next-generation designs.

According to research analysts at Yole Développement Group, TSV-enabled devices are projected to account for nearly $40B by 2017—which is 10% of the global chip business. To drive that growth, this segment will rely on leading technologies like HMC.

FIGURE 4.Engineering samples are set to debut in 2013, but 4GB production in 2014.

Production schedule
Micron is working closely with several customers to enable a variety of applications with HMC. HMC engineering samples of a 4 link 31X31X4mm package are expected later this year, with volume production beginning the first half of 2014. Micron’s 4GB HMC is also targeted for production in 2014.

Future stacks, multiple memories
Moving forward, we will see HMC technology evolve as volume production reduces costs for TSVs and HMC enters markets where traditional DDR-type of memory has resided. Beyond DDR4, we see this class of memory technology becoming mainstream, not only because of its extreme performance, but because of its ability to overcome the effects of process scaling as seen in the NAND industry. HMC Gen3 is on the horizon, with a performance target of 320 GB/s and an 8GB density. A packaged HMC is shown in FIGURE 4.

Among the benefits of this architectural breakthrough is the future ability to stack multiple memories onto one chip. •

THOMAS KINSLEY is a Memory Development Engineer and ARON LUNDE is the Product Program Manager at Micron Technology, Inc., Boise, ID.

Packaging at The ConFab

September 18, 2013

At The ConFab conference in Las Vegas in June, Mike Ma, VP of Corporate R&D at Siliconware (SPIL), announced a new business model for interposer based SiP’s, namely the “turnkey OSAT model.” In his presentation “The expanding Role of OSATS in the Era of System Integration,” Ma looked at the obstacles to 2.5/3D implementation and came up with the conclusion that cost is still a significant deterrent to all segments.

By Dr. Phil Garrou, Contributing Editor

Over the past few years, TSMC has been proposing a turnkey foundry model which has met with significant resistance from their IC customers. Under the foundry turnkey model, the foundry handles all operations including chip fabrication, interposer fabrication, assembly and test. Foundry rivals UMC and GlobalFoundries, have been supporting an OSAT/Foundry collaboration model where the foundries would fabricate the chips with TSV and the OSATs would do assembly of chips and interposers that could come from several different sources.

FIGURE 1. Amkor’s “possum” stacking technology.

SPIL is the first OSAT to propose this OSAT centric model where the interposer is fabricated by the OSAT who then assembles and tests modules made with chips from multiple sources. The impediment to this route in the past has been the lack of OSAT capability to fabricate the fine pitch interposers which require dual damascene processing capability, which until now was only available in the foundries. This week SPIL announced the equipment for fine pitch interposer capability (>2 layers, 0.4-3µm metal line width and 0.5µm TSV) has been purchased and is in place.

Ma indicates that while the foundries are not happy with this SPIL proposal, their customers, especially their fabless customers have been very supportive. He feels the inherent lower cost structure of OSATS will have a positive impact on the 2.5/3D market which has been somewhat stagnant since the FPGA and memory product announcements in 2010.

Also presenting at The ConFab: Bob Lanzone, Senior VP of Engineering Solutions for Amkor. He, like the other OSATS, sees smartphones and tablets driving the market moving forward.

Amkor’s update on Copper Pillar technology indicates an expected doubling in demand this year and continued expansion into “all flip chip products”. Their “TSV status” takes credit for being the first into production with TSMC and Xilinx.

Looking at the 2.5D TSV and interposer supply chain they see different requirements for high end, mid-range and lower cost products. For high end, such as networking and servers, silicon interposers are needed with < 2µm L/S, 25k μbumps per die. Amkor is engaged with foundries to deliver silicon interposers today.

For mid-range products, such as gaming, graphics, HDTV, and tablets, silicon or Glass interposers are need with < 3µm L/S, < 25ns latency and ~10k μbumps/die. Amkor is not actively pursuing glass interposers yet as the infrastructure is still immature.

For lower cost products, such as lower end tablets and smart phones, silicon, glass or laminate interposers are needed, with < 8um L/S, low resistance and ~2k μbumps per die. Lazone said a cost reduction path must be provided to enable this sector, and they are working with the laminate supply chain to do that. They are targeting 2014 for their “possum” stacking as shown in FIGURE 1. •

Collaboration needed on 3D-IC

September 5, 2013

By Karen Savala, President, SEMI Americas

The history of semiconductors has been a history of collaboration. For decades, the great leaps forward in semiconductor cost reductions and performance improvements have been achieved through widespread industry collaboration efforts in technology roadmaps, manufacturing standards, wafer size transitions, collaborative R&D consortia, international trade agreements, and other areas. Today, a similar industry-wide collaborative approach to 3D stacked ICs is needed to reach widespread 3D-IC adoption and continue the amazing progress our industry has historically achieved. I will be speaking on this topic at the upcoming 2013 MEPTEC Roadmaps Symposium on September 24 in Santa Clara, Calif. Here’s a preview.

In the past, when the industry was small, semiconductor progress as defined by Moore’s Law occurred nearly simultaneously in different companies. Progress was achieved through science and technology innovation occurring through independent R&D labs and spread through academia and commercial competition. Later, as the scale, scope and complexity of semiconductor manufacturing expanded exponentially—with much of the R&D distributed throughout the supply chain involving hundreds of equipment and materials suppliers each specializing on their unique role in the fabrication process—industry roadmaps were required to keep everyone on pace. No single firm could master all the elements of innovation required for Moore Law improvements. For several years it was an American effort, but in 1998 the roadmap became an international process, today’s International Technology Roadmap for Semiconductors (ITRS). Today, the ITRS has expanded to address not only critical requirements to sustain Moore’s Law, but also the key development milestones necessary in the More-Than-Moore—in areas like advanced packaging and MEMS.

R&D costs have also expanded to meet the targets dictated by Moore’s Law. In the early days, only the largest R&D lab in the world, Bell Labs, could manage the multi-disciplinary requirements for semiconductor chip development. Eventually, collaborative research consortia emerged that allowed industry players to pool resources in a pre-competitive environment to develop the science and technology needed for the next generation chip.

In addition to collaborative roadmaps and R&D, the semiconductor industry also agreed upon collective industry standards that reduced cost and spur innovation. These standards involve such areas as wafer size and dimensions, software and hardware interfaces, materials characterization and test methods, and hundreds of other areas. Today, there are nearly 4,000 volunteers from every major company working together on SEMI industry standards. They have produced hundreds of widely-accepted standards that have reduced costs and allowed companies to compete on innovation. In addition to SEMI Standards, other standards bodies have emerged such as IEEE and JEDEC to address semiconductor standards needs in electrical, signaling, form factor, packaging and other areas.

With roadmaps, standards and consortia in place, the semiconductor industry targeted what was considered by some an “easy” wafer transition to 300mm silicon. It was anything but easy. As many of you know, the transition went poorly. The industry couldn’t agree when to introduce 300mm production and stop advanced development at 200mm, and they couldn’t afford to do both. There were several false starts and hundreds of millions of dollars were lost.

Today, the industry is planning a 450mm wafer transition while at the same time trying to manage the increasingly complex R&D challenges of new materials development, new transistor architectures, and new packaging paradigms. The cost of advanced semiconductor development has skyrocketed. The industry has responded by dramatically expanding the Consortia model for collaborative R&D.

Over the last two years, the industry has launched nearly a dozen consortium-like entities in 450mm and related areas of development. Joining Belgium’s imec, Germany’s Fraunhofer Institute, Taiwan’s ITRI, and France’s CEA-Leti—to name a few—are a number of new consortia established to collaborate on joint R&D for 450mm wafers and other next-generation semiconductor challenges. GlobalFoundries, Intel, IBM, Samsung and TSMC formed the Global 450 Consortium (G450C) to manage 450mm wafer processing requirements. Recently, G450C set up a separate fab facility consortium. Europe has launched five separate 450mm projects or consortiums, with two others on the drawing board. Israel has established 450mm consortium on metrology and Japan has collaborative arrangement on 450mm with Toshiba.

With uncertainties on 450 wafer processing, EUV lithography, and the continued transition to new transistor architectures, many experts are questioning the continuation of Moore’s Law. It’s been reported that cost targets at 28 nanometers were not reached, 20 nanometers may be delayed and also come in at a high price. Consequently, the industry has been excited about More-Than-Moore applications, especially 3D stacked ICs that promise to improve bandwidth, reduce footprint, decrease power consumption, and lower cost.

We have seen the proliferation of stacked die with wire bond or flip chip, stacked packages, package-on-package, and chip-on-chip packages. But today, the most anticipated innovation is 2.5 and 3D stacked ICs using TSVs to achieve both the power and bandwidth benefits associated with a radical new interconnect solution.

Like 450mm wafer processing, critical standards foundation work for the adoption 3D-IC is well underway. At SEMI, Standards task forces have been established in thin wafer handling, inspection and metrology, and wafer bonding. But like 450mm wafer processing, enabling the 3D-IC revolution will require more than industry standards activities.

While a promising technology, technical challenges remain with 3D stacked ICs. Many companies have a silicon interposer or 2.5D solution on their packaging roadmaps where a logic device is mounted next to a stack of memory and the TSVs are in the substrate. However, while Samsung and others have made announcements, affordable stacked memory is not yet available. In addition, many companies are also looking at alternatives to silicon interposers, such as glass interposers, to bring the price down. So, even 2.5D has been delayed and questions remain about its configuration at high volume. For heterogeneous integration of memory and logic, the industry still needs design tools, thermal solutions, continued work on wafer bonding and de-bonding, and accepted test methodologies, to name a few requirements.

Gartner estimates that TSV adoption for memory will be pushed out to 2014 or 2015, with non-memory applications delayed to 2016-17 if that. They currently forecast that TSV devices will account for less five percent of the units in the total wafer-level packaging market by 2017.

For 3D-IC to be widely adopted, meaningful collaboration throughout the value chain still needs to occur. At this time in the market, all the important players in the ecosystem have a different perspective. All the players have a business model that must be defended or exploited based on what technical discoveries occur and what customers eventually want. TSMC sees an integrated approach that threatens the traditional Fabless/Foundry/OSAT model. Obviously leading OSATs prefer this vision as it provides an opportunity to expand their business. But OSATs themselves are looking at ways to differentiate. IDMs like Intel probably see the fabless model coming full circle with 3D IC. Fabless companies believe that 3D must emerge in ways that continue their own—and their customer’s — familiar multiple-sourcing considerations.

We’ll continue to see discoveries, inventions and new products in 3D-IC and progress will continue. Hundreds of patents in the area have already been issued. We’re seeing innovation and invention in wafer bonding, via manufacturing, and other areas. Standards work at JEDEC and SEMI will also contribute to the market’s development, both to enable processes and cost-reduce manufacturing, but without the emergence of a new, robust collaboration model that can deliver meaningful agreements between key constituencies, the promise of 3D innovation will remain distant and illusive.

In addition to 2013 MEPTEC Roadmaps Symposium (September 24), 3D-IC industry progress will also be the subject of the SIP Global Summit (September 5-6) held in conjunction with SEMICON Taiwan, and The Advanced Packaging Conference (October 8-9) at SEMICON Eu

Stanford and UT Austin professors to be honored at annual SRC TECHCON

September 5, 2013

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, will honor professors from Stanford University and University of Texas at Austin with awards for chip-related research and education at SRC’s annual TECHCON conference Sept. 9-10.

Dr. James Harris, professor of Electrical Engineering at Stanford University, will be the recipient of this year’s SRC Aristotle Award for outstanding teaching and a deep commitment to the educational experience of his students. With SRC support, Harris’ team at Stanford’s Solid State and Photonics Laboratory has pioneered research in multiple semiconductor disciplines from nanofabrication to optoelectronics and spintronics.

Additionally, Dr. David Pan, professor of Electrical and Computer Engineering at University of Texas at Austin, is the recipient of the SRC Technical Excellence Award for his SRC-funded work advancing nanometer integrated circuit (IC) design for semiconductor manufacturability across multiple layers from mask synthesis to physical design.

Selected by SRC’s 12 member companies and the SRC staff, the award-winning faculty and research teams will be recognized for their exemplary impact on semiconductor productivity through cultivation of technology and talent. The awards will be formally presented during SRC’s annual TECHCON conference hosted in Austin, Texas. The conference features next-generation research progress among hundreds of university students, faculty and industry experts.

“Today’s technology-based economy critically depends on a robust university research enterprise — producing fundamental scientific advances and, just as importantly, well-educated scientists and engineers,” said SRC President Larry Sumney. “The valuable researchers we are recognizing this year have helped the industry achieve both of those aims.”

Stanford and UT Austin Research Fuels Semiconductor Advancements

The scope and impact of Dr. Harris’ research includes new electronic and optoelectronic device structures created by heterojunctions, quantum wells, superlattices and engineered materials. Molecular Beam Epitaxy (MBE) is utilized to prepare artificially structured metastable materials with atomic layer control and dimensions smaller than the wavelength of electrons. In this regime, quantum size effects can be utilized to create entirely new device structures based upon tunneling and/or transitions between quantum states.

“I had the good fortune to first study under and be mentored by many of the early leaders in semiconductor technology (Pearson, Moll, Shockley, Linvill, Gibbons, Kroemer), and second, to be at the earliest stages of nanotechnology and development of MBE and have been able to pass on to succeeding generations of students my mentors’ enthusiasm, knowledge and creativity for the continued development of this amazing technology over the past 40 years,” said Dr. Harris.

Dr. Pan’s research includes cross-layer nanometer IC design for manufacturability and reliability, new frontiers of physical design and CAD for emerging technologies including 3D-IC, bio and nanophotonics. One key feature of his research is to seek synergistic design-technology co-optimization across multiple abstraction layers with strong algorithmic components for holistic optimizations.

“I am truly honored and humbled to receive this award. As a former SRC-supported student, a former SRC member company (IBM) researcher and liaison and now an SRC principal investigator, I have always had wonderful experiences with SRC,” said Dr. Pan. “Through regular interactions with SRC liaisons, my students and I are very proud to be part of the SRC community to carry out forward-looking, yet impactful university research and push forward the design technologies in extreme scaling and beyond.”

The Aristotle Award is given to SRC-funded university faculty that have profoundly and continuously impacted their students’ professional performances in a way that provides long-term benefit to the SRC member companies. The Technical Excellence Award recognizes researchers who have made key contributions to technologies that significantly enhance the productivity of the semiconductor industry

More than 9,000 students have been prepared by SRC programs, professors and mentors for entry into the semiconductor business.

EV Group unveils new via-filling process to improve reliability of 3D-IC/TSV packaging

September 4, 2013

EV Group, a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled a new polymer via-filling process for 3D-IC/through-silicon-via (TSV) semiconductor packaging applications. Available on the EVG100 series of resist processing systems, the new NanoFill process provides void-free via filling of very deep trenches and high-aspect ratio structures, and is suitable for all common polymeric dielectrics—offering a highly flexible, low-cost and production-ready via-fill platform for interposer development for 3D-integrated image sensors and other device types.

TSV interconnects are critical to the development of 3D-ICs since they enable through-chip communication between the vertically stacked device layers. Currently, most TSVs employ a solid copper via structure. However, the mismatch in coefficient thermal expansion (CTE) between the copper via and the surrounding silicon can create a high amount of stress on the via structure, which results in long-term reliability issues. Replacing copper as the conducting material is not practical due to the general ease of use of the process as well as the fact that the tooling infrastructure for copper is already well established. However, replacing the solid copper via with a partial copper-plated via that is filled with a polymeric dielectric has been demonstrated to reduce CTE mismatch and stress, thus minimizing reliability issues. EVG’s proprietary process and system enable simultaneous void-free via filling and dielectric redistribution layer (RDL) formation utilizing a field-proven process technology that is compatible with all standard polymeric materials.

“3D packaging represents a fundamental change in the semiconductor industry that paves the way for continued advances in device performance and cost reduction through ‘More than Moore’ approaches,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “EV Group has made significant investments in our portfolio of wafer-level manufacturing solutions to add new products and capabilities, such as our NanoFill solution, to help our customers accelerate the commercialization of 3D-integrated devices.”

EVG’s new NanoFill via-filling solution provides numerous advantages over traditional spin coating and dry lamination techniques, including providing complete via filling for permanent passivation and planarization without forming voids or cavities. The solution’s ability to use all common polymeric materials provides customers with a high degree of flexibility. In addition, a sidewall passivation option is available that provides cost and throughput benefits for selected applications.

Dow Corning and EV Group to collaborate on temporary bonding materials for 3D-IC

September 3, 2013

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, announced today that Dow Corning has joined its network of top technology providers to support EVG’s LowTemp platform for room-temperature wafer bonding and debonding processes. The addition of Dow Corning to EVG’s list of collaboration partners follows intensive co-development efforts between the two companies, including stringent testing of Dow Corning’s simple and innovative bi-layer temporary bonding technology. EVG launched its new open LowTemp platform in July when it also announced the expansion of its global materials supply chain to accelerate the growth of high-end 3D-IC packaging.

“As a global leader in advanced silicone technology and expertise, Dow Corning is an important and much welcomed addition to our open temporary wafer bonding/debonding materials platform,” said Dr. Thorsten Matthias, business development director, EV Group. “Their collaborative approach and exceptional materials expertise helped us to develop an innovative, cost-effective temporary bonding solution that now offers our customers expanded options for room-temperature bonding and debonding of active and carrier wafers using conventional manufacturing methods.”

EVG’s LowTemp temporary bonding/debonding platform (TB/DB) features three different room-temperature wafer-debonding processes – ultraviolet (UV) laser debonding, multilayer adhesive debonding and ZoneBOND technology – that have been qualified for the company’s high-volume production.

EVG said that Dow Corning’s bi-layer TB/DB silicone technology is a natural fit for its platform in that it comprises an adhesive and release layer that enables simple, room-temperature TB/DB, and delivers best-in-class performance with regard to low total thickness variation. It also provides excellent chemical resistance and good thermal stability when exposed to temperatures reaching 300 degrees Celsius.

Through this non-exclusive agreement, the two companies plan to offer the advanced semiconductor packaging industry a cost-effective TB/DB solution to support high-volume production of 3D-IC packaging applications.

“This collaboration signifies another major milestone for Dow Corning, EVG and the semiconductor industry as a whole with regard to 3D IC and through silicon via development,” said Andrew Ho, global industry director, Advanced Semiconductor Materials at Dow Corning. “In addition to signaling another important validation of Dow Corning’s simple, room-temperature temporary bonding/debonding technology, it enables further commercialization of EVG’s leading-edge open platform for volume manufacturing. Equally important, this technology represents a major step forward toward the further integration of the 3D-IC packaging process for next-generation microelectronic applications.”

3D-IC integration promises to significantly improve the form factor, bandwidth and functionality of microelectronic devices by enabling once-horizontal chip structures to be fabricated into vertical architectures. However, this revolutionary new technology first requires simple, cost-effective TB/DB solutions to adhere active device wafers to thicker carrier wafers. This allows subsequent thinning of the active wafer down to 50 microns or less, and fabrication of through-silicon vias that enable vertical interchip communication.

Moore’s Law Dead By 2022: Crying Wolf?

August 30, 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about recent predictions regarding the demise of continued scaling.

“Moore’s Law Dead by 2022” announces EE Times headline reporting on a keynote by Bob Colwell’s at Hot Chips this week. Actual quote: “Moore’s Law — the ability to pack twice as many transistors on the same sliver of silicon every two years — will come to an end as soon as 2020 at the 7nm node.” Collwell told the audience that DARPA “tracks a list of as many as 30 possible alternatives to the CMOS technology that has been the workhorse of Moore’s Law. My personal take is there are two or three promising ones and they are not very promising,” he said. Colwell is the Director of DARPA’s Microsystems Technology Office (MTO) and has both visibility and credibility in these matters. In fact, this is not his first time to publicly state the end of Moore’s Law — he did so at ACM SIGDA and DAC meetings earlier this year. His slide (below) clearly presents the gap between the end of dimensional (Dennard) scaling and the establishment and ramp-up of alternatives to the current silicon based technology.

The discussion at EE Times remind us that we have “been hearing this for 20 years or more”, so why is it different now? Well, even in the crying wolf story the wolf eventually did come! This time the signs are very clear. In fact, one could argue that as far as cost reduction, Moore’s Law is already dead. The following ASML chart clearly shows it.

Taking into account additional information released during the recent Semicon West, it seems that effective cost for most fabless companies might even go higher with future scaling. Even if we ignore the fact that most foundries chose to keep their metal rules at 20nm when going to 14nm node, with the associated end-device cost implications, advanced nodes come with many additional layout restrictions. Those create circuit design and interconnect overheads that eat away a large part of theoretical scaling benefits. Quoting Andrew Kahng: “Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap.” Add to it the fact that embedded memory SRAM bit cell is expected to barely scale, as shown in the following slide, and end-product costs might go up even for the same SoC complexity!

The following chart from Samsung clearly illustrates this dynamics for NAND, but from the above discussion it may be even more true for SoC.

The issue of cost has very significant implications. For the semiconductor industry Moore’s Law is not just a matter of pride: it became one of its fundamental business drivers. In the food industry vendors keep on selling food as it get consumed, clothing and car industry products get worn out or go out of fashion. But in the semiconductor industry old products mostly get displaced by better new products – the upgrades. Imagine what would happen to the major industry players’ stock if they were to update their projections to expect 20% reduction in revenue!!!

And 20% might be a conservative number once the dynamics of the last 30 years would hit a hard stop.

The following Samsung chart is a good illustration of where we are and the choice that at least Samsung has made:

We can keep on hoping that the wolf will never come, just as it hasn’t before. Or we can take action now before ‘they comes’.

Samsung, Toshiba and the rest of the NAND industry are already taking action. On the SoC side the challenges are as severe, yet at this point the industry is consumed by the enormous efforts to bring up FinFETs. It may even bring up compound semiconductors (III-V) for the next node (10nm), but then what? At what cost? For what kind of return?

It seems to me that the right moves are:

First, logic design market needs to adopt an alternative to the embedded memory. IBM stated at the recent Common Platform Forum that adopting eDRAM gave it the equivalent benefit of one node scaling. This was seconded by Intel’s recent announcement of integrating eDRAM with their new Haswell processor – Intel eDRAM attacks graphics in pre-3-D IC days. An even better option would be the one transistor two state memory breakthrough solution recently developed by Zeno Semiconductors.

Second, logic design needs to follow the NAND industry by developing monolithic 3D technology for SoC and logic products. In a recent blog we reported that CEA Leti has placed Monolithic 3D is now on the roadmap for 2019. We are pleased to announce that we will provide a tutorial on monolithic 3D as a part of the upcoming IEEE 3D IC Conference in early October in San Francisco, and we will follow with a plenary talk the following week at the IEEE S3S Conference in Monterey. In these conferences we also plan to present a new practical process flow for monolithic 3D, leveraging industry’s shift to laser annealing. This technology supports 3D technologies we had presented in the past, and can be used independently for new monolithic 3D process flows. We are looking forward to meeting you all there.

Entegris and imec collaborate on 3D wafer handling and shipping challenges

August 28, 2013

Entegris, Inc., a developer of contamination control and materials handling technologies for highly demanding advanced manufacturing environments, and imec, a research center in nanoelectronics, announced they are collaborating to advance the development and broaden the adoption of 3D integrated circuits.

3D IC technology, a process by which multiple semiconductor dies are stacked into a single device, is aimed at increasing the functionality and performance of next-generation integrated circuits while reducing footprint and power consumption. It is a key technology to enable the next generation of portable electronics such as smartphones and tablets that require smaller ICs which consume less power.

One of the key steps in 3D IC manufacturing process entails thinning semiconductor wafers while they are bonded to carrier substrates. Handling such thinned 3D IC wafers during the production process can result in wafer breakage, edge damage, and particle generation. A standardized, fully automated solution that supports the handling of multiple types of wafers would result in a significant cost reduction and pave the way toward further development and scaling of 3D IC technologies. Imec and Entegris are working on creating a solution to safely transfer and handle multiple kinds of 3D IC wafers without the risk of breakage and other damage that may occur during the 3D production process.

"We are excited to work with the imec team, which is a key research center leading technology innovation for the semiconductor industry," said Bertrand Loy, president and CEO of Entegris. "Our current collaboration is aimed at leveraging our wafer handling expertise and technology to reduce contamination and breakage by applying full automation to the handling of thin wafers during 3D wafer production. This project builds on our previously completed work with imec to develop dispense and filtration methods to reduce bubble and defect formation during the dispense of material that is used to temporarily bond 3D wafers to carrier substrates," said Loy.

"This collaboration with Entegris aims at developing a solution toward fully automated handling of multiple types of 3D IC wafers," stated Eric Beyne, director of imec’s 3D integration research program. "Such a general solution would imply a significant reduction of the development cost, which is key to the realization of a scalable and manufacturable 3D IC technology."

Samsung introduces worldâs first 3D V-NAND-based SSD

August 14, 2013

Samsung today introduced the first solid state drive (SSD) based on its recently released 3D V-NAND technology. Samsung announced its new SSD, designed for use in enterprise servers and data centers, during a keynote at the Flash Memory Summit 2013.

Samsung V-NAND SSD

“By applying our 3D V-NAND – which has overcome the formidable hurdle of scaling beyond the 10-nanometer (nm) class, Samsung is providing its global customers with high density and exceptional reliability, as well as an over 20 percent performance increase and an over 40 percent improvement in power consumption,” said E.S. Jung, executive vice president, semiconductor R&D center at Samsung Electronics and a keynote speaker at the Flash Memory Summit. “As we pioneer a new era of memory technology, we will continue to introduce differentiated green memory products and solutions for the server, mobile and PC markets to help reduce energy waste and to create greater shared value in the enterprise and for consumers.”

Monolithic 3D is now in production: Samsung starts mass producing first 3D vertical NAND flash

August 6, 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about Samsung’s recent announcement on 3D vertical NAND.

Samsung announced today (Aug. 6, 2013) the mass production of the industry’s first three-dimensional (3D) Vertical NAND (V-NAND) flash memory, which breaks through the current scaling limit for existing NAND flash technology. Achieving gains in performance and area ratio, the new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs).

According to Samsung, the new V-NAND offers a 128 gigabit (Gb) density in a single chip, utilizing the company’s proprietary vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology to link the 3D cell array. By applying both of these technologies, Samsung’s 3D V-NAND is able to provide over twice the scaling of 20nm-class planar NAND flash.

It’s worth mentioning to the point that while the volume production of TSV based 3D IC is keep being pushed out as discussed in a recent blog: EUV vs TSV: Which one will become production ready first?, this announcement indicates that monolithic 3D NAND is beating the forecast by a few years as illustrated by the following 2012 ITRS chart:

Clearly monolithic 3D is a promising alternative to dimension scaling, as one can read in the Samsung announcement. It also adheres very well to the low cost objective for mass production products.

Monolithic 3D technology provides multiple unique and powerful advantages as we present on our site under the tab: 3D-IC Edge. Under item 5 we present the unique advantage that was first introduced in 2007, when Toshiba unveiled its Bit Cost Scalable (BiCS) technology. The unique advantage of 3D NAND is the ability to pattern and process multiple layers simultaneously.

This advantage comes very naturally for regular layout fabrics such as memory, but it is also available for logic circuits. The driver for this advantage is the escalating costs of lithography in state of the art IC. The following charts illustrate the impact of dimensional scaling on lithography costs.

Currently critical lithography steps dominate the end device production costs as illustrated in the following chart:

Accordingly, if the critical lithography step could be used once for multiple layers rather than multiple times for each single layer, then the end device cost would roughly be reduced in proportion to the number of layers processed simultaneously. Multiple memory architectures that support such drastic cost reduction has been presented in various conferences and other forums. Few of those had been presented in our blog: The Flash Industry’s Direction, and MonolithIC 3D Inc.’s Solution…