Category Archives: 3D Integration

Alchimer, S.A. today announced a collaboration with the French research institute CEA-Leti to evaluate and implement Alchimer’s wet deposition processes for 300mm high-volume manufacturing. The project will evaluate Alchimer’s Electrografting (eG) and Chemicalgrafting (cG) processes for isolation, barrier and seed layers. When combined, Alchimer’s wet deposition processes have been demonstrated to achieve 20:1 aspect ratio through silicon vias (TSVs) due to their ability to coat conformally regardless of via topography, diameter or depth.

3D integration is moving towards a "via middle" approach where TSVs are formed after front-end processes, but prior to stacking.  Several applications are in the development phase, leading to constraints and different specifications for TSVs. Alchimer’s technology shows the potential to break through existing barriers to achieve high aspect ratio TSVs. This collaboration will evaluate the potential of its technology and its suitability for high-volume manufacturing.

"Current techniques, such as PECVD isolation and iPVD metallization, have performance limitations that are limiting achievable TSVs to 10:1 aspect ratios," said Bruno Morel, CEO of Alchimer. "Our 3D TSV products have unequivocally demonstrated their ability to deliver 20:1 aspect ratios at a significantly reduced cost as compared to current approaches. Now it is critical to validate the products’ full potential for 300mm high-volume manufacturing as well as to study their compatibility with the overall 3D integration process. Leti’s leading 3D expertise and world-class infrastructure will allow us to do that.

"Collaborating with Alchimer fits perfectly our strategy of delivering innovative solutions to industry," added Fabrice Geiger, head of Leti’s Silicon Technology Division. "Alchimer’s eG technology is a promising, cost-effective and breakthrough solution to address the challenges of future 3D TSV integration. Through this collaboration, Alchimer will have access to Leti’s expertise in the domain of 3D TSV integration and its world-class 300mm 3D platform capabilities."

eG is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. This process achieves a combination of conformality, step coverage and purity that cannot be matched by dry processes.

Europe’s recently launched industrial strategy to reinforce micro- and nanoelectronics manufacturing is more than just a vision — it’s a major opportunity for equipment and material suppliers to participate to large-scale investment projects, increase their holding in key technologies and reach out to new customers and markets. Implementation is already underway: the first EU funding calls for projects will start at the latest in early 2014 and discussions are already underway on investment priorities.  The recent launch of five EU projects, worth over €700 Million and bringing together over 120 partners, around 30 percent of which are small and medium enterprises, is proof that Europe can put its “money where its mouth is.” So what should you be doing to join the 10/100/20 momentum?

10/100/20 in a nutshell

Dubbed the ‘10/100/20’ strategy, the EU initiative will see €10 billion worth of EU co-funded projects (public/private investment), coupled with €100 Euros investment by the industry with the goal of 20 percent of global chip manufacturing by 2020. The aim is to focus on Europe’s strengths, pool together EU, national and regional resources and invest in specific areas that can give Europe a competitive edge globally. EU investment will cover the entire semiconductor manufacturing supply chain, from research to design and device makers. Maintaining leadership in equipment and material supply is clearly stated as an objective of the EU’s strategy, as is the integration of small and medium enterprises (SMEs) in value chains and providing them access to state-of-the-art technologies and R&D&I facilities.

Why get involved, especially as a SME

A number of companies, and small and medium enterprises in particular, may shy away from EU projects, perceiving them to be too complex to access and placing too much of an administrative burden for little financial gain. But the true value of EU projects lies in the new network you have access to: a variety of companies across the supply chain, many of who will become your new customers, and access to state-of-the-art research facilities and technologies. Take the example of the five pilot lines recently launched with combined funding from the EU, national governments and partner companies under the ENIAC program:

The European 450 Equipment Demo Line (E450EDL) will support the equipment and materials industry in the 450mm wafer size transition. 43 partners from 11 European countries will develop and test lithography, front end equipment, metrology tools and wafer handling and automation equipment. The partners include the large European research centers and equipment and device manufacturers, as well as smaller companies. The demo line will provide a world-class research infrastructure to validate tools that remain at the manufacturers’ sites, thus giving suppliers access to state-of-the-art facilities and an opportunity to share the knowledge and financial burden of testing their products. The Lab4MEMS project will create the first European pilot line for innovative technologies on advanced piezoelectric and magnetic materials, including 3D packaging, offers SMEs and fabless companies a manufacturing route for their future projects that has been difficult to access so far.

Interested? So what’s next?

Now is the time to decide on the technology trends that you want your company to follow and start reaching out to your partners and customers. If you think your technology could give Europe a competitive edge and should be part of Europe’s investment strategy, then start talking about it, show its benefits and convince people that this is the way to go. In the case of EU projects, there is strength in numbers, so start talking to your customers and your suppliers, look at what others are doing, and see how you can fit into the technology and investment trends.

The EU pledge of €10 billion worth of public/private co-financed projects will be spent gradually in the form of regular EU funding calls, the first of which is expected by end 2013. The call will set the overall requirements for project ideas: what technologies the project should focus on, what parts of the value chain should be partners to the project, the estimated overall budget and duration of the project as well as the technical details for applying for EU funding.  By the time the call has been published, you should already have an idea of what it is you want to do, who you want to work with and how you can fit your idea into the investment priorities that will be announced.

How to get connected

If you are visiting SEMICON West in San Francisco, then mark your calendar for Wednesday, July 10. At 16:00/4:00pm there will be a presentation of the new 10/100/20 strategy for Europe at the TechXpot in South Hall. Join us to find out more about the new strategy, why it’s important and how to get involved.

Your next major opportunity to meet with the equipment and materials industry, learn about the latest technologies and discuss the EU strategy is SEMICON Europa 2013 (8-10 October, Dresden, Germany).  Our programs will cover each of the major projects, including 450mm wafer processing, power electronics, MEMS, FDSOI as well as advanced packaging including 3D and TSV technologies.  They will in one way or the other all address Europe’s 10/100/20 strategy. The SEMICON Europa Executive Summit will discuss implementation of the strategy and we are also organizing an EU funding workshop with hands-on advice about how to identify funding opportunities for your company and join EU projects.

For more information on SEMICON Europa, please visit: www.semiconeuropa.org. The event in Dresden will again be co-located with Plastic Electronics Europe. The conference and exhibition is the leading international technology-to-industry and industry-to-industry event focused on organic and large area electronics. It is the premium forum in its kind where professionals in the area and from around the world meet to present and to discuss progress of topics. For more information, please visit: www.plastic-electronics.org.

 

EV Group and Dynaloy, LLC today introduced CoatsClean—an single-wafer photoresist and residue removal technology designed to address thick films and difficult-to-remove material layers for the 3D-ICs/through-silicon vias (TSVs), advanced packaging, MEMS and compound semiconductor markets.  In its official press release, EVG said CoatsClean provides a complete wafer cleaning solution that offers significant efficiency, performance and cost-of-ownership (CoO) advantages compared to traditional resist stripping and post-etch residue removal methods.

"Increasing wafer processing challenges associated with the adoption of new materials, device architectures and packaging schemes requires a new, holistic view of wafer cleaning, where the chemistry, process and equipment are all critically important and must be addressed in combination," stated Steven Dwyer, business director at Dynaloy.  "We’re pleased to be working with EV Group on developing and commercializing CoatsClean technology to meet the needs of our customers for a more cost-effective, flexible approach to thick-film resist removal."

The CoatsClean process and chemical formulation are engineered to perform at higher temperatures, resulting in faster stripping rates and cycle times.  This enables CoatsClean to operate as a single-wafer process for thick resist films and difficult-to-remove resists—resulting in improved performance, consistency, reproducibility and repeatability.  The engineered formulation also enables selective stripping of the resist.

CoatsClean is also unique in its ability to dispense a small amount of material on the top of the wafer, and then activate the material with direct heat.  This direct utilization of the material and heat dramatically reduces the strip material used.  CoatsClean uses fresh solution for each processed wafer compared to competing techniques that use an immersion bath—resulting in greater process efficiency and eliminating cross contamination.  The highly selective application of resist strip material eliminates damage to the wafer backside.  The entire CoatsClean process is performed in a single bowl, which reduces tool footprint.

"CoatsClean applies the right chemistry at the right process conditions to provide optimal cleaning results," stated Paul Lindner, EV Group’s executive technology director.  

EV Group will be responsible for selling the CoatsClean systems and providing customer support, while Dynaloy will be responsible for selling the CoatsClean resist stripping materials.  CoatsClean systems have already been installed for customer demonstrations, and EVG and Dynaloy are now accepting orders for the systems and resist stripping materials.

Dr. Deepak Sekar is a senior principal engineer at Rambus Labs. He is the author or co-author of a book, two invited book chapters, 30 publications and 100 issued or pending patents (50 issued). He is a program committee chair at the International Interconnect Technology Conference, has received two best paper awards and serves on the committee of the International Technology Roadmap for Semiconductors. 

 In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult. The solution, he said, is to supplement VLSI with what he called a Wafer Level System Integration (WLSI) paradigm. Advances in wafer level packaging and through-silicon via technology could allow systems to scale and reduce the dependence on transistor/chip scaling, according to Yu.

Figure 1: Douglas Yu of TSMC talked about WLSI

Techniques for WLSI

Yu then described TSMC’s efforts towards WLSI.

Fan-in wafer level packages, where the package is the same size as the chip, were shown with sizes as high as 52 sq. mm (see Figure 2(a)). These could be used for low pin count applications such as WiFi.

Fan-out wafer level packages, where individual die are embedded in a molding compound, could be used for higher pin count applications, said Yu. These allow placing one or more die within the same package. TSMC has qualified large 225 sq. mm fan-out wafer level packages with tight 20um pitch redistribution layer wiring (see Figure 2(b)). These fan-out wafer level packages could be used for medium to high pin count applications and also for multi-chip packages.

Figure 2: (a) A 52 sq. mm fan-in wafer level package (b) A 225 sq. mm fan-out wafer level package where the die is surrounded by a molding compound

Yu then showed TSMC’s silicon interposer and 3D-TSV technology, called CoWoS (chip-on-wafer-on-substrate). Figure 3 depicts the process flow for CoWoS and finished systems built with the technology. It is just a matter of time before TSV technologies are prevalent, he said.

Figure 3: Chip-on-Wafer-on-Substrate technology used for interposer and 3D systems

How WLSI could allow system scaling despite the increasing challenges with Moore’s Law

Significant reductions in system size are possible with wafer level packaging, interposer and 3D stacking technologies, said Yu. This is particularly beneficial to mobile applications, which show the fastest growth in the industry today. This would allow packing more and more functionality within the same form factor, something Moore’s Law is finding increasingly difficult to do.

Smart system partitioning with WLSI can benefit electronic products quite a bit, said Yu. He gave an example of partitioning digital and analog components. With finFETs moving to production, designing analog components on the same chip as logic becomes difficult due to high parasitic capacitance. Analog blocks take up more and more percentage of the chip area since they don’t scale well. In this scenario, placing analog components on a separate chip and using fan-out wafer level packaging or TSV technology to build competitive systems is beneficial, he said. This allows systems to combine analog at a trailing edge node (eg. 65nm) and logic at a leading edge node (eg. 14nm). IP blocks can be reused, time-to-market can be accelerated with smart system partitioning and yields can be improved due to the lower die size, said Yu.

System performance per watt improvement, one of the benefits of Moore’s Law scaling, can also be obtained with WLSI, according to Yu. Memory (access) power is now a key component of total system power and this is increasing with every generation. By using fan-out wafer level packaging or TSV technology, memory power can be significantly reduced due to the shorter wire lengths (Figure 4).

Figure 4: WLSI could reduce logic to DRAM wire lengths from 20mm to 0.03mm.

During the question and answer session, Yu mentioned that all of the technologies he described used pure wafer-based processes, which allowed larger packages and lower cost. Audience members, when asked about the keynote, mentioned that cost will determine how prevalent the technologies presented in Yu’s talk will become. 3D chip technologies are still considered a few years away from mass adoption.

The International Interconnect Technology Conference, held in Kyoto this year, is IEEE’s flagship conference in the interconnect field.

Advanced packaging technology is undergoing dramatic changes as the smart phones and new sensor technologies demand continued improvements in form and function.  To address these massive changes, SEMICON West will feature a number of programs on new packaging technologies and processes with speakers from leading chip makers, equipment manufacturers, and material suppliers.

According to IDC, forecasts semiconductor revenues will log a compound annual growth rate (CAGR) of 4.1 percent from 2011-2016, but revenues for 4G phones will experience annual growth over 100 percent for the same period. NanoMarkets estimates that the global market for “Internet of Things” sensors will reach $1.6 billion this year and grow to a value of $17.6 billion by the end of the decade as sensors become increasingly connected to the Internet directly or through hubs.  Both trends will significantly impact semiconductor and microelectronics packaging.  Demand for equipment and related tools in the 3D-IC and wafer-level packaging area alone is forecasted to grow from approximately $370 million in 2010 to over $2.5 billion by 2016, according to Yole Developpment.

To address these changes, SEMICON West 2013 (register at www.semiconwest.org/registration), held on July 9-11 in San Francisco, will feature a number of programs on new packaging applications, requirements, technologies, and products, including:

  • Generation Mobile:  Enabled by IC Packaging Technologies — Speakers from ASE, UBM Tech Insights, Amkor Technology, SK Hynix, and Universal Scientific Industrial will present on the latest advances in wafer-level packaging, new materials, and multi-die integration, including new System-in-Package (SiP) and Package-on-Package (PoP) methods. Location: Moscone Center (North Hall), TechXPOT North, Tuesday, July 9, 10:30am-12:30pm.
  • “THIN IS IN": Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era — IEEE/CPMT will hold a technical workshop on the overall trend of maximum functional integration in the smallest and thinnest package with lowest packaging costs with speakers from Intel, Cisco, ASE, Micron, SK Hynix, Nanium, Kyocera and more. Location: San Francisco Marriott Marquis, Tuesday, July 9, 1:30-4:45pm.
  • Advancing 2.5D and 3D Packaging through Value Engineering — Speakers from Altera, Amkor, ASE, ASET, KPMG, UMC, STATS ChipPAC and more will take a critical look at 2.5D implementations and the current outlook for 3D packages, including tools and technologies for heterogeneous stacks. Location: Moscone Center (North Hall), TechXPOT North, Wednesday, July 10, 1:00-3:30pm.
  • MEMS & Sensor Packaging for the Internet of Things— This session will feature speakers from all parts of the ecosystem to address how future visions of a pervasive interconnected world will be realized through the heterogeneous integration of MEMS and ICs.  The program will feature keynote speaker Janusz Bryzek from Fairchild Semiconductor, and speakers from VTT Research, Fraunhofer IZM, Robert Bosche, EV Group, Dai Nippon Printing, and more. Location: Moscone Center (North Hall), TechXPOT North, Thursday, July 11, 10:30am-1:00pm.

In addition to the packaging programs, SEMICON West 2013 will also feature over 560 exhibitors with the latest innovation on microelectronics manufacturing, including over 150 exhibitors with equipment and technology solutions for advanced packaging.  Other programs and exhibitors at West will address lithography, advanced materials and processes, silicon photonics, test, LED and MEMS manufacturing, and other subjects.  For more information on SEMICON West and to register, visit www.semiconwest.org

Fab equipment spending will grow two percent year-over-year  (US$ 32.5 billion) for 2013 and about 23 to 27 percent in 2014 ($41 billion) according to the May edition of the SEMI World Fab Forecast. Fab construction spending, which can be a strong indicator for future equipment spending, is expected to grow 6.5 percent ($6.6 billion) in 2013, followed by a decline of 18 percent ($5.4 billion) in 2014. The new World Fab Forecast report covers fab information on over 1,140 facilities, including such details as capacities, technology nodes, product types, and spending for construction and equipment for any cleanroom wafer facility by quarter.

Fab equipment spending for the second half of 2013 is expected to be much stronger with a 32 percent growth rate or $18.5 billion compared to the first half of 2013. The equipment spending increase in the second half is attributed to growing semiconductor demand and improving average selling price for chips. 2014 is expected to have about 23 to 27 percent growth year-over-year (YoY) to reach about $41 billion, which would be an all-time record.

Looking at product types, the largest amounts of spending on fab equipment in 2013 will come from the foundry sector, which increases by about 21 percent. This is driven mainly by capex increases by TSMC. The memory sector is expected to have an increase of only one percent — after a 35 percent decline in the previous year. The MPU sector is expected to grow by about five percent. A double-digit increase in the Analog sector in 2013 will still translate into low absolute dollar amounts, compared to the other sectors.  

 

Construction spending is a good indicator for more equipment spending.  Fab construction spending in 2013 is expected to be almost 15 percent growth YoY ($6.6 billion) with 38 known construction projects. Top spenders for fab construction in 2013 are TSMC and Samsung, who plan to spend between $1.5 and $2 billion each, followed by Intel, Globalfoundries and UMC. The SEMI World Fab Forecast report reveals more detail.

2014 shows a decline of about 18 percent ($5.4 billion) in construction spending with only 21 construction projects expected to be on-going. These construction projects include large fabs; some are 450mm-ready. 

Since the last fab database publication at the end February 2013 SEMI’s worldwide dedicated analysis team has made 389 updates to 324 facilities (including Opto/LED fabs) in the database. The latest edition of the World Fab Forecast lists 1,144 facilities (including 310 Opto/LED facilities), with 61 facilities with various probabilities starting production this year and in the near future. Seventeen new facilities were added and 8 facilities were closed.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs; and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter.

GLOBALFOUNDRIES plans to unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes at next week’s 50th Design Automation Conference (DAC) in Austin, Texas. The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches.

Multi-vendor support is available, with full implementation flows from Synopsys and Cadence Design Systems. Physical verification with Mentor Graphics’ suite of tools is included in the flow.

The GLOBALFOUNDRIES 2.5D technology addresses the challenges of multi-die integration with solutions for front-end steps such as via-middle TSV creation, and flexibility for the backend steps, like bonding/debonding, grinding, assembly, and metrology.

“Our 2.5D technology provides designers with a path to enable heterogeneous logic and logic/memory integration, offering increased performance and reduced power consumption, without the need for additional packages,” said Andy Brotman, vice president of design infrastructure at GLOBALFOUNDRIES. “These benefits can now be realized very efficiently with certified design flows that provide support for the additional steps and design rules involved in the design process. By working closely with our EDA partners, we can greatly reduce the development time and time-to-production using the most advanced multi-die approaches.”

The flows allow designer to quickly and reliably address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing. The flows support the need for additional verification steps brought on by 2.5D design rules.

The design flows work with GLOBALFOUNDRIES’ process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GLOBALFOUNDRIES design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

The flows come with a CPU core and memory IP and all the scripts and settings to execute a Synopsys Galaxy Implementation Platform-based flow or Cadence Encounter-based implementation flows with the GLOBALFOUNDRIES PDK. Similarly, the Mentor Calibre 3DSTACK tool is exercised in the flow to verify DRC, LVS and extraction within and between the various die stacks leveraging the same golden design kits as used inside of GLOBALFOUNDRIES .

The semiconductor industry’s march toward broader 3D IC integration marked an important milestone this week at the 2013 Electronic Components & Technology Conference (ECTC), with the report of an advanced new temporary bonding solution for 3D Through-Silicone-Via (TSV) semiconductor packaging. The breakthrough was unveiled during ECTC’s 3D Materials and Processing session, when Ranjith John, materials development and integration engineer at Dow Corning, presented a paper co-authored by Dow Corning, a developer of silicones, silicon-based technology and innovation, and SÜSS MicroTec, a supplier of semiconductor processing equipment.

The paper, titled Low Cost, Room Temperature Debondable Spin on Temporary Bonding Solution:  A Key Enabler for 2.5D/3D IC Packaging, details the development of a bi-layer spin-on temporary bonding solution that eliminates the need for specialized equipment for wafer pretreatment to enable bonding or wafer post-treatment for debonding. Thus, it greatly increases the throughput of the temporary bonding/debonding process to help lower the total cost of ownership. 

“This advance underscores why Dow Corning values collaborative innovation. Combining our advanced silicone expertise with SÜSS MicroTec’s knowledgeable leadership in processing equipment, we were able to develop a temporary bonding solution that met all critical performance criteria for TSV fabrication processes. Importantly, the spin coat-bond-debond process we detailed in our co-authored paper takes less than 15 minutes, with room for further improvement,” said John. “Based on these results, we are confident that this technology contributes an important step toward high-volume manufacturing of 2.5D and 3D IC stacking.”

Both 2.5D and 3D IC integration offer significant potential for reducing the form factor of microelectronic devices targeting next-generation communication devices, while improving their electrical and thermal performance. Cost-effective temporary bonding solutions are a key enabler for this advanced technology by bonding today’s ultra-thin active device wafers to thicker carrier wafers for subsequent thinning and TSV formation. However, in order to be competitive, candidate temporary bonding solutions must deliver a uniformly thick adhesive coat, and be able to withstand the mechanical, thermal and chemical processes of TSV fabrication. In addition, they must subsequently debond the active and carrier wafers without damaging the high-value fabricated devices.

Through their collaboration, Dow Corning and SÜSS MicroTec were able to develop a temporary bonding solution that met all of these application requirements. Comprising an adhesive and release layer, Dow Corning’s silicon-based material is optimized for simple processing with a bi-layer spin coating and bonding process. Combined with SÜSS MicroTec equipment, the total solution offers the benefits of simple bonding using standard manufacturing methods. In their co-published paper, the collaborators report a solution exhibiting a total thickness variation of less than 2 µm for spin-coated films on either 200- or 300-mm wafers. The bonding material exhibited strong chemical stability when exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. In addition, the bonding solution and paired wafers showed good thermal stability when exposed to the 300°C temperatures common to the TSV process.

Dow Corning builds on a long history of silicon-based innovation and collaboration in semiconductor packaging. From die encapsulants for stress relief, to adhesives for sealing and bonding, to thermal interface materials for performance and reliability, Dow Corning’s well-established global infrastructure ensures reliable supply, quality and support, no matter where you are in the world.

CEA-Leti will host a workshop for industrial companies to present its latest advances in MEMS and an overview of the success of its recent MEMS startup, Wavelens, during Transducers’ 2013 and Eurosensors XXVII in Barcelona, Spain.

Workshop: 6:30-8 p.m., June 18, Rooms 118-119, CCIB Barcelona

The session features three brief presentations from 6:30-7:10 p.m.: 6:30-6:40 p.m.: Overview of CEA-Leti, from technologies to applications.  Jean-René Lèquepeys, head of Leti’s Silicon Components Division, which is involved in micro- and nanoelectronics, micro- and nanosystems, and 3Dstacking.

6:40-7 p.m.: Presentation of Leti’s most recent major achievements in the MEMS field, with a focus on advanced multi-purpose MEMS and NEMS platforms. Dr. Julien Arcamone, manager for MEMS business development in the Silicon Components Division.

7-7:10 p.m.: Update on Wavelens, a recent Leti startup that is focused on improving the performance of miniature cameras with innovative MEMS optical solutions. Dr. Arnaud Pouydebasque, Wavelens CTO.

A networking and cocktail event will follow the workshop from 7:10 p.m. to 8 p.m.

Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. CEA-Leti operates 8,000-m² of clean room space on 200mm and 300mm wafer platforms. It employs 1,700 scientists and engineers including 320 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 2,200 patent families.

Mentor Graphics Corp. and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.

 “Tezzaron specializes in 3D wafer stacking and TSV processes. We work with dozens of customers to create custom 3D-ICs for prototyping and commercialization, including recent 3D-ICs in 40nm and 65nm, the first at these small nodes,” said Robert Patti, CTO and VP of design engineering at Tezzaron Semiconductor. “By collaborating with Mentor Graphics, we can offer our mutual customers a comprehensive design verification solution. It creates the highest value for them with the least disruption to their existing flows. Using Calibre, our customers get the best possible turnaround time. Even better, there is no need to generate a ‘Frankenstein’ GDS file combining all the individual dies in a 3D-IC assembly, and no need to deal with a ‘monster’ rule file combining different die processes. Calibre makes the process very fast and relatively easy.”

Tezzaron works with industry, academia, and government to create advanced 3D-ICs. Their offerings include wafer stacking and die stacking technology with TSVs, Bi-STAR built in self-test and repair circuitry for continuous error detection and recovery, and extremely fast memory devices for both standalone and stacked applications.

Complementing Tezzaron’s 3D-IC design capabilities, the Calibre 3DSTACK signoff solution provides DRC, LVS, and parasitic extraction (PEX) capabilities. It verifies physical offset, rotation, and scaling at the die interfaces. It also enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation. The Calibre 3DSTACK product is a fully compatible extension to the standard Calibre signoff platform, so it can be easily added to existing verification flows to support flexible stacking configurations of multiple dies, including dies based on different technologies or process nodes.

“Over the last two years, the relationship between Mentor Graphics and Tezzaron has really blossomed as we work together to bring volume 3D-IC applications to the IC industry mainstream,” said Michael Buehler-Garcia, senior director of marketing for Calibre Design Solutions at Mentor Graphics.

Tezzaron Semiconductor Corporation is a designer and producer of 3D-ICs built with through-silicon vias (TSVs). Tezzaron also builds patented ultra-high-speed memory products. Tezzaron’s products and technologies have applications in defense, super-computing, high speed telecommunications, and anywhere that speed, reliability, and power optimization are needed. Corporate headquarters are located at 1415 Bond Street, Suite 111, Naperville, Illinois.