Category Archives: 3D Integration

Copper shrinkage results in tensile stress in the silicon while CMP stop layer shrinkage results in compressive stress in the silicon

Copper shrinkage results in tensile stress in the silicon while CMP stop layer shrinkage results in compressive stress in the silicon

Through Silicon Vias (TSVs), an important component of 3D chip stacking technology, typically have a “keep-out zone” around them, where transistors are not placed. This is due to co-efficient of thermal expansion mismatch between the copper TSVs and silicon, which introduces tensile stresses in the silicon and changes transistor performance. These keep-out zones are typically >7mm, which adds constraints for design and leads to die size penalties.

In this work from GLOBALFOUNDRIES, a CMP stop layer is specially designed such that it introduces compressive stresses on the silicon and compensates for the tensile stresses introduced due to copper TSVs. The result is a near-zero keep-out zone for TSV technology, that is validated with simulations as well as experiments.

[5.2. M. Rabie, et al., “Novel Stress Free Keep Out Zone Process Development for Via Middle TSV in 20nm CMOS”, GLOBALFOUNDRIES]

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By Dr. Phil Garrou, Contributing Editor

I have said many times that it will be impossible for a complicated technology like 3DIC to ever become commercial without standardization. SEMI has been working on this now for 3+ years. Let’s take a look at their recent update from their SEMICON Singapore presentation. So far, they have published the following standards:

SEMI 3D1-0912, Terminology for Through Silicon via Geometrical Metrology

– Clear and commonly accepted definitions are needed for efficient communication and to prevent misunderstanding between buyers and vendors of metrology equipment and manufacturing services.

– The purpose of this Document is to provide a consistent terminology for the understanding and discussion of metrology issues important to through silicon vias (TSV).

SEMI 3D2-1113, Specification for Glass Carrier Wafers for 3DS-IC

– This Specification describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state;

– Methods of measurements suitable for determining the characteristics in the specifications indicated.

SEMI 3D3-0613, Guide for Multi-Wafer Transport and Storage Containers for 300 mm, Thin Silicon Wafers on Tape Frames

–Address the methods for shipping thin wafers on tape frames.

SEMI 3D4-0613, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

– Control of bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and

– This std provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.

SEMI 3D5-0314, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through- Silicon Vias (TSVs) in 3DS-IC Structures

– This std assists in the selection and use of tools for performing measurements of geometrical parameters of an individual TSV (through-silicon via), or of an array of TSVs.

SEMI 3D6-0913, New Standard: Guide for CMP and Micro-bump Processes for Frontside Through Silicon Via (TSV) Integration

– This std provides a generic middle-end process flow to define acceptable TSV and CMP quality criteria as well as to develop methodology and measuring procedures for micro-bump.

SEMI 3D7-0913, New Standard: Guide for Alignment Mark for 3DS-IC Process

– Photo alignment mark configuration is the key to ensure consistent and precise alignment of layers, chips and wafers.

– This standard provides an alignment mark strategy for chip to chip, chip to wafer, and wafer to wafer stacking.

SEMI also has organized task forces in North America, Taiwan and Japan focused on various aspects of 3DIC manufacturing and testing. The North America task force is focused on:

Bonded Wafer Stacks – Create and/or modify specifica- tions that reflect bonded wafer stacks parameters and the wafer bonding process.

Inspection & Metrology – Develop standards for metrology and inspection methods to be used for measuring TSV properties, bonded wafer stacks, and dies used in the 3DIC manufacturing process.

Thin Wafer Handling – Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro- pillar Grid array -MPGA) used in 3DIC high-volume manufacturing (HVM).

Yole Développement announced its 2.5D, 3DIC and TSV Interconnect Patent Investigation report. Yole Développement’s investigation aims at providing statistical analysis of existing IP to give a landscape overview together with an in-depth investigation on five player portfolios selected by the analyst.

2.5D, 3DIC and TSV patent landscape

A very young patent landscape dominated by 10 companies

For this analysis of 3D packaging technology patents, more than 1800 patent families were screened. Fifty-two percent of the families have been classified as relevant and further studied.

“The in-depth analysis quickly revealed that the overall patent landscape was pretty young with 82 percent of patents filed since 2006,” explained Lionel Cadix, technology and market analyst of the Advanced Packaging division at Yole Développement. “Actually about 260 players are involved in 3DIC technology while the top 10 assignees represents 48 percent of patents filed in the 3DIC domain.”

In this report, Yole Développement selected five companies from these 10 most active players to focus on and lead an accurate analysis of their patent portfolios.

Yole Développement also found main types of business models among the top 10 assignees involved in this mutating middle end area:

  • Foundries and IDM: IBM, Samsung, Intel
  • OSATs: STATS ChipPAC, Amkor
  • Memory IDM/Foundries: Micron, SK Hynix, Elpida
  • Research centers: ITRI

It is also interesting to notice that the USA is the early player increasingly involved in 3DIC since 1969. China and Korea are new players since 2005.

This complete description of the patent landscape is included in the first part of the report and provides all the background materials for the 3DIC patent landscape analysis. Yole Développement’s report provides a complete analysis of the patent landscape including geographical origins of the patents, companies or R&D organizations that have been granted the patents, historical data on when the companies that have applied for patents in the last 20 years, inventors of the patents, expiration status, R&D collaborations.

Understanding the patent portfolio of the top 10 3DIC assignees

The report also provides a deep dive into each of the patent portfolios of assignees selected by Yole Développement, including Intel, Samsung, Micron, IBM and TSMC.

For each of these companies, Yole’s report provides an in-depth analysis of its patent portfolio, highlighting the following points:

  • Company patent portfolio evolution
  • Countries of deposition and origin of the patents
  • Top inventors
  • Technical segmentation of each patent portfolio
  • Patent portfolio analysis for each manufacturing process steps and architecture
  • Main technical innovations

This analysis of each company provides an in-depth view of the strengths and weaknesses of the patent portfolio of each company and the developments that are now implemented by these companies.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing and design, announced that worldwide sales of semiconductors reached $23.48 billion for the month of March 2013, an increase of 1.1 percent from the previous month when sales were $23.23 billion. Global sales for March 2013 were 0.9 percent higher than the March 2012 total of $23.28 billion, and total sales through the first quarter of 2013 were 0.9 percent higher than sales from the first quarter of 2012. All monthly sales numbers represent a three-month moving average.  

“Through the first quarter of 2013, the global semiconductor industry has seen modest but consistent growth compared to last year,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “Sales have increased across most end product categories, with memory showing the strongest growth. With recent indications that companies could be set to replenish inventories, we are hopeful that growth will continue in the months ahead. Regionally, the Americas slipped slightly in March after a strong start to the year, but Asia Pacific and Europe have seen impressive growth recently.” 

Year-over-year sales increased in Asia Pacific (6.9 percent) and Europe (0.7 percent), but decreased slightly in the Americas (-1.5 percent) and sharply in Japan (-18 percent), reflecting in part the devaluation of the Japanese yen. Sales in Europe increased by 5.7 percent compared to the previous month, the region’s largest sequential monthly increase since March 2010.  Sales also increased from the previous month in Asia Pacific (1.7 percent), but fell in Japan (-1.6 percent) and the Americas (-1.9 percent).

MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, has teamed up with imec, Ireland’s Tyndall National Institute and ePIXfab, the European Silicon Photonics support center providing low-cost prototyping services for photonic ICs. The partnership gives MOSIS’ customers access to imec’s state-of-the-art fully integrated silicon photonics processes and Tyndall’s advanced silicon photonics packaging technology.

Packaged passive silicon photonics chip, showing imec’s silicon photonic chip andTyndall’s fiber array packaging.

Imec’s silicon photonics platform enables cost-effective R&D of silicon photonic ICs for high-performance optical transceivers (25Gb/s and beyond) for telecom, datacom, and optical sensing for life science applications. The offered integrated components include low-loss waveguides, efficient grating couplers, high-speed silicon electro-optic modulators and high-speed germanium waveguide photo-detectors. A comprehensive design kit to access imec technologies will be provided. Moreover, the Tyndall National Institute, being a partner of ePIXfab, offers the ability to provide packaged silicon photonics devices. This includes the design and fabrication of custom photonic packages, fiber coupling (single and arrays) and electrical interconnects. Design rules to support these packaging capabilities will also be provided.

“Imec’s Silicon Photonics platform provides robust performance, and solutions to integrated photonics products. Companies can benefit from imec silicon photonics capability through established standard cells, or explore the functionality of their own designs in MultiProject Wafer runs,” stated Philippe Absil, program director at imec. “With this collaboration, MOSIS will offer its first access to a mature Silicon Photonics infrastructure, with the option for follow-on production,” added Wes Hansford, MOSIS Director.

The first ePIXfab-Europractice run for passive silicon photonics ICs is open for registration from June 2013 with design deadline September 9th 2013. MOSIS’ customers can register for this run and obtain the design kit via MOSIS in June 2013.

Imec’s Si Photonics 200mm wafer platform includes:

  • Tight within-wafer silicon thickness variation 3sigma < 2.5nm
  • 3-level patterning of 220nm top Si layer (193nm optical lithography)
  • poly-Si overlay and patterning (193nm optical lithography)
  • 3-level n-type implants and 3-level p-type implants in Si
  • Ge epitaxial growth on Si and p-type and n-type implants in Ge
  • Local NiSi contacts, Tungsten vias and Cu metal interconnects
  • Al bond pads
  • Validated cell library with fiber couplers, polarization rotators, highly efficient carrier depletion modulators and ultra-compact Ge waveguide photo-detectors with low dark current.
  • Design kit support for IPKISS framework, PhoeniX Software and Mentor Graphics software

Tyndall’s Si Photonics Packaging Technology enables:

  • Passive device packaging, single and multi-fiber arrays to grating couplers
  • Active device packaging, modulators and detectors with electrical ports and fiber arrays
  • Custom packaging requirements (mechanical, thermal stability etc.)

Amkor Technology, Inc. today announced that Stephen D. Kelley has been appointed to serve as president and chief executive officer and as a director of the company, effective May 8, 2013. Kelley succeeds Ken Joyce, who previously announced his intention to retire. Kelley’s appointment follows a comprehensive, six month search process conducted by the Board of Directors with the professional assistance of a global executive recruiting firm.

 “We have been investing significant resources in the key packaging and test technologies that support the rapidly growing market for smartphones and tablets, and today we are well-positioned to take advantage of significant growth opportunities in mobile communications and our other end markets,” said James J. Kim, Amkor’s executive chairman of the board of directors. “Steve Kelley has a wealth of experience helping major global semiconductor companies grow revenues and increase profitability. With his strong record of success, deep customer knowledge and great drive, Steve is the ideal CEO to lead Amkor.”

Most recently, Kelley served as chief executive officer of Scio Diamond Technology Corporation, an industrial diamond technology company, and as a senior advisor to Advanced Technology Investment Company, the Abu Dhabi-sponsored investment company that owns GLOBALFOUNDRIES, a full service semiconductor foundry. Kelley, 50, has more than 25 years of experience in the global semiconductor industry, including as executive vice president and chief operating officer of Cree, Inc. from 2008 to 2011, as vice president/general manager of display, standard logic, linear and military businesses at Texas Instruments, Inc. from 2003 to 2008, in various positions with Philips Semiconductors from 1993 to 2003 including senior vice president and general manager, and in various positions with National Semiconductor Corporation and Motorola Semiconductor. Kelley holds a B.S. in chemical engineering from Massachusetts Institute of Technology and a J.D. from Santa Clara University.

“I’m very excited to join the Amkor team,” said Kelley. “Throughout its history, Amkor has been a pioneer and technology leader, and I look forward to the opportunity to build on that success.”

Kim also commented on the retirement of Joyce.

“Ken has had a remarkable career, including over 15 years of service to Amkor,” he said. “Today, Amkor is well-positioned for success with industry-leading technology in our key end markets, and the entire Board of Directors joins me in thanking Ken for helping to lead us here. We are fortunate that Ken has agreed to be available to work with Steve over the coming months to ensure a smooth transition.”

Amkor is a leading provider of semiconductor packaging and test services to semiconductor companies and electronics OEMs.

Rudolph Technologies, Inc., a provider of process characterization, photolithography equipment and software for the semiconductor, FPD, LED and solar industries, announced today that it has purchased selected assets, including a strong patent portfolio, relating to metrology capability from Tamar Technology, Newbury Park, Calif. The addition of Tamar’s advanced metrology technologies to Rudolph’s existing inspection and metrology systems will allow the company to address the emerging need for fast, precise three-dimensional (3D) measurement capabilities in the rapidly-growing advanced packaging market sector.

“The purchase of these assets adds new capabilities to our technology portfolio, which addresses an emerging need for 3D measurements to control copper pillar bumping in advanced packaging processes,” said Michael Jost, vice president and general manager of Rudolph’s Inspection Business Unit. “Tamar’s technology is already well-known and widely used. Integrating it into our NSX and F30 inspection and metrology platforms adds critical capability and value to an established and reliable tool set. Several customers brought this exclusive technology to our attention; and it was readily apparent that the acquisition of these assets would significantly enhance the breadth of our advanced packaging solutions. In addition, this purchase gives Rudolph a significant patent portfolio that we plan to fully leverage. The integration work is essentially complete and we expect to receive initial system orders in the coming months.”

Copper pillar bumping for flip-chips has been forecast to grow at a 35 percent CAGR from 2010 to 2018. While copper pillar bumping processes are the most significant immediate application, Tamar’s products are capable of critical measurements required in several packaging applications. For example, one application uses infrared light to measure TSV depth from the backside of the wafer, thus avoiding the limitations on via aspect ratio encountered by most frontside measurement approaches.

“We expect the addition of these unique and proprietary capabilities to positively influence both unit volume and margins while helping Rudolph to maintain our #1 market share position in this rapidly growing sector,” said Jost.

Terms of the transaction were not disclosed. However, the company noted that the asset purchase agreement includes an earn-out contingency that, if met, would bring the total transaction value to approximately $10 million. The company also noted that it expects the transaction to be accretive to earnings within the first 12 months.

Tamar Technology, based in Newbury Park, California, is a precision metrology company specializing in systems for the semiconductor, hard disk drive and medical device industries.  Rudolph provides a full-fab solution through its families of proprietary products that provide critical yield-enhancing information, enabling microelectronic device manufacturers to drive down the costs and time to market of their products.

 Electro Scientific Industries, Inc. today announced it had signed a definitive agreement to acquire the Semiconductor Systems business of GSI Group, Inc., a supplier of precision photonics, laser-based solutions and precision motion devices to the medical, industrial, scientific, and electronics markets. Based in Bedford, Massachusetts, the Semiconductor Systems business provides products in laser marking and trimming of semiconductor wafers and hybrid circuits. The parties expect the transaction to close within thirty days.

Both ESI and Semiconductor Systems have decades of laser-based wafer processing experience. The Semiconductor Systems’ wafer marking products are positioned to capitalize on the industry-wide transition to 450mm wafer diameters and are complementary to ESI’s commitment to enabling 3D semiconductor packaging.

This acquisition will add approximately $20-30 million of annual revenue to ESI. It is expected to add $0.05 to $0.10 to non-GAAP earnings per share in the first year.

“The GSI Semiconductor Systems business is an excellent operational fit with ESI. The business brings a strong technical team, broadens our revenue base with our semi customers, and strengthens our Semiconductor Division,” stated Nick Konidaris, CEO of ESI. “With complementary capabilities but almost no product overlap, this acquisition broadens our product portfolio and allows ESI to provide a more complete set of laser-based manufacturing solutions to our semiconductor customers.”

“We are pleased to complete this transaction, which ultimately enables GSI to focus our growth investments on our OEM component businesses,” said John Roush, CEO of GSI. “We believe this outcome is the best result for customers, employees and shareholders of both companies. The GSI team will work closely with our counterparts at ESI to ensure a smooth transition of ownership of the Semiconductor Systems business.”

ESI is a leading supplier of innovative, laser-based manufacturing solutions for the microtechnology industry. Their focus is on developing the precise structuring of micron to submicron features in electronic devices, semiconductors, LEDs and other high-value components. Founded in 1944, ESI is headquartered in Portland, Ore., with global operations from the Pacific Northwest to the Pacific Rim.

Silex Microsystems, the world’s largest pure-play MEMS foundry, and BroadPak, a provider of ultra-high performance 2.5D silicon interposer and 3D integration technologies, today announced the immediate availability of their jointly developed silicon interposer solution in high-volume manufacturing. Leveraging the advanced interposer co-design methodology and system integration expertise of BroadPak with the proven interposer manufacturing capabilities of Silex, this new solution delivers a cost-effective, ultra-high performance, reliable and high-yield silicon interposer that will enable a broader market to realize the benefits of 2.5D packaging. 

 While market analyst firm Yole Dévelopement expects the market for interposers to grow by 88 percent annually through 2017, Silex and BroadPak believe their partnership can accelerate this market adoption by overcoming the cost, engineering, reliability and supply chain bottlenecks.  3D-IC designs are widely recognized as the next step towards meeting the growing performance requirements such as increased bandwidth, reduced latency, and lower power.  2.5D silicon interposers, which are double-sided die used to stack chips side-by-side, have emerged as the most effective way to accelerate the adoption of 3D-IC, but these solutions are costly and complex, which presents significant design, integration, reliability and supply chain challenges. Recognizing these bottlenecks, Silex and BroadPak believe their new 2.5D silicon interposer product solves these hurdles that have prevented many companies from participating in this space.

“This partnership is a critical step in enabling companies to benefit from silicon interposers because most companies don’t have the integration techniques and methodologies to even start a 2.5D IC design and the current solutions have been too costly and high-risk to implement,” said Peter Himes, Vice President of Marketing and Strategic Alliances for Silex Microsystems.  “The combined Silex/BroadPak solution opens up this market to a very large portion of customers that have been unable to compete in this space due to overwhelming cost, engineering and integration challenges.”

“BroadPak and Silex have created a technical solution and the supply chain infrastructure that the industry has been waiting for,” said Farhang Yazdani, President and CEO of BroadPak. “To date, silicon interposer technology has been limited to a very small number of companies. We are now enabling the mass adoption of silicon interposer by lowering the cost and providing the co-design, heterogeneous integration and the required supply chain infrastructure in a complete package.”

 The Silex/Broadpak finished product consists of a robust interposer for 2.5D packaging, which has been designed and characterized for thermal-stress and signal integrity performance by BroadPak and also optimized for manufacturing by Silex. The unique challenges of 2.5D/3D-IC packaging require special engineering expertise to deliver cost effective solutions to meet the reliability, warpage and signal/power integrity requirements of the packaged components as well as an optimized and robust manufacturing process.

GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GLOBALFOUNDRIES’ leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today’s electronic devices.

TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers.

GLOBALFOUNDRIES utilizes a “via-middle” approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, GLOBALFOUNDRIES engineers have developed a proprietary contact protection scheme. This scheme enabled the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

“Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality,” said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. “Our next step is to leverage Fab 8’s advanced TSV capabilities in conjunction with our OSAT partners to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain.”

As the fabless-foundry business model evolves to address the realities of today’s dynamic market, foundries are taking on increasing responsibility for managing the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs. To help address these challenges, GLOBALFOUNDRIES is engaging early with partners to jointly develop solutions that will enable the next wave of innovation in the industry. This open and collaborative approach will give customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.