Category Archives: 3D Integration

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. and Benjamin S. Louie of Zeno Semiconductor blog about dimensional scaling as it relates to EUV and future per transistor device cost.

At the IEEE International Solid-State Circuit Conference, the issue of dimensional scaling as it relates to EUV and future per transistor device cost was an important topic in the plenary session. One important, and perhaps overlooked, aspect of the industry’s scaling issue relates to the future of the SRAM bit-cell within this framework of dimensional scaling. We would like to shine some light on this impending issue.

As widely reported in the industry and articulated by ASML’s Executive VP & CTO Martin van den Brink at ISSCC 2013, there is substantial evidence that without EUV the cost of logic transistors is most likely going up with scaling. One slide he used to illustrate this is below:

Source: ASML

The above slide arrived after Martin had presented another non-encouraging slide, showing the same view from three companies: a Broadcom chart of increasing cost per gate correlated with dimensional scaling, together with the now famous Nvidia chart of no more crossover of transistor cost below 28nm, and third a GlobalFoundries chart showing some limited value for EUV.

 

 

 

We may attribute Martin statements to ASML interest in promoting EUV, but since ASML has already received significant EUV participation from INTEL, Samsung and TSMC, it might indicate further bumps are on the road to bringing EUV to market. We don’t know if EUV will ever become real, but we do know very well that it is been delayed, and delayed again, and delayed again. It was made public recently that EUV has probably already missed the 10nm process node -“10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries.

An even more interesting slide was presented by van den Brink:

This chart brings up an important aspect of dimensional scaling that has not been discussed much before – the scaling of the SRAM bit-cell.  According to this chart, the SRAM bit-cell size might not be reduced from the 20nm to 10 nm node, and might even get larger at 7nm as it may need more than 8 transistors. (Sound familiar? Fabs are doing the same with BEOL metallization scaling…little or none).

Modern logic devices demand a significant amount of embedded SRAM. In fact, more than 50% of the typical logic device area is allocated for these SRAM as illustrated by the following chart of Semico (June, 2010).

The dominant embedded SRAM bit-cell architecture has been the 6 transistor cell (6T). And for many years this very cell has been hand-crafted using special design rules independently developed by foundries for every new technology node. It makes sense: the SRAM cell is a unique structure that does not obey normal logic design rules as it drives output against output anytime a write cycle is being performed. In many cases it is the SRAM cell that is the most sensitive portion of the logic device to process parameter variations and this sensitivity greatly impacts end device yield.

It well known that scaling the SRAM bit-cell has become harder and harder. Some vendors have already moved away from the 6T bit-cell in preference to the 8T (eight transistors) bit-cell.  ISSCC 2013 had a significant number of papers that were presented using 8T SRAM.  The few papers who kept the 6T SRAM embedded in their logic devices were forced to add read/write support circuits and additional overhead to enable the 6T bit-cell to function reliably.

Since SRAM bit scaling is now not able to keep up with logic scaling, the overall end device cost scaling could be even more disappointing than the transistor or gate cost illustrations above. 

Of course, well aware of this trend, IBM has been promoting their embedded DRAM solution for years. In the recent Common Platform Forum Dr. Gary Patton, VP, IBM Semiconductor R& D Center, was very pleased to share that in their 32nm product line the use of the embedded DRAM has given IBM the equivalent of a process node scaling benefit. Yet, as of now, most other vendors have not adopted eDRAM due to the process complexity and cost it adds to the logic process. It fair to assume that the appetite for eDRAM will not grow with dimensional scaling as the DRAM capacitor will be very hard to scale, the extra power for supporting DRAM will not be available and the cost of advance process development to add in extra complexity will be too high.

Accordingly we can learn from the recent ISSCC that dimensional scaling is facing the cost challenges we were aware of before in addition to new challenges that we might not have been aware of: the cost and the active/passive power handicaps due to the incompatibility of the 6T SRAM  bit-cell with scaling.

As we have suggested before, now that monolithic 3D is practical, we could advance and maintain Moore’s Law by augmenting dimensional scaling with 3D IC scaling. We could enjoy depreciated equipment charges for more years and much lower R&D engineering outlays that would bring down production and development costs, and also enjoy improvements to power and performance.

Another exciting option is to replace the 6T SRAM bit-cell with the 1T bi-stable floating body memory cell invented by Zeno Semiconductor.  The Zeno bit-cell provides two stable states, analogous to an SRAM while only consuming ~20% area of a traditional 6T SRAM and requires considerably less power.  The area and power savings over a traditional 6T SRAM improve further with scaling.  Most excitingly the Zeno bit-cell is compatible with existing logic processes. 

About the authors

Zvi Or-Bach is a well-known serial entrepreneur. He founded eASIC in 1999 and served as the company’s CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB in three successive rounds. Or-Bach also founded Chip Express in 1989 (recently acquired by Gigoptix) and served as the company’s President and CEO for almost 10 years. In 2009 he founded and incorporated MonolithIC 3D Inc., a company that developed and patented a technology breakthrough for practical monolithic 3D-ICs.

Benjamin S. Louie has more than 16 years of experience in memory design including NOR Flash, NAND Flash and MRAM.  Most recently he led design efforts at Magsil, an MRAM IP company.  Prior to Magsil, Ben worked as a Design Manger at Micron Technology where he led the design development of Micron’s NAND program. 

FlipChip International (FCI), a developer of flip chip bumping, Wafer Level and embedded die packaging and EZconn Czech a.s. announced a partnership agreement today.  FCI will provide sales and marketing services to promote and leverage EZconn’s packaging technologies and services based in their Trutnov facility in the Czech Republic, thereby extending support for leading edge wafer level bumping and module assembly. EZconn will also support FCI’s advanced packaging roadmap for 2.5D and 3D WLCSP and flip chip solutions for its global customers with this Partnership.

This strategic partnership will provide a platform for the promotion of the EZconn Czech a.s. Wafer Level Micro Assembly Technology and Services including volume production of customer specific micro-modules, optical diodes and transceivers of all kinds.

"We are excited about this partnership which combines EZconn’s advanced wafer level assembly technologies with FCI’s Wafer Level Packaging technologies creating a unique capability for next generation 2.5D and 3D packaging," Bob Forcier, FCI President and CEO said, "The technology crossovers of these two technologies will enable further reductions in the Z axis and X-Y axis mechanical envelopes which is paramount to our mutual customers quest for miniaturization of their products in a variety of global markets."

"We are very pleased to enhance and extend our product portfolio with this partnership with FCI," Petr Tauchman, EZconn Czech a.s. Managing Director, said. "There are synergies in our respective Product and Technology Roadmaps that will provide excellent advanced packaging solutions for our customers."

EV Group, a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has installed a fully automated 300mm system from EVG’s Gemini product family of integrated wafer bonding clusters to a leading Chinese semiconductor foundry. This customer will use the system for 3D IC integration and advanced packaging—two high-volume applications for which EVG’s wafer bonding solutions are frequently used.

"This order from one of the largest Chinese foundries further cements EV Group’s position as the market and technology leader in wafer bonding for leading-edge applications," stated Hermann Waltl, executive sales and customer support director at EV Group. "China is an important market for us, and this order is further testament to our continued success in penetrating leading high-volume microelectronics manufacturers in China—from advanced substrate suppliers to light emitting diode (LED) and semiconductor device makers."

EVG won this order following a competitive bid with other leading process equipment suppliers.  Reasons cited by the customer for choosing EVG included high alignment accuracy, comprehensive process development and support, successful demo results in EVG cleanrooms, unmatched expertise in wafer bonding and other high-volume process solutions, and a technology roadmap that is strongly aligned with that of the customer. 

The EVG Gemini is a fully automated and integrated platform for wafer conditioning, wafer-to-wafer alignment and wafer bonding.  This highly modular design provides customers with a highly flexible solution that can integrate all of EVG’s technology solutions in one platform with minimized footprint.  Configurations can include the option of EVG’s clean modules, low temperature plasma activation modules, SmartView align modules with integrated bond capability, as well as dedicated bond modules.

Tokyo-based Asahi Glass Co., Ltd. and nMode Solutions Inc. of Tucson, Arizona, have invested $2.1 million to co-found a subsidiary business, Triton Micro Technologies , to develop via-fill technology for interposers, enabling next-generation semiconductor packaging solutions using ultra-thin glass. The new company, headquartered in Tucson with a manufacturing facility planned in California, will combine nMode’s interposer technology for electrically connecting semiconductor devices with AGC’s materials technology and micro-hole drilling techniques to produce 2.5-dimensional (2.5D) and three-dimensional (3D) through-glass-via (TGV) interposers needed for advanced semiconductor devices.

To achieve the next generation in high-density semiconductor packaging, interposer technologies are needed to form the high number of electrical connections between a silicon chip and a printed circuit board. Interposers allow high packaging integration in the smallest available form factors.

Triton Micro Technologies will manufacture ultra-thin glass interposers using a high-efficiency continuous process that lowers costs and helps to commercialize the widespread use of interposers. The company will draw upon nMode’s intellectual property and AGC’s proven carrier-glass technology and via-hole drilling methodologies to fabricate its interposers. Triton then will apply its proprietary technology to fill the high-aspect-ratio via holes with a copper paste that has the same coefficient of thermal expansion as glass. This reduces the potentially damaging effects of thermal stress during manufacturing and long-term use. Triton’s process creates high-quality electrodes within the interposer to provide the electrical interface capable of accommodating advanced, high-density ICs.

Triton’s interposers are compatible with wafers having diameters from 100mm to 300mm and thicknesses of 0.7mm and below. The company also can design and manufacture customized solutions for unique applications.

“The global semiconductor industry recognizes that silicon is approaching its performance limits as an interposer material, but the need remains to create smaller, more efficient packages for today’s and tomorrow’s high-performance ICs,” said Tim Mobley, CEO at Triton. “Our technology allows us to achieve known-good-die testing at the highest levels of packaging integration, faster cycle times and the lowest cost per unit in the market.”

Despite its high 19% CAGR, Flip-chip is not new – in fact, it was first introduced by IBM over 30 years ago. As such, it would be easy to consider it an old, uninteresting, mature technology, but this is far from true. Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3D IC and 2.5D. No matter what packaging technology you’re using, a bumping step is always required at the end. In 2012, bumping technologies accounted for 81% of the total installed capacity in the middle end area. That’s big. Really big. So big that it represents 14M+ 12’’eq wafers – and fab loading rates are high as well, especially for the Cu pillar platform (88%). Flip-Chip is also big on value: in 2012 it was a $20B market (making it the biggest market in the middle-end area), and Yole Développement expects it to continue growing at a 9% clip, ultimately reaching $35 billion by 2018.

Flip-Chip capacity is expected to grow over the next five years to meet large demand from three main areas:

1) CMOS 28nm IC, including new applications like APE and BB

2) The next generation of DDR Memory

3) 3DIC/2.5D interposer using micro-bumping.

Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.

In addition to traditional applications which have used Flip-Chip for a while now (laptop, desktop and their CPUs, GPUs & Chipsets – which are growing slowly but still represent significant production volumes for Flip-Chip), Yole Développement’s analyst expects to see strong demand from mobile & wireless (smartphones), consumer applications (tablets, smart TV, set top box), computing and high performance/ industrial applications such as network, servers, data centers and HPC.

The new “Flip-Chip packaged ICs” are expected to radically alter the market landscape with new specific motivations that will drive demand for wafer bumping.

“In the context of 3D integration and the ‘More than Moore’ approach, Flip-Chip is one of the key technology bricks and will help enable more sophisticated system on chip integration than ever before,” says Lionel Cadix, Market & Technology Analyst, Advanced Packaging, at Yole Développement.

Flip-Chip is being reshaped by a new kind of demand that is hungry for Cu pillars and micro-bumps, which are on their way to becoming the new mainstream bumping metallurgy for die interconnection.

Meanwhile, Cu pillar is fast becoming the interconnect of choice for advanced CMOS (≤28nm), memory, and micro-bumping for 2.5D interposer and 3D IC.

In addition to studying mainstream bumping technologies, the Yole Développement report focuses on Cu pillar bumping, which is becoming increasingly popular for a wide variety of applications. The massive adoption of Cu pillars is motivated by a combination of several drivers, including very fine pitch, no UBM needed, high Z standoff, etc. Cu pillar Flip-Chip is expected to grow at a 35% CAGR between 2010-2018 in terms of wafer count. Production is already high at Intel – and by 2014, more than 50% of bumped wafers for Flip-Chip will be equipped with Cu pillars.

As early as 2013, micro-bumping for 2.5D & 3D IC, in conjunction with new applications like APE, DDR memory, etc., will boost Flip-Chip demand and create new challenges and new technological developments (see figure on the left). Today, Flip- Chip is available in a wide range of pitches to answer the specific needs of every application. The ultimate evolution in bumping technologies will consist of directly bonding IC with copper pads. 3D integration of ICs using this bump-less Cu-Cu bonding is expected to provide an IC-to-IC connection density higher than 4 x 105 cm-2, making it suitable for future wafer-level 3D integration of IC in order to augment Moore’s Law scaling.

Taiwan is the #1 location for Flip-Chip bumping

The major OSATs are preparing to produce fcBGA based Cu pillar packages and won’t limit the reach of cu pillar bumping to fcCSP. This will allow every company involved in CPU, GPU Chipset, APE, BB, ASIC, FPGA and Memory to access Cu pillar Flip-Chip technology. Cu pillar capacity is expected to grow rapidly over the 2010 – 2014 timeframe (31% CAGR), hitting ~9M wspy by 2014 and supporting the growing demand for micro-bumping and advanced CMOS IC bumping.

In the mutating middle-end area, CMOS foundries now propose wafer bumping services (TSMC, GLOBALFOUNDRIES, etc.), as opposed to bumping houses, which are dedicated to bumping operations (FCI, Nepes, etc.), and OSATs, which keep investing in advanced bumping technologies. In 2012, OSATs owned 31% of installed capacity in ECD solder bumping and 22% of installed capacity in Cu pillar bumping. A full overview of 2012 installed capacities for all bumping platforms is provided in this report.

Concerning geography, Taiwan has the biggest overall bumping capacity (regardless of the metallurgy), with important capacity coming from foundries and OSAT factories. Taiwan currently leads the outsourcing “solder & copper” Flip-Chip wafer bumping market. Flip-Chip market growth, spurred on by the emergence of the “middle-end” environment, has challenged traditional “IDM vs. fabless” supply chain possibilities more than ever before.

3-D integration with nanostructuresResearchers at North Carolina State University have developed a new type of nanoscale structure that resembles a “nano-shish-kebab,” consisting of multiple two-dimensional nanosheets that appear to be impaled upon a one-dimensional nanowire. However, the nanowire and nanosheets are actually a single, three-dimensional structure consisting of a seamless series of germanium sulfide (GeS) crystals. The structure holds promise for use in the creation of new, three-dimensional (3-D) technologies.

The researchers believe this is the first engineered nanomaterial to combine one-dimensional and two-dimensional structures in which all of the components have a shared crystalline structure.

Combining the nanowire and nanosheets into a single “heterostructure” creates a material with both a large surface area and the ability to transfer electric charges efficiently. The nanosheets provide a very large surface area, and the nanowire acts as a channel that can transmit charges between the nanosheets or from the nanosheets to another surface. This combination of features means it could be used to develop 3-D devices, such as next-generation sensors, photodetectors or solar cells. This 3-D structure could also be useful for developing new energy storage technologies, such as next-generation supercapacitors.

“We think this approach could also be used to create heterostructures like these using other materials whose molecules form similar crystalline layers, such as molybdenum sulfide (MoS2),” says Dr. Linyou Cao, an assistant professor of materials science and engineering at NC State and co-author of a paper on the research. “And, while germanium sulfide has excellent photonic properties, MoS2 holds more promise for electronic applications.”

The process, Cao says, is also attractive because “it is inexpensive and could be scaled up for industrial processes.”

To create the nano-shish-kebabs, the researchers begin by creating a GeS nanowire approximately 100 nanometers in width. The nanowire is then exposed to air, creating nucleation sites on the wire surface through weak oxidation. The nanowire is then exposed to GeS vapor, which forms into two-dimensional nanosheets at each of the nucleation sites.

“Our next step is to see if we can create these heterostructures in other materials, such as MoS2,” Cao says. “We think we can, but we need to prove it.”

The paper, Epitaxial Nanosheet–Nanowire Heterostructures, was published online Feb. 18 in Nano Letters. The lead author is Dr. Chun Li, a former postdoctoral researcher at NC State. Co-authors are Yifei Yu, a Ph.D. student at NC State; Cao; and Dr. Miaofang Chi of Oak Ridge National Laboratory. The research was supported by the U.S. Army Research Office.

Research and Markets has announced the addition of the "Global 3D IC Market 2012-2016" report to their offering.

TechNavio’s analysts forecast the global 3D IC market to grow at a CAGR of 19.7 percent over the period 2012-2016. One of the key factors contributing to this market growth is the huge demand for memory-enhanced applications. The global 3D IC market has also been witnessing the increase of multi-chip packaging. However, the thermal conductivity issues could pose a challenge to the growth of this market.

The key vendors dominating this market space are Advanced Semiconductor Engineering Co. (ASE), Samsung Electronics Co. Ltd., STMicroelectronics N.V., and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). Other vendors mentioned in the report include Elpida Memory Inc., IBM Corp., Intel Corp., and Micron Technology Inc.

“One of the emerging trends in the global 3D integrated circuit (IC) market is multi-chip packaging. In this type of packaging more transistors can be packed into a single 3D IC,” an analyst from TechNavio’s Hardware team said, commenting on the report.  “This type of packaging is very important for memory-enhanced applications because this approach enables improved interaction between the memory and the processor. It is expected that multi-chip packaging will be a promising approach for most applications in the future. Thus, vendors consider that multi-chip packaging is one of the crucial trends that will lead to the growth of the Global 3D IC market.’

According to the report, one of the major growth drivers is the increasing demand for 3D ICs in memory products (flash memory and DRAM). 3D ICs are able to improve the performance and reliability of memory products and can also help reduce their cost and size.

TechNavio’s report, the Global 3D IC Market 2012-2016, was prepared based on an in-depth market analysis with inputs from industry experts. The report covers the Americas, and the EMEA and APAC regions; it also covers the global 3D IC market landscape and its growth prospects in the coming years. The report also includes a discussion of the key vendors operating in this market. The study was conducted using an objective combination of primary and secondary information including inputs from key participants in the industry. The report contains a comprehensive market and vendor landscape in addition to a SWOT analysis of the key vendors.

The relentless march of process technology brings more integration and performance. IBM’s System z processor leads the charge at ISSCC 2013 clocking in at 5.7GHz and with 2.75B transistors.

The chip complexity chart below shows the trend in transistor integration on a single chip over the past two decades. While the 1 billion transistor integration mark was achieved some years ago, we now commonly see processors with beyond 2B transistors on a die.

Leveraging sophisticated strategies to lower leakage and manage voltage, variability and aging, has bolstered the continuing reduction in total power dissipation. This is helping rein in the increase in energy demands from PCs, servers, and similar systems. As power reduction becomes mandatory in every application, the trend towards maintaining near-constant clock frequencies also continues as shown below in frequency trends plot. This will yield solutions with less cost and cooling demands, resulting in greener products in the future.

Processors are choosing to trade off performance by lowering supply voltage. The performance loss of reduced voltage and clock frequency is compensated by further increased parallelism. Processors with more than eight cores are now commonplace. This year at ISSCC 2013, a 24-core processor from Fudan University will be presented as noted in the core count trend chart below.

In addition to the trend to integrate more cores on a single chip, multiple die within a single package are appearing. In ISSCC 2013, IBM will present a multi-chip module with six CPUs and two embedded DRAM cache chips. As well, dedicated co-processing units for graphics and communications are now commonly integrated on these complex systems-on-chip. Design of these SoCs requires broad collaboration across multiple disciplines including circuits, architecture, graphics, process technology, package, system design, energy efficiency and software. New performance and power-efficient computing techniques continue to be introduced at targeted, critical applications such as floating point and SIMD.

As technology continues to scale to finer dimensions, large caches are being integrated into microprocessor die.

Methods to communicate within-die as well as cross-die are becoming increasingly important. This is being driven by two trends: (1) 3D integration continues to grow in interest and (2) intra-die communications become more challenging with process scaling due increases in delay per unit interconnect length. Work on bringing package-level inter-chip transport onto the die has been gaining in popularity and we see this trend continuing.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.

Imagers

Since 2010, there has been growth beyond expectations in the adoption of mobile devices, such as smart phones and tablets, which has called for larger volumes of CMOS image sensor chips to be produced. The resolution and miniaturization races are ongoing, and performance metrics are also becoming more stringent. In addition to the conventional pixel shrinkage, a “more than Moore” trend is increasingly evident. Resolutions of over 20 Mpixels are commercially available for mobile devices employing enhanced small-size pixels. Thanks to the innovative readout and ADC architectures embedded at the column and chip levels, data rates approaching 50Gb/s and a noise floor below single electron have been demonstrated. In addition to the conventional applications, ultra-low-power vision sensors, 3D, high-speed, and multispectral imaging are the front-running emerging technologies.

Back-side Illumination (BSI) is now the mainstream technology for high-volume, high-performance mobile applications, 1.12μm BSI pixels are available, and the industry is potentially moving towards 0.9μm pixel pitch and below. Additional innovative technologies outside of the traditional scaling include advanced 3D stacking of a specialized image sensor layer on top of deep-submicron digital CMOS (65nm 1P7M) using through silicon vias (TSVs) and micro-bumps. The importance of digital-signal-processing technology in cameras continues to grow in order to mitigate sensor imperfections and noise, and to compensate for optical limitations. The level of sensor computation is increasing to thousands of operations-per pixel, requiring high-performance and low-power digital-signal-processing solutions. In parallel with these efforts is a trend throughout the image sensor industry toward higher levels of integration to reduce system costs.

Ultra-low-power vision sensors are being reported in which more programmability and computation is performed at the pixel level in order to extract scene information such as object features and motion.

Lightfield/plenoptic commercial cameras, which have been available since 2010, are now gaining popularity and are being marketed for 3D imaging and/or all-in-focus 2D imaging. On-chip stereoscopic vision has been demonstrated through digital micro lenses (DML), paving the way to next-generation passive 3D imaging for mobile and entertainment applications, e.g. through gesture control user interfaces.

Significant R&D effort is being spent on active 3D imaging time-of-flight (TOF) applications to support requirements from autonomous driving, gaming, and industrial applications, addressing open challenges like background light immunity, higher spatial resolution, and longer distance range. Deep-submicron CMOS single-photon avalanche diodes (SPADs) have been developed by several groups using different technology nodes. They are now capable of meeting the requirements for high resolution, high timing accuracy by employing highly parallel time-to-digital-converters (TDCs) and small pixel pitch with better fill factor.

Ultra-high-speed image sensors for scientific imaging applications with up to 20Mfps acquisition speed have been demonstrated.

Multispectral imaging is gaining a lot of interest from the image sensor community: several research groups have demonstrated fully CMOS room-temperature THz image sensors, and a hybrid sensor capable of simultaneous visible, IR, and THz detection has been reported.

The share of CCDs continues to shrink in machine vision, compact DSC and security applications. Only for high-end digital cameras for astronomy and medical imaging do CCDs still maintain a significant market share.

Sensors & MEMS

A 4×4 array of sensing cells, developed by Dr. Peng Peng of Seagate Technology, from Flexible Microtactile Sensor for Normal and Shear Elasticity (IEEE Transactions on Industrial Electronics)

MEMS inertial sensors are finding widespread use in consumer applications to provide enhanced user interfaces, localization, and image stabilization. Accelerometers and gyroscopes are being combined with 3D magnetic-field sensors to form nine-degree-of-freedom devices, and pressure sensors will eventually add a 10th degree. The power consumption of such devices is becoming sufficiently low for the sensor to be on all the time, enhancing indoor navigation. There have been further advances in heterogeneous integration of MEMS with interface circuits in supporting increased performance, larger sensor arrays, reduced noise sensitivity, reduced size, and lower costs.

To address the stringent requirements of automotive, industrial, mobile, and scientific application, MEMS inertial sensors, pressure sensors and microphones are becoming more robust against electromagnetic interference (EMI), packaging parasitics, process voltage temperature (PVT) variations, humidity, and vibration.

Sensor interfaces achieve increasingly high resolution and dynamic range while maintaining or improving power or energy efficiency. This is achieved through techniques such as zooming, non-uniform quantization, and compensation for baseline values.

New calibration approaches, such as voltage calibration, are being adopted for BJT-based temperature sensors to reduce cost. In addition to thermal management applications (prevention of overheating in microprocessors and SoCs), temperature sensors are also increasingly co-integrated with other sensors (e.g. humidity, pressure, and current sensors) and MEMS resonators for cross-sensitivity compensation. Alternative temperature-sensing concepts find their way into applications with specific requirements not easily addressed by BJTs: thermal diffusivity-based sensing for high-temperature applications; thermistor-based and Q-based concepts for in-situ temperature sensing of MEMS devices and for ultra-low voltage operation.

MEMS oscillators continue to improve; phase noise is now low enough for demanding RF applications, 12kHz-to-20MHz integrated jitter is now below 0.5ps, and frequency accuracy is now better than 0.5ppm. Consumer applications are adopting new low-power and low-cost oscillators.

Biomedical

There have been continuous achievements in the area of ICs for neural and biopotential interfacing technologies. Spatial resolution of neural monitoring devices is being reduced utilizing the benefits of CMOS technology. IC providers are increasing their component offerings towards miniaturization of portable medical devices.

Telemedicine and remote-monitoring applications are expanding with support from IC manufacturing companies. The applications of such systems are not limited to services targeted for elderly or chronically ill patients; for example there are several technologies developed to enhance the way clinical trials are conducted by monitoring patient adherence and by improving data collection. Low power WiFi, and Bluetooth-low-energy is emerging as a standard wireless connection between portable communication services and wearable technology.

Smart biomolecular sensing is another major trend that marries solid-state and biochemical worlds together with the ultimate goal of enabling a more predictive and preventative medicine. With the help of the accuracy and parallelism enabled by CMOS technology, time, cost, and error rate of DNA sequencing may be significantly improved. Direct electronic readout may relax the need for complex biochemical assays. Similar trends are becoming increasingly evident in the space of proteomics and sample preparation.

Even for medical imaging, there is a trend from hospital imaging toward point-of-care and portable devices. A key example is in the space of portable high-resolution ultrasounds in which larger scientific imaging setups are being integrated onto the sensor by process technology (e.g. integrated spectral filters, CMUT). Another example is in the space of molecular imaging. The advent of silicon photomultipliers (SiPM) providing a solid-state alternative to PMTs enable the realization of PET scanners compatible with MRI, opening the way to new frontiers in the field of cancer diagnostics. More recently, SiPMs realized within deep-submicron CMOS technologies have allowed the integration at pixel- and chip-level of extra features, e.g. multiple timestamp extraction, allowing in perspective a dramatic reduction of the system cost.

Displays

The desire to put much higher-resolution and higher-definition displays into mobile applications is one of the display technology trends, and it is now opening a Full HD smartphone era.  440ppi high-definition displays are expected, even for 5-inch display sizes. Low-temperature polysilicon (LTPS) technology seems to have more merits over a-Si TFT technology. But a-Si TFT and oxide TFT technologies supported by compensating driver systems are being prepared to compete with it. Very-large-size LCD TVs over 84 inches, and UD (3840×2160) resolution are now the leading entertainment systems. 55-inch AMOLED TVs with Full HD resolution are also opening new opportunities in consumer applications.

As touch-screen displays for mobile devices become increasingly thin, capacitive touch sensors move closer to the display. The resulting in-cell touch displays come with reduced signal levels due to increased parasitics, and increased interference from the display and switched-mode chargers. Noise immunity is improved by adopting noise filtering and new signal modulation approaches.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.

Image by IBM ResearchDow Corning and IBM scientists unveiled a major step in photonics yesterday at the Photonics West conference, using a new type of polymer material to transmit light instead of electrical signals within supercomputers and data centers. This new silicone-based material offers better physical properties, including robustness and flexibility, making it ideal for applications in Big Data and for the development of future exascale computers, which are capable of performing a billion billion computations per second.

With exabytes of structured and unstructured data growing annually at 60 percent, scientists have been researching a range of technological advancements to drastically reduce the energy required to move all that data from the processor to the printed circuit board within a computer. Optical interconnect technology offers bandwidth and power efficiency advantages compared to established electrical signaling.

“Polymer waveguides provide an integrated means to route optical signals similar to how copper lines route electrical signals,” said Dr. Bert Jan Offrein, manager of the Photonics Research Group at IBM Research. “Our design is highly flexible, resistant to high temperatures and has strong adhesion properties – these waveguides were designed with no compromises.”

In a collaboration with Dow Corning, the scientists fabricated thin sheets of optical waveguide that show no curling and can bend to a 1 mm radius and is stable at extreme operating conditions including 85 percent humidity and 85°C. This new polymer, based on silicone materials, offers an optimized combination of properties for integration in established electrical printed circuit board technology. In addition, the material can be fabricated into waveguides using conventional manufacturing techniques available today.

“Dow Corning’s breakthrough polymer waveguide silicone has positioned us at the forefront of a new era in robust, data-rich computing, especially as we continue to collaborate with outstanding industry leaders like IBM,” said Eric Peeters, vice president, Dow Corning Electronic Solutions. “Optical waveguides made from Dow Corning’s silicone polymer technology offer customers revolutionary new options for transmitting data substantially faster, and with lower heat and energy consumption. We are confident that silicone-based board-level interconnects will quickly supersede conventional electronic signal distribution to deliver the amazing speeds needed for tomorrow’s supercomputers.”

A presentation, entitled Stable and Easily Processable Optical Silicones for Low-Loss Polymer Waveguides, given here by Brandon Swatowski, application engineer for Dow Corning Electronics Solutions, reported that fabrication of full waveguide builds can be completed in less than 45 minutes, and enable a high degree of process flexibility. Silicone polymer material, which is dispensed as a liquid, processes more quickly than competitive waveguide materials such as glass and does not require a controlled atmosphere chamber.

Swatowski’s presentation went on to say that waveguide builds based on the silicone polymer showed excellent adhesion to polyimide substrates. It also discussed how optical characterization of the new polymer waveguides silicones showed losses as low as 0.03 dB/cm, with environmental stability extending past 2,000 hours exposure to high humidity and temperature, and good performance sustained over 500 thermal cycles between -40°C and 120°C.