Category Archives: 3D Integration

Spending on research and development by semiconductor companies grew 7% in 2012 to a record-high $53.0 billion, even though the semiconductor market declined 1% to $317.6 billion, according to the 2013 edition of IC Insights’ McClean Report.  The increase lifted R&D spending by chip companies to 16.7% of total semiconductor sales in 2012, the highest level since the peak of 17.5% was reached in both 2008 and 2009.

For more than three decades, R&D spending as a percentage of total semiconductor sales has trended higher due to increasing costs associated with developing complex IC designs and creating next-generation process technologies to manufacture these circuits.  In the late 1970s and early 1980s, R&D spending as a percent of semiconductor sales by chip companies was typically 7-8%.  R&D-to-sales ratios grew to 10-12% of revenues by the early 1990s and then jumped to over 15% during the last decade, reaching a record 17.5% in 2008.

However, as shown in Figure 1, not all companies have seen a growing portion of sales consumed by R&D.  For example, Samsung’s R&D-to-sales ratio fell from a peak of 25% in 2001 to 8% in 2010 and has remained there since.  

Samsung’s semiconductor business is more capital-intensive than it is R&D-intensive because of the commodity nature of the DRAM and flash memory businesses in which it mainly participates.  As a result, since 2001, Samsung’s semiconductor sales have grown an average of 16% per year, while its R&D spending has increased at about one-third the rate (5%) and it’s capital expenditures have grown by an average of 19% annually.  The main focus of Samsung’s investments is in adding new fab capacity for large-diameter wafers (currently 300mm but heading toward 450mm later this decade).

Intel’s business is also capital-intensive.  Its spending on new fabs and equipment in each of the past two years was about $11 billion, which was only about $1 billion shy of what Samsung spent in each of those years.  Intel’s advanced microprocessors and other incredibly complex logic devices have very short life cycles.  Spending large amounts of money on research and development is part of its business model.  Intel’s $10.1 billion in semiconductor R&D spending in 2012 was more than 7x the amount spent by second-place Qualcomm!  In fact, Intel spent more than one-third of the combined $28.7B spent by the top-10 R&D spenders in 2012, according to the 2013 McClean Report.

Figure 1 also shows how much the industry’s largest pure-play foundry, TSMC, has been spending on R&D as a percent of sales over the past decade-and-a-half.  As the process technology needed for each new generation of ICs has become increasingly difficult to develop, fabless companies and the growing number of fab-lite companies have come to rely on TSMC not only for fabricating their wafers, but also for helping to bring their IC designs into existence.  As a result, TSMC’s R&D spending-to-sales ratio has been gradually climbing over the past 6-8 years.  TSMC’s spending ratio reached 8% in 2001, but that had a lot to do with the fact that its sales were hit hard by the industry recession that year.  Aside from a small dip in 2009, TSMC’s spending on R&D has grown every year since 1998 and at an average annual rate of 25%!  Over that same 1998-2012 timeperiod TSMC’s sales grew an average rate of 19% per year.

STATS ChipPAC Ltd. (SGX-ST: STATSChP) and United Microelectronics Corp. (NYSE: UMC; TWSE: 2303) announced the world’s first demonstration of TSV-enabled 3D IC chip stacking technology developed under an open ecosystem collaboration. The 3D chip stack, consisting of a wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, successfully reached a major milestone on package-level reliability assessment.

"The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models," said Shim Il Kwon, VP of Technology Innovation of STATS ChipPAC.

S.C. Chien, vice president of Advanced Technology Development at UMC, said, "We see no imperative to restrict 3D IC to a captive business model, as UMC’s development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach. This model should work especially well for our mutual 3D IC customers, as foundry and OSAT can utilize their respective core strengths during development and delivery, while customers can benefit from keeping supply chain management flexible and realize better transparency over technology access compared to closed, captive 3D IC business models."

Under the 3D IC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC’s 28nm poly SiON process flow. The know-how developed will be applied towards implementation on the foundry’s 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.

Renesas Electronics Corp. (TSE: 6723, Renesas) and J-Devices Corp. signed a memorandum of understanding regarding the transfer of the semiconductor back-end production business of three facilities operated by Renesas’ wholly owned manufacturing subsidiaries (the Hakodate Factory of Renesas Northern Japan Semiconductor, Inc. (Renesas Northern Japan), the Fukui Factory of Renesas Kansai Semiconductor Co., Ltd. (SKS), and the Kumamoto Factory of Renesas Kyushu Semiconductor Corp. (Renesas Kyushu)) and Renesas Northern Japan’s wholly owned subsidiary, Hokkai Electronics Co., Ltd. (Hokkai Electronics) to J-Devices.

This proposed transaction “aims at building a long-term, mutually beneficial relationship between the two companies as strategic partners in the semiconductor production business.” According to a press release.  The two companies plan to negotiate a final agreement and to complete the transfer in early June 2013.

The current employees of the transferred facilities will be “on loan” to J-Devices for a set period, under the premise that they will be reassigned to J-Devices on the basis of individual agreements in future. The Renesas products which will be manufactured at the facilities to be transferred will continue to be supplied by Renesas to customers with the quality, delivery schedules, service equal to or better than before even after the transfer.

In addition to the current seven facilities of J-Devices (Usuki, Oita Prefecture (Headquarters); Kitsuki, Oita Prefecture (Headquarters functions); Shibata-gun, Miyagi Prefecture; Aizuwakamatsu, Fukushima Prefecture; Miyawaka, Fukuoka Prefecture; Oita, Oita Prefecture; and Satsumasendai, Kagoshima Prefecture), the present transfer will add an additional three production facilities. This will make J-Devices one of the world’s top five OSAT (Outsourced Semiconductor Assembly and Test) service providers.

At the same time, the advantages gained as a long-term strategic partner of Renesas, including larger business scale, fusion of technical capabilities, and expanded product lineup, will enable J-Devices to improve cost competitiveness, technical capabilities, and product quality, allowing it to contribute to the continued development of the semiconductor industry as a world-top-level OSAT service provider and also providing substantial benefits for customers.

Renesas Electronics Corp. lays claim as world’s number one supplier of microcontrollers, and also offers SoC solutions and a range of analog and power devices. Business operations began as Renesas Electronics in April 2010 through the integration of NEC Electronics Corp. and Renesas Technology Corp., with operations spanning research, development, design and manufacturing for a wide range of applications. Headquartered in Japan, Renesas Electronics has subsidiaries in 20 countries worldwide. More information can be found at .

J-Devices is one of the largest independent semiconductor assembly and test company in Japan with seven factories in Japan. The original company (named Nakaya Microdevices) was established in 1970 and offers a broad lineup of packages including thermally enhanced BGA, CMOS sensor, leadframe and other original packages. J-Devices offers skilled package development as well as the full turnkey "one stop" service such as wafer sort, assembly, and final testing for consumer and automotive product.

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc., San Jose, CA, blogs about the evolution of 3D technology seen at the International Electron Devices Meeting. 

From our biased point of view we see the recent IEDM12 as a pivotal point for monolithic 3D. Here’s why:

We start with the EE Times article IEDM goes deep on 3-D circuits, starting with "Continuing on the theme of 3-D circuit technology addressed in an earlier post about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. .." and follow with a quote from the abstract to IEDMs short course "Emerging Technologies for post 14nm CMOS" organized by Wilfried Haensch, of IBM’s Watson Research Center: "Scaling the dimension was the key for the unprecedented success of the development of IC circuits for the last several decades. It now becomes apparent that scaling will become increasingly difficult due to fundamental physical limits that we are approaching with respect to power and performance trade-offs. This short course will give an overview of several aspects in this “end-of-scaling” scenario. …"

We then continue with statements made by Dr. Howard Ko, a Senior Vice President and General Manager of the Silicon Engineering Group of Synopsys in his 2013: Next-generation 3-D NAND flash technology article: "Yet there are a variety of developments in another type of 3-D scaling that are likely to have a similarly large impact on semiconductors in the near future – 3-D devices for NAND flash…. And as in planar CMOS logic, NAND flash technology has been progressively scaled to smaller feature sizes, becoming the process leader in driving the smallest line-widths in manufacturing as evidenced by the current 1x-nm (~19-nm) process node. Yet, despite plans to scale down to the 1y-nm (~15-nm) and possibly 1z-nm (~13-nm) nodes, the traditional planar floating gate NAND flash architecture is approaching the scaling limit, prompting the search for new device architectures.  Not to be upstaged by the planar to 3-D (FinFET) transition in logic devices, NAND flash has embarked on its own 3-D scaling program, whereby the stacking of bit cells allows continuous cost-per-bit scaling while relaxing the lateral feature size scaling."

In our recent blog 3D NAND Opens the Door for Monolithic 3D we discussed in detail the adoption of monolithic 3D for the next generations of NAND Flash. The trend was very popular subject of this year’s IEDM and is nicely illustrated by this older chart:

And accordingly the updated ITRS 2012 present the change from dimension scaling to monolithic 3D scaling as presented in the following slide.

This year’s IEDM brought up two of the driving forces behind the shift from dimensional scaling to monolithic 3D IC scaling, that we will detail below as #1 and #2.

The current 2D-IC is facing escalating challenges:

On-chip interconnect (#1): Dominates device power consumption, Dominates device performance, Penalizes device size and cost

Lithography (#2): Dominates Fab cost, Dominates device cost and diminishes scaling benefits, Dominates device yield, and Dominates IC development costs.

The problem with on-chip interconnect didn’t start today. This vintage Synopsys slide below clearly indicates that on-chip interconnect started to dominate overall device performance a decade ago:

In response, the industry has spent an enormous amount of money to convert from aluminum to copper and to low-K inter-metal dielectrics. But now, we have very few additional options left (perhaps air-bridge?) as illustrated by the following chart:

It shows that neither Carbon Nano Tube (CNT) nor Optical interconnect are better than copper, and that monolithic 3D still is the best path.

The practiced ‘band-aid’ fix so far has been throwing more transistors (they are getting cheaper, right? No longer. See father below) at the problem in the form of buffer and repeaters. But as we scale down we need exponentially more of these ban-aids as illustrated by the following:

Copper, however, is now reaching its inflection point as was articulated in a special session organized by Applied Materials attached to this IEDM, the 14 nanometer node is expected to be an inflection point. Quoting from the abstract:

"The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design. On December 11, 2012, Applied Materials, Inc. will host an important forum in San Francisco to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.” (emphasis added)

This had been illustrated before in the following chart:

And to make it crystal clear, IBM presented the following chart in its short course:

 
Power is now dominating IC design and clearly dimensional scaling does not improve the interconnect’s impact – see the following chart built from the ITRS Roadmap. The only effective path forward that addresses interconnect is monolithic 3D.

As for the second challenge – lithography – we start again with an old chart by Synopsys:

The implication is that any new node of dimensional scaling comes with escalating lithography costs; and sure enough, that’s what is happening. When litho costs are plotted over time, it fits a log-linear scale….this is not a sustainable trend.
The following chart illustrate the lithography escalating cost of equipment which directly reflect the wafer cost.

This resulted in the following slide by IBM at the GSA Silicon Summit 2012:

Quoting from the slide: "Net: neither per wafer nor per gate [are] showing historical cost reduction trends." Another EE Times IEDM12 article covering a keynote given by Luc van den Hove, chief executive of IMEC,  IEDM: Moore’s Law seen hitting big bump at 14 nm, repeats the same conclusion.

In fact, some vendors are already changing course accordingly. GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, ST Micro in the Fully Depleted Transistors Technology Symposium (11 December, 2012) during IEDM12 week also acknowledged that their 14nm node will have a 20nm node metal pitch, and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
So it would seem that also for lithographic reasons, the industry’s next generation path, and the continuation of Moore’s Law, would be achieved by leveraging the third dimension.

Now that monolithic 3D is feasible and practical, the time has come to move in this new direction, as has been nicely illustrated by this concluding chart below:

January 24, 2012 – Imec and PVA Tepla say they have achieved void detection in through-silicon vias at wafer level, after TSV copper plating, thanks to a nondestructive high-frequency scanning acoustic microscopy (SAM) technique. The method also can be applied to detect voids in TSVs during processing, they claim.

The initial focus of their work was to develop metrology for detecting voids after temporary wafer bonding of 3D wafers, which remains challenging because development of interface particles and voids can impact subsequent wafer thinning processes, as well as overall wafer thinning and tool performance.

To address this, PVA Tepla and imec developed an automated foup-to-foup, wafer-level process based on 200MHz SAM using Tepla

frederic-raynalFrederic Raynal, CTO, Alchimer

Looking at 2014, we see challenges and innovations in both the front-end semiconductor and 3D TSV markets.

In the front end, we are seeing a focus on further scaling to smaller nodes. For logic, TSMC has just announced it is ready for 16nm node, and Intel is ramping to 14nm. Industry experts question whether shrinking to 10nm will be feasible from a technology perspective. For example, at 10nm, most of the layers in copper interconnection must be between 2 and 4nm thick, which poses challenges for the technologies used in volume manufacturing. Controlling the thickness of single as well as dual damascene layers requires new technologies, such as electrografting, which is much more controllable and able to meet emerging requirements. We strongly believe that new technologies will need to be introduced for logic at the 10nm node and memory at the 16nm node, with ramp occurring at the 10nm node for the industry to maintain the path of Moore’s law.

We also expect to see 3D TSVs ramping to production in 2014. This is another area where innovation is needed that can meet demanding performance requirements while controlling costs, since cost is currently holding back widespread adoption of 3D-ICs. High-aspect-ratio (HAR) vias are a good candidate for new technology like electrografting, which is cost competitive compared with electrochemical deposition, chemical vapor deposition or physical vapor deposition, and delivers higher performance. For example, 40:1 aspect-ratio capabilities were recently demonstrated for electrografted barrier and seed layers, and 20:1 aspect ratio for fill processes.

It is widely expected that both the front-end and packaging areas of the semiconductor industry are poised for growth in 2014. Continued technology innovations will be a key driver in both areas in order to meet emerging performance requirements while successfully controlling cost and overcoming current roadblocks.

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January 18, 2013 – Ziptronix Inc. says it has signed a licensing agreement with Novati Technologies Inc. for the use of its patented direct bonding technologies, "direct bond interconnect" (DBI) and "direct oxide bonding (ZiBond).

Novati, the former SVTC facility in Austin which was acquired and relaunched by Tezzaron Semiconductor last fall, will use the technology for 3D stacking services and test. Tezzaron itself recently licensed Ziptronix’s DBI and ZiBond patents for use in 3D memory.

"Adding Ziptronix 3D process technologies to Novati’s existing wafer fabrication and testing facilities enables Novati to become the first open-platform, full-line foundry in the world offering 3D stacking services and test to all its customers," stated Dave Anderson, CEO of Novati Technologies. "We believe 3D is the new cutting edge of product development and we intend to continue our heritage as a contract R&D and lab-to-fab production facility enabling customers to cost-effectively prototype and test both 2.5D interposer and 3D designs with true, 3D integration and TSV interconnect."

"With our DBI, which contains interconnect at the bond interface, Novati can now provide technologically advanced services in many different markets at a lower cost and better performance compared to competing technologies also attempting 3D integration," added Ziptronix CEO Dan Donabedian.

By Joe Cestari, President, Total Facility Solutions

A major challenge facing the industry in the coming year is how to deliver products faster without affecting budgets or compromising safety and quality. The continued technology innovations will still support investment, and the ongoing move to mobile computing is a major driver in everyone’s forecast. The bottom line is that the industry will continue to advance, with Moore’s Law and economics driving market opportunity. From a US standpoint, we must continue to invest in emerging technologies and maintain our leadership status as an R&D center of excellence — driving investment is important. We can’t continue to afford to just innovate here then provide incentives to drive manufacturing overseas. We must find a way to keep heavily IP-weighted manufacturing in the US. What has happened in New York is a great example. Previously known for high labor rates, now some of the top manufacturers in the industry are bringing their manufacturing there, proving the US is not only an innovator, but a viable producer of a quality product at a lower total cost.

Most notably, in semiconductor manufacturing, 450mm is the next big opportunity. Issues of economic scale and complexity will force fab designers, OEMs and process integrators to investigate all open avenues in the search for solutions to the huge challenges that accompany 450mm. Next generation fabs present new challenges with respect to the design of the facilities, substrate handling, tool connection, chemical distribution, water and electrical systems and other areas. A transition to a bigger wafer size will bring many opportunities – some of which include helping to evolve the way we fabricate devices, introducing different chemistries, supporting greener, more sustainable builds and improving the efficiency of the entire process infrastructure.

Right now, with 450mm in its infancy, no one really knows what to expect, especially with regards to tool installation and hook up as design packages aren’t ready yet and in some cases the tools don’t even exist. The switch faces numerous challenges, as is the nature of the business. Competing vendors will no longer have to work only with the manufacturer, but with each other to settle a standard platform, an approach that could be challenging, yet beneficial all around. There has been a need for closer collaboration throughout the semiconductor industry for some time, starting from the facility construction process. The entire industry would benefit if suppliers were more integrated in the supply chain; and our goal of delivering products faster without affecting budgets or compromising safety and quality could be better realized.

Jim Mello, Vice President, Sales and Marketing, Entrepix, Inc.

The global economic difficulties are impacting the semiconductor industry more now than ever because the world has become increasingly interconnected and more consumer driven. The financial crisis in Europe, the "fiscal cliff" in the US and the slow down in China’s growth have made it more difficult for any one catalyst to push the markets in a positive direction. Ultimately, the semiconductor industry is caught up in this environment and its outlook continues to be mixed, which points towards a flat 2013. While smart phones and tablets will continue to drive the markets for communication chips, CMOS image sensors and many other types of sensors, the semiconductor industry will not be able to overcome the stagnation of the PC market. The momentum for more powerful, smaller and faster portable devices will dominate the PC market, continuing to drive smaller system packaging technologies and less power consumption while creating more functionality and memory capacity. Technology investments will continue for the advanced nodes and leading edge packaging development, but until the confidence of the economy comes back, the capacity investments will be selective based on individual markets. 

One of the biggest challenges for the industry is that 80 percent of the devices used for portable and mobile applications are currently manufactured on 200mm or smaller wafers. How this plays out going forward could change who the dominant players will be and therefore could drive consolidation. As the communications market advances, design wins play a large role in the uncertainty. The secondary equipment market provides ongoing opportunities throughout the entire market, especially during periods of economic difficulty, and is extremely well positioned to capitalize on the continued strength of the 200mm market. Remanufactured equipment continues to demonstrate its viability within the industry, often being sold with guaranteed reliability and shorter lead times that allow for capacity investments that can accommodate changes in short term demand. Additional value-add can be found in the secondary market from a subset of suppliers who are specialized in specific processes. These vendors provide process development and fully qualified processes to customers to accelerate the manufacturing ramp and further enhance the cost of ownership benefits of refurbished equipment.

By Rudy Kellner, VP & GM, Electronics Business Unit, FEI

Consumer demand for more power, speed and functionality in less space seems to be insatiable. Yet semiconductor manufacturers have reached the end of the era when this demand could be satisfied by simply shrinking the dimensions of fundamental planar device technologies. Now they must accommodate complex, three-dimensional (3D) device architectures and a plethora of new materials. At the package level they must develop and produce 3D designs that stack and interconnect multiple die without sacrificing yield or performance. The net result of all this innovation is a sharp increase in R&D capital intensity. In order to maintain profitability manufacturers must increase the productivity and return from their R&D investments. Moreover, time-to-market has become the new battle ground where the first to market enjoy a brief period of premium pricing and higher margins, before the battle begins again.

The decreasing size and increasing complexity of devices has driven demand for high-power transmission electron microscopes (TEMs) required to visualize and analyze structures with critical dimensions of a few tens of nanometers. Equally important, it has also driven demand for the focused ion beam/scanning electron microscope (FIB/SEM) systems needed to create ultrathin samples from precise locations on a die. We have invested heavily to improve the speed and throughput of these systems, reducing sample preparation times to less than 90 minutes with recipe-based automation and hardware innovations that streamline difficult and time-consuming sample manipulations. At the packaging level we have introduced a plasma-based FIB system with milling rates fast enough to permit package-scale edits that can save weeks in the assembly process.

As the industry continues to consolidate, the battle ground will continue to shift. Production excellence and efficiency will remain a requirement, but the spoils will go to the first to market. Accelerating R&D turns and decreasing time to yield will be the keys to success.