Category Archives: 3D Integration

IEDM 2012 slideshow 07


December 4, 2012

Hybrid-channel ETSOI CMOS

CMOS technology uses the two types of MOSFET transistors (N and P) working together in a complementary fashion: when one is on, the other is off. However, the conflicting materials and design requirements for N- and P-type devices make achieving balanced performance and desired threshold voltage challenging. Meanwhile, extremely thin SOI (ETSOI) technology is a viable device architecture for continued CMOS scaling to 22nm and beyond, offering superior short-channel control and low device variability with undoped channels.

At IEDM, a team led by IBM will report on the world’s first high-performance hybrid-channel ETSOI CMOS device. They integrated a PFET having a thin, uniform strained SiGe channel, with an NFET having a Si channel, at 22nm geometries. A novel STI-last (isolation-last) process makes the hybrid architecture possible. The researchers built a ring oscillator circuit to benchmark performance, and the hybrid planar devices enabled the fastest ring oscillator ever reported, with a delay of only 11.2ps/stage at 0.7V, even better than FinFETs. (#18.1: "High-Performance Extremely Thin SOI (ETSOI) Hybrid CMOS with Si Channel NFET and Strained SiGe Channel PFET")

 

A wrap FG cell (left) and a planar FG cell (right).

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IEDM 2012 slideshow 06


December 4, 2012

Goodbye graphene, hello MoS2

Graphene, a one-atom-thick sheet of carbon atoms, is seen as a potential replacement for silicon in future transistors thanks to its exceptional set of properties (high current density, mobility, and saturation velocity). However, transistors made of graphene cannot be turned off because graphene has almost no bandgap. So investigations have begun for a new 2D material, molybdenum sulfide (MoS), which has similar characteristics but offers something graphene doesn’t: a wide energy bandgap, enabling transistors and circuits to be built from it directly. At IEDM, an MIT-led team will describe the use of CVD processing to grow uniform, flexible, single-molecular layers of MoS, comprising a layer of Mo atoms sandwiched between two layers of S atoms. They exploited the material’s 1.8 eV bandgap to build MoS transistors and simple digital and analog circuits (a NAND logic gate and a 1-bit ADC converter). The transistors demonstrated record MoS mobility (>190 cm2/Vs), an ultra-high on/off current ratio of 108, record current density (~20μA/μm) and saturation, and the first GHz RF performance from MoS. The results show MoS may be suitable for mixed-signal applications and for those which require high performance and mechanical flexibility. (#4.6: "Large-Scale 2D Electronics Based on Single-layer MoS2 Grown by Chemical Vapor Deposition")

 

A schematic of the CVD process for growing single-layer MoS.

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Next week is the semiconductor industry’s flagship technical conference show-and-tell: the 58th annual IEEE International Electron Devices Meeting (IEDM, Dec. 10-12), this year held back on the West Coast at the San Francisco Hilton Union Square (and preceded by two days of short courses and tutorial sessions). Highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include unveiling of Intel’s trigate manufacturing technology; a plethora of advances in memory technologies; high-performance logic on flexible plastic substrates; continuing advances in transistor scaling to teens and single-digit nodes; advancements in emerging new materials, wafer-level packaging, MEMS technologies and applications, and more.

Solid State Technology’s Pete Singer will be on site at IEDM 2012, and we’ll be getting input from bloggers and our industry friends. To kick things off, we’ve scanned the entire IEDM 2012 program to present a quick sampling of some of the more intriguing papers. Enjoy the slideshow!

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Major MPU makers are starting to focus on using more exotic dielectric materials with low signal loss (low loss tangent) to meet the higher frequency specs of next-generation MPUs. These materials, such as cyanide ester and polyphenyl ether (PPE), will be able to reliably bond with conductor surfaces using advanced non-etching adhesion promoters (NEAPs) that do not require an interposer layer.

"Unlike some of the other commercially available non-roughening adhesion promoters, the newly developed NEAP does not require an interposer layer such as a thin layer of tin," explains Dr. Rami Haidar, global product manager for surface treatment technology at Atotech Deutschland GmbH, a Berlin, Germany, manufacturer of processes and equipment for the PCB industry. "By avoiding the use of a metal interposer layer, the new NEAP process is more cost competitive and environmentally friendly."

Most of the commercially available NEAP processes are based solely on chemical bonding for providing adhesion between the smooth conductor surface and dielectric materials, says Atotech. The potential weakness of such chemical bonding is its adhesion performance, which depends highly on the type of material to which the adhesive layer is bonded.

"The new NEAP provides mechanical bonding," states Dr. Haidar. "It propagates a nano-scale structure of copper oxide that forms a thin anchoring layer with increased surface area."

The new NEAPs are independent of the adhesion performance of various types of dielectric materials, and the new NEAP process adds surface area to the conductors. Research findings show that copper oxide on the surface hardly contributes to surface roughness, which the root mean square measured at <250 nm, reports Atotech.

The use of NEAP is one of the key technologies for inner and outer layer bonding between conductors and dielectric materials. It enables state-of-the-art IC-substrate manufacturing and meets the technical specifications of major MPU manufacturers.

For future packaging substrates, L/S (lines and spaces) become increasingly finer, even below 8/8 µm. This poses a steep challenge for manufacturers in regard to etching such fine tracks, since the current process of record for adhesion promoters in the packaging industry is still an etching-based system.

EV Group has completed its expanded cleanroom IV facility at its corporate headquarters in Austria, which doubled its cleanroom space for process development and pilot production services.

As part of the company’s long-term growth strategy to address high-volume tool orders and speed time to market, EV Group, a supplier of wafer bonding and lithography equipment, also increased the size of its application labs, added new R&D facilities for internal tool development and testing, and opened a new customer and employee training center.

The customer and employee training center provides several new rooms for instructional training courses, as well as a large number of manual and automated EVG tools for training.

While manufacturing and product development are centralized at EV Group’s corporate headquarters, technology and process development teams in Austria work closely with the company’s subsidiaries in Tempe, AZ; Albany, NY; Yokohama and Fukuoka, Japan; Seoul, South Korea; and Chung-Li, Taiwan, where additional, state-of-the-art application labs and cleanroom facilities are available.

Earlier this year, the addition of an ultra-modern manufacturing facility that doubled the production floor space marked the completion of the first phase of EVG’s long term expansion plans. Already positively contributing to EVG’s growth from the beginning of 2012, the company increased its order intake in FY12 (ended September 30) by 5 percent over fiscal 2011, and increased its revenue by 20 percent within the same period.

Many of the world’s 3D IC elite met last week at the 2nd annual Georgia Tech 2.5D Interposer Conference which focused on the technology and performance of silicon and glass interposers.

Matt Nowak of Qualcomm, long a 3D advocate, reported that Qualcomm has now built "thousands of parts" and does not see anything stopping high-volume manufacturing (HVM) except cost. Nowak indicates that Qualcomm will require a price of ~ $2 for a 200mm2 silicon interposer. The former is just out of the reach of those proposing "coarse" interposer fabrication, and the latter is significantly out of the pricing structure for dual damascene foundry-based fine interposers

Nagesh Vordharalli of Altera quoted an IMEC study which shows that the sweet spot for maximum bandwidth will come from interposers with RDL lines/spaces ~ 3

STATS ChipPAC Ltd. plans to expand its semiconductor assembly and test operation in South Korea. The Company has signed a non-binding memorandum of understanding to invest in a new integrated facility in the Incheon Free Economic Zone, an international business district located in the Incheon metropolitan area that is adjacent to Seoul, South Korea.

The integrated facility will include approximately 95,000 square meters (1 million square feet) of land with options for future expansion. The integrated facility will be used for manufacturing, research and development, and administration. Construction is scheduled to begin in the third quarter of 2013 and the new facility is expected to be operational in the second half of 2015. STATS ChipPAC intends to integrate its existing facilities in South Korea into the new, larger facility to achieve a more efficient, cost effective manufacturing flow and provide flexibility for future expansion.

STATS ChipPAC Korea’s flip chip technology portfolio ranges from large single die fcBGA packages with passive components used for graphics, CPU and ASIC devices to smaller fcFBGA packages including single die, multi-die and stacked configurations that combine wire bond and flip chip technology within a single package.  In terms of 3D technology, STATS ChipPAC Korea provides advanced Package-on-Package (PoP), Package-in-Package (PiP) and System-in-Package (SiP) technologies that integrate one or more integrated circuits or passives into a single solution for mobile, digital consumer and data storage applications.

“We are excited to begin a new phase of expansion in South Korea with the opportunity to increase the level of manufacturing efficiency, capabilities and overall capacity for our customers,” said Sang-Jin Maeng, Managing Director, STATS ChipPAC Korea. “We believe our strategic partnership with Incheon International Airport Corporation (IIAC) will facilitate our future growth in South Korea due to the exceptional business infrastructure in Yeongjongdo and close proximity to Incheon International Airport for accessibility and efficient supply chain logistics.”

November 13, 2012 – Alchimer SA says it is seeking partnerships with various semiconductor equipment and materials companies as it welcomes two top execs. Bruno Morel is the company’s CEO since May of this year, and product development director Fr

by Paul Feeney, Axus Technology

The International Conference on Planarization/CMP Technology (ICPT) was held Oct 15-17 in Grenoble in southern France. This international event is the world’s largest conference covering chemical mechanical planarization (CMP) and related topics, over a 2.5 day period. Over time, the CMP users groups from around the world that come together to form this event are acting increasingly as one body, and the quality of the information has risen.

ICPT oral and poster presentations can be grouped into a handful of major themes:

  • Integration of new device structures, and the CMP processes and slurries needed to support them;
  • Advances in equipment and in endpoint and control methods;
  • Advanced copper interconnects, and the extension of this to 3D and MEMS technologies;
  • Consumables, with a keen focus on mechanistic understanding; and
  • Alternative planarization methods and the application of CMP to new materials.

CMP and new device structures

Leading off the discussion of the application of CMP for new devices was a plenary talk by Daniel-Camille Bensahel from CEA-Leti. He stressed the parallel paths that exist today for 14nm technology and beyond between fully depleted silicon-on-insulator (FD-SOI) and multi-gate or FinFET devices. As technology goes beyond these two architectures, the future will lie in making the transition from silicon channels to some combination of germanium, nanowires, and graphene. All of this bolsters the effect we have already seen putting more focus on the use of planarization in creating devices rather than solely in making interconnects.

Invited talks from IMEC and GlobalFoundries nicely covered the complexity of CMP steps now being employed to fabricate leading-edge devices. In years past, shallow trench isolation (STI) CMP was the only set of CMP steps in the front-end-of-line (FEOL) process flow. Now, many new CMP applications are being added and each calls for multiple process steps. The special dielectric fill for FinFET’s creates the need for steps very similar to those used for STI, but drives the need for stopping on the extremely small nitride features that cover the fins. The ILD 0 or pre-metal dielectric or poly-open-polish (POP) CMP that exposes the tops of the dummy silicon for metal gates also has similarities to these two. The metal gate CMP that follows was discussed as being implemented with either aluminum (Al) or tungsten (W) as the bulk material. There was also coverage of techniques similar to those of replacement gates for formation of replacement channel materials made from germanium (Ge), indium phosphide (InP), or indium gallium arsenide (InGaAs).

Papers that delved into a portion of these new CMP applications pointed out some of the unique challenges. Catherine Euvrard from CEA-Leti pointed out that POP CMP must not only retain tight control over remaining film thickness, but must do so while simultaneous removing nitride and oxide materials deposited at slightly different heights due to the non-planarity remaining after STI. Another difficulty is that the pattern removal rates of nitride and oxide do not follow what might be expected from blanket rates on each of the films when polished separately. Patrick Ong from IMEC went into the development of a 2-step process for replacement Ge channels. The epitaxial overgrowth of Ge is polished back to oxide and then buffed to produce roughness in the range of 2Å. Ulrich Kuenzelmann from TU Dresden showed results from their implementation of Al CMP. These papers were all geared towards advanced logic. Hynix also contributed with talks on new ceria particles for lower defectivity in STI and CMP for buried gates or wordlines for advanced memory. For buried wordline CMP, the bulk metal includes W and must stop on a nitride layer.

CMP equipment, materials, and methods

On the second theme of equipment, a variety of new hardware and control options were highlighted. Len Borucki from Araca pointed out the slurry flow reduction or oxide removal rate gain with a “slurry injector” apparatus. A second talk from Araca described similarities and differences seen in doing CMP of 300mm vs. 450mm wafers. Polishing of 450mm wafers can generate temperatures a few &degC higher, which is likely to have a noticeable effect on temperature sensitive steps such as Cu CMP. Pusan National University and G&P Technology showed that they were able to achieve a radial non-uniformity (NU) of 3% at 2mm edge exclusion with their wafer carrier that contains an “edge profile ring” between the wafer and the retaining ring.

A number of papers described ideas for metrology. Applied Materials and a few customers covered the application of white light illumination for endpoint control across a range of FEOL CMP applications. Improved results were presented for STI thickness, POP thickness with closed loop control of both profile and polishing time, as well as establishment of endpoint control of a process for replacement SiGe channels. Silvio Del Monaco from STMicroelectronics displayed a technique for in-situ measurement of pad groove depth that could be used in characterizing the pad cutting rate of conditioner disks. Florent Dettoni from CEA-Leti described a technique they developed to stitch together interferometric scans to create accurate maps of topography both for whole dies as well as across wafers. Those results were correlated to profilometer scan data, but measurements can be done much quicker. Chandar Palamadai laid out the process that KLA-Tencor has created for quantification of scratching through analysis of blanket wafer haze maps.

CMP and Cu interconnects

The next major theme regarding copper (Cu) included advanced interconnects both for wafers as well as quite a bit on 3D interconnects. Olivier Robin from STMicroelectronics taught us how sheet resistance control mean and variation can be improved by switching to a barrier process with higher selectivity between the dual hardmask and the dense ultralow-k material just below them. Jie Lin from Fujimi described work to develop a slurry for Cu that can get good planarization efficiency despite being used with a pad of moderate hardness. Contributors from Fudan University and from DuPont covered work studying the corrosion and removal rate behavior of the cobalt and molybdenum materials being investigated as part of new barrier material stacks.

ICPT has given increased attention to 3D interconnects and the formation of through-silicon-vias (TSVs) over the last few years. This year included an overview by Viorel Balan from CEA-Leti of some of the issues that need to be addressed in order to do Cu-to-Cu direct bonding. A key to success was identifying and improving topography across several length scales. Both he and Benjamin Steible from ISIT gave evidence that new generations of abrasive-free slurries provide a nice advantage in controlling the dishing of especially larger structures. Jinhai Xu talked about his work at SMIC demonstrating that rings of corrosion at the edges of vias can be seen as a recessed area when there is still about a micron of bulk copper left on the wafer. Rob Rhoades showed two different processes for the TSV nail expose process depending on whether it is an active wafer or an interposer. Catharina Rudolph from Fraunhofer presented a story showing that the combination of high-density TSVs and a higher-temperature anneal actually leads to enough stress that the wafer can explode.

CMP consumables

Over time, consumables for CMP have become more specialized to fit the needs of individual process steps for each application. Consumable topics have always been a popular topic at ICPT and this year was no exception. In the area of pad conditioning, there were two topics that received the most attention. One was applying conditioning techniques to the double-sided polishers used in wafer polishing. Jorn Kanzow from Peter Wolters reported that conditioning provided edge control for the double-sided polishing that is now necessary for achieving flatness for 300mm wafers. The second was the study of pad debris that is generated during pad conditioning and how it leads to an increase in scratch defects. Scratching was shown to be best when doing excitu conditioning or when vacuuming the debris off the pad. A relatively recent style of conditioner uses diamond coating over an engineered surface. 3M presented a summary of their efforts to do that utilizing some of their micro-replication methods.

Keiichi Kimura from Kyushu Institute of Technology presented some very exciting concepts surrounding research done to identify individual removal events during CMP. Through the use of evanescent light, where laser light is bounced off a prism surface, individual slurry particles that come in contact with the prism are illuminated. Their findings put forth the idea that pad asperities and the fluid around them cause adhered particles to be pulled off the polished surface. This happens at velocities much slower than what the pad achieves across the wafer — which rebukes a standard theory that removal is from 3-body contact of a pad asperity pushing a slurry particle into the film being polished. Greg Gaudet from Cabot Microelectronics provided an argument for removal rate with softer pads being driven more by the number of contact points between the pad and wafer rather than the total area of contact. This data seems to back up the concepts presented by Kimura.

For slurries, Intel together with Bradley University and MIT had a few talks outlining the outcome of fundamental studies. Alex Tregub made the point that the characterization of particle size is often overly simplified into a mono-modal distribution. Those tests also often use highly diluted slurry that may not be behaving as it would in its normal state. Mansour Moinpour went over results showing how desorption of additives from particle surfaces can be characterized. Joy Johnson from MIT reviewed a collection of literature surrounding particle agglomeration and added some work showing the role additives can play in agglomerate formation. Along somewhat similar lines, Pall got together with Lewis University to characterize the interaction that slurry particles have with the fibers inside of slurry filters, which may lead someday to the use of novel fibers.

New and improved CMP materials, processes

The remaining major theme is the extension of CMP to new materials and other types of removal processes besides CMP that are also being improved upon. Talks covered new materials such as carbon nanotubes with titanium (Ti) for vias, potassium dihydrogen phosphate (KDP) crystals for optics, GST for phase change memory, SiC for hardmask removal, and Ti and Ti02 for biomedical applications. It turns out that lowering surface roughness of Ti02 improves the biocompatibility of surgically implanted materials.

Though there does not appear to be any technology that is threatening the continued adoption of CMP for many applications, there are also other types of processes that have their place. Hyuk-Min Kim from Hanyang University taught us how lapping results could be improved by switching to a fixed abrasive system. Chuljin Park from KIIT showed a multistep process where diamond mechanical polishing was useful followed by CMP for sapphire substrates. Paul Feeney from Axus Technology demonstrated that improvements in grinding technology can make the CMP of Si after grinding much easier and produce better results. Grinding of Si can be done two-orders-of-magnitude faster than CMP and with within wafer non-uniformity unheard of in CMP. Adding CMP afterwards then produces the best possible surface.

Overall, the technical content of this event was very good. Clearly a lot of energy is being applied around the world to make advances on a wide variety of planarization applications. A high bar has been set for next year’s ICPT in Taiwan!

Paul Feeney ([email protected]) is director of process technology at polishing and thinning company Axus Technology. He started his involvement in CMP at IBM in 1989, holding both process and equipment responsibilities there, including doing pioneering module process and integration work on copper and barrier CMP for the world’s first commercial copper chips. He spent many years at Cabot Microelectronics; as a CMP Fellow there, he led development of a wide range of materials for leading-edge CMP applications. He is also a co-leader for planarization topics for the ITRS.

November 1, 2012 – X-Fab Silicon Foundries says it has become the majority shareholder in German MEMS Foundry Itzehoe GmbH (MFI), the latest in a series of recent moves to raise its profile as a top MEMS foundry.

The MFI business, renamed X-Fab MEMS Foundry Itzehoe, complements X-Fab’s capabilities in its MEMS foundry in Erfurt, adding technologies for microsensors, actuators, micro-optical structures and hermetic wafer-level packaging processes. X-Fab originally signed MFI as a contract MEMS manufacturing partner in Feb. 2011, a deal that expanded its capabilities across a range of 200mm MEMS technologies. Its ownership stake in MFI is now 51%, up from 25.5%.

X-Fab MEMS Foundry Itzehoe will continue its long-term cooperation with the Frauhofer Institute for Silicon Technology‘s (ISIT) MEMS Group. MFI was spun out of ISIT in 2009 and is located within the same wafer fabrication facility in Itzehoe/Germany.

"Our customers will benefit from both an even wider spectrum of available MEMS technologies and from direct access to X-Fab’s manufacturing facilities for CMOS-compatible MEMS processes," stated Thomas Hartung, VP of marketing at X-Fab Group. "X-Fab MEMS Foundry Itzehoe will play an important role in the implementation of our MEMS strategy, and brings us closer to our goal of becoming one of the top three pure-play MEMS foundry providers."

"The rich combination of the versatile MEMS-specific technology portfolio at the Itzehoe-based MEMS foundry and the development expertise of Fraunhofer ISIT greatly expands the capabilities of X-Fab’s technology offering," added Peter Merz, managing director of X-Fab MEMS Foundry Itzehoe. "We are delighted to provide the full bandwidth of MEMS technologies including vacuum and optical wafer-level packaging or TSV backed by X-Fab’s existing and well-proven foundry services. This integration brings X-Fab customers bundled and accelerated product development and manufacturing cycles for micro-machined devices such as inertial sensors, micro-mirrors, and piezoelectric transducers."

Barely a month ago X-Fab pledged to invest $50M over the next three years to support projected growth and a goal of "becoming one of the top three worldwide suppliers of MEMS foundry services." (X-Fab placed 10th in Yole Développement’s 2011 MEMS foundry rankings, surging 33% to roughly $16M in revenues, about $31M shy of No.3 Silex Microsystems.) Among X-Fab‘s other recent MEMS accomplishments: