Category Archives: 3D Integration

RRAM synapses mimic the brain


September 20, 2012

Neuromorphic, or brain-like, electronic systems that mimic cognitive functions are the focus of research because of their potential for complex tasks such as pattern-recognition. Papers presented at the International Electron Devices Meeting in 2011 described studies using programmable phase-change memory (PCM) synapses in neuromorphic systems to carry out a function called spike-timing-dependent plasticity (STDP). STDP is an electronic analog of a brain mechanism for learning and memory, so an electronic system that accurately performs STDP can be said to be “learning.”

At this year’s IEDM, a team led by Korea’s Gwangju Institute of Science and Technology will detail a high-speed pattern-recognition system comprising CMOS “neurons” and an array of resistive-RAM (RRAM)-based “synapses,” which demonstrated STDP. The 1-Kb RRAM array has a simple crosspoint structure and possibly can be scaled to 4F (the theoretical minimum size for a crosspoint array). The work shows the feasibility of using neuromorphic architecture for high-speed pattern recognition.

 

 

Photo of CMOS neuron circuit with 1kB RRAM array as synapse

 

 

Schematic structure of the proposed system. Input spikes come from the left into the RRAM array. (The inset shows the user interface of a computer simulator.)  The ten input images in the neuromorphic system are learned by edge weighting, and during the learning process ‘5’ in node 4 is represented clearly.

 

In this comparison of artificial brain projects, Gwangju Institute of Science and Technology’s neuromorphic device is compared to other reported devices.

Flash memory lifetimes are limited by use, because repeated program/erase (P/E) cycles degrade the tunnel oxide which insulates flash memory cells. In principle, heating the oxide will repair the damage but thermal annealing has been impractical because flash memories can’t tolerate the high temperatures and long baking times required.

At the upcoming International Electron Devices Meeting, Macronix researchers will describe how they built flash memories that could heal themselves by means of tiny onboard heaters that provide thermal annealing just at the spots where it is needed. They modified the wordline from a single-ended to a double-ended structure, which enabled current to be passed through the gate to generate Joule heating. High temperatures (>800° C) thus were generated only in immediate proximity to the gate. The devices demonstrated record-setting endurance of >100 million P/E cycles with excellent data retention. Interestingly, the researchers also saw that the heating enabled faster erasing, which is thought to be temperature-independent.

 

The schematic image above shows the structure of the diode-strapped wordline. A PN diode can be formed directly on top of the wordline, and local interconnect can be used to connect to the metal heat plates.

The 58th annual International Electron Devices Meeting (IEDM) will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to vanishingly small sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

“The IEDM can be a crystal ball looking into the future of technology evolution. Leading-edge technologies and novel devices reported at the conference will shine light on the industrial mainstream in the next three-to-five years,” said Tzu-Ning Fang, IEDM 2012 Publicity Chair and Senior Member, Technical Staff, at Spansion, Inc. “This year’s program shows a tremendous amount of work being done in emerging technologies, including novel materials such as molybdenum sulfide, new structures, 3D NAND memories, wider use of III-V materials, MRAM, nanowires and more.”

Besides the IEDM technical program, attendees will enjoy evening panel sessions, Short Courses, award presentations and other events, as follows:

90-Minute Tutorials — Saturday, Dec. 8

Back by popular demand for the second year, the IEDM will hold 90-minute tutorial sessions on emerging topics presented by experts in the fields. They are meant to bridge the gap between established textbook-level knowledge and the leading-edge research as presented during the conference. The tutorial sessions will be presented in parallel in two time slots. Advance registration is required.

2:45-4 p.m.

High Mobility Channel CMOS Transistors – Beyond Silicon by Shinichi Takagi, University of Tokyo

Fundamentals of GaN Based High Frequency Power Electronics by Tomas Palacios, M.I.T.

Spintronics for Embedded Non-Volatile Electronics by Tetsuo Endoh/Tohoku University and Arijit Roychowdhury/Intel

4:30-6:00

2D semiconductors – Fundamental Science and Device Physics by Ali Javey, University of California, Berkeley

Scaling Challenges of Analog Electronics at 32nm and Beyond by Mustafa Badaroglu/IMEC and Bram Nauta/University of Twente

Beyond Charge-Based Computing by Kaushik Roy, Purdue University

Short Courses — Sunday, Dec. 9

The IEDM offers two day-long short courses on Sunday, prior to the technical sessions. They provide the opportunity to learn about emerging areas and important developments, and to benefit from direct contact with expert lecturers. Advance registration is required. This year’s courses are:

Emerging Technologies for Post-14nm CMOS

Circuit and Technology Interaction

Plenary Presentations — Monday, Dec. 10

IEDM 2012 will open on Monday, Dec. 10 at 9 a.m. with three plenary talks:

Flexible Bio-Integrated Electronics by John A. Rogers, University of Illinois

State of the Art and Future Prospects in Display Technologies by Joo-Tae Moon, Senior VP, Director R&D Center, Samsung Display Company

Ultimate Transistor and Memory Technologies: Core of a Sustainable Society by Luc Van den hove, CEO and President IMEC

Emerging Technologies Session — Tuesday morning, Dec. 11

This year’s Emerging Technologies session is on the topic Spintronics: Magnetic Materials and Device Applications, organized by Stefan De Gendt of IMEC. Invited speakers from academia and industry will discuss the challenges, prospects and recent advances in spin-based technology, devices and systems. Following the discovery of the giant magnetoresistance (GMR) effect more than a decade ago, this field has witnessed a veritable revolution encompassing materials and physical phenomena. Electronic devices based on spin transport are expected to play a major role in future information and communication technologies, as spintronic devices will use the spin degree of freedom to store, transport and process information. Papers in this session are:

Spin Transport in Graphene: Fundamental Concepts and Practical Implications by Abdelmadjid Anane et al, Unité Mixte de Physique CNRS/Thales

Thermal Spin Transport and Applications by S. Y. Huang et al, Johns Hopkins/National Tsing Hua University/Academia Sinica

Progress of STT-MRAM Technology and the Effect on Normally-Off Computing Systems, by H. Yoda et al, Toshiba

 Spin Transport in Metal and Oxide Devices at the Nanoscale, by Subir Parui et al, Zernike Institute for Advanced Materials

Error Immunity Techniques for Nanomagnetic Logic, Brian Lambson et al, University of California, Berkeley/Lawrence Berkeley National Lab

Boolean and Non-Boolean Computation With Spin Devices, Mrigank Sharad et al, Purdue University

Luncheon Presentation — Tuesday, Dec. 11

The IEDM Luncheon presentation will be given by Ajit Manocha, CEO of GLOBALFOUNDRIES, Inc., on the topic Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!

Evening Panel Sessions — Tuesday evening, Dec. 11

The IEDM will offer attendees two evening panel discussions. Audience participation is encouraged, with the goal of fostering an open and vigorous exchange of ideas. The panel topics are:

"Will Future Non-Volatile-Memory Contenders Disrupt NAND?" moderated by Al Fazio, Intel

 “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” moderated by Suresh Venkatesan, GLOBALFOUNDRIES.

Entrepreneurs Lunch — Wednesday noon, Dec. 12

New for 2012 is an entrepreneurs lunch. The speaker will be Weili Dai, cofounder of Marvell Technology Group and Vice President and General Manager of Marvell’s Communications and Consumer Business. One of the most successful women entrepreneurs in the world, she was named No. 89 on the Forbes list of “The World’s 100 Most Powerful Women” earlier this year.

Further information

For registration and other information, interested persons should visit the IEDM 2012 home page at www.ieee-iedm.org.

Singapore’s A*STAR’s Institute of Microelectronics (IME), and Hitachi Chemical Co., will be collaborating on a joint research program to develop high performance material technologies for thin wafer processing for 3D IC packaging.

"Our expertise, experience and infrastructure in 2.5D/3D IC process-integration, thin-wafer-handling, and assembly flow provide a compelling value proposition for advanced materials manufacturers to test their products and overcome key technical barriers in the commercialization of 2.5D/3D IC technology,” said Prof. Dim-Lee Kwong, Executive Director of IME. “IME is in a strong position to enable materials development that is increasingly critical to ramping advanced packaging technologies to high volume manufacturing.”

The Interconnect and Packaging Program (IPP) at IME focuses on strategic research areas in the research and development of 3DIC and TSV technologies, including: 3D stacking with chip-to-wafer (C2W) and wafer-to-wafer (W2W) bonding technologies, embedded wafer level packaging, integrated passive device (IPD) with Si or polymer substrate, MEMS packaging, electrical, thermal, mechanical design, materials, process and reliability.

Due to the temperature-hermeticity-sensitivity of the MEMS/MOEMS devices and the thermal-stress effects of the 3D stacked dies, there is a critical need for lower wafer bonding temperatures of below 200°C. At IME, the current R&D focus on low-temperature processes includes: Wafer-to-wafer bonding of hermetic sealed MEMS/MOEMS devices, and chip-to-wafer bonding of 3D stacking with TSV technology and microbump interconnects.

3D research at IME is also focused on TSV formation, including:

•           Dielectric isolation materials and processes

•           High-speed via architectures and filling methods

•           Electrical design and characterization of Si-interposer

•           Global/local design and modeling of interconnects of Cu/ultra low-k large chips

•           Microbump interconnection design, materials, assembly processes and reliability

“IME has strong background technologies of microelectronics, especially in IC packaging technologies, and Hitachi Chemical has many kinds of material for the electronics. I believe this joint research between IME and Hitachi Chemical will contribute greatly to the progress in advanced 3D IC packaging technologies.” said Shun-ichiro Uchimura, Vice President and CTO of Hitachi Chemical.”

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September 13, 2012 – Step aside, scatterometry and AFMs — there’s a new hybrid technique that’s both more precise and less expensive to measure features on a chip.

The National Institute of Standards and Technology (NIST) says it’s combined scanning techniques and statistical data "using a Bayesian approach." They created a library of simulated data based on typical chip feature dimensions, to be compared with actual measurements made with AFM, scatterometry and other means. Comparing that analysis with actual measurements to extract valid measurement values can be costly — until one applies a little Bayesian statistical analysis.

"In essence, if you’ve got a really small uncertainty in your AFM measurement but a big one in your optical measurements, the final uncertainty will end up even smaller than either of them," explains NIST scientist Richard Silver. Adding a few other measured values to the library model reduced uncertainty in some of the measurements — by up to a factor of three in some cases, NIST claims.

This approach, the scientists say, will be a key part of measuring complex 3D transistor structures that are quickly approaching the 16nm node and beyond. In fact, Silver reveals that "IBM and GlobalFoundries have already begun developing the technique since we first described it at a 2009 conference, and they are improving their measurements using this hybrid approach."

The research is described in the Sept. 1 issue of the journal Applied Optics.

A silicon pillar, measuring <100nm along any of its sides, is the type
of semiconductor feature in the crosshairs of a new NIST hybrid metrology
technique to reduce measurement uncertainties. (Credit: NIST)

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Samsung Electronics Co., Ltd., held a groundbreaking ceremony for a major new memory fabrication line in Xi’an, China. Once completed, the new facility will make use of advanced 10-19nm technology to produce NAND flash memory chips, according to the company.  

Samsung Electronics Vice Chairman and CEO Dr. Oh-hyun Kwon hosted the event, which welcomed 600 attendees including government dignitaries such as Zhao Leji, secretary of provincial party committee and director of provincial People’s Congress Standing Committee, and Kyu Hyung Lee, Ambassador of the Republic of Korea to China. Other honored attendees included Sang-Jick Yoon, vice minister for Industry and Technology at the Ministry of Knowledge Economy, as well as hundreds of Samsung suppliers and customers.

Vice Premier of State Council of the People’s Republic of China Li Keqiang congratulated the event through a personal letter, noting that the project will move the partnership between the two countries forward within the IT field.

Dr. Kwon said in his remarks during the ceremony, "It is a great honor to announce our groundbreaking at Xi’an, a city of tremendous historic and academic significance, as we celebrate the 20th anniversary of diplomatic relations between Korea and China. At this time, our memory semiconductor business also marks its 20th consecutive year as the leader of the memory industry. The new Samsung China Semiconductor fab will lay a solid foundation for continued supply of leading memory components, enabling Samsung to further spearhead the advancement of the IT industry and enhanced user experiences."

With the groundbreaking, the Samsung China Semiconductor complex has a target timeline for achieving full-fledged operation in 2014. Initially, Samsung is investing US$2.3 billion in the Xi’an fab. Samsung China Semiconductor will mark the single largest investment by Samsung in China with a phased total investment of US$7 billion.

The capital of multiple dynasties spanning over a thousand years, Xi’an is at the center of development of advanced electronics technology as a primary location in China’s Western Region Development. Xi’an’s industrial landscape supports all key considerations in the production of advanced IT infrastructure such as basic resources including water and power, and a solid employee base for IT research, development and manufacturing.

Xi’an is home to 37 universities and 3,000 R&D centers focused on advanced IT technology. Samsung has also kicked off a program for close academic collaboration with several reknown local universities, which will include scholarships to nurture skilled talent locally.

The groundbreaking in Xi’an comes just one year after Samsung commenced operations at its Line 16 in Hwaseong, Korea.

September 10, 2012 – EV Group (EVG), St. Florian, Austria, has updated its modular EVG 150 automated resist processing system to address specific needs for backend lithography, conformal coating, and planarization. The new system was announced at last week’s SEMICON Taiwan.

The newest version of the EVG150 high-volume coater/developer performs spin coating, developing, spray coating and lift off on 50-200mm wafers, enabling up to four wet process modules combined with two stacks of hot plates, chill plates, and vapor prime modules. Two key additions include EVG’s OmniSpray technology (with proprietary ultrasonic nozzle), which allows the conformal coating of high topography surfaces (e.g. ultra-thin, fragile, or perforated wafers) and can result in up to 80% reduced material consumption vs. traditional spin coating, according to the company. The other key addition is the NanoSpray coating technique to coat surfaces with vertical sidewall angles — for example, processing through-silicon vias (TSV) with polymer liners and photoresist.

EVG reps summarized the additions for SST:

  • A modular design allowing roll-in/-out of process modules, for enhanced uptime and serviceability

  • A new spray coating module (the company’s OmniSpray technology) with x,y (raster) spray coating

  • A new module for the company’s proprietary "NanoSpray" process for coating blind vias

  • A new structural frame with most chemicals stored within the main frame, to shorten point-of-use and optimize process control

  • CIM Framework software, to help meet rigorous requirements for uptime, process control, and fab automation

"Close collaboration with our customers made it clear that the next logical step for our coater/developer technology was to create a universal approach for high-volume processing of devices with more complicated structures and topographies," stated Markus Wimplinger, EV Group’s corporate technology development and IP director.

 

Left: Vias with 1:5 aspect ratio, conformally coated with NanoSpray. Right: Top edge of
spraycoated cavity (cavity 150

September 4, 2012 – Singapore’s Institute of Microelectronics (IME), a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR), and MOSIS have signed a memorandum of understanding (MOU) to offer a multiple-project wafer (MPW) service targeting silicon integrated photonics.

The goal of the collaboration is to reduce the cost obstacles and promote broader adoption of silicon photonics devices for the industry. The partnership specifically involves sharing costs for the fabrication, the reticles or masks, the setup and use of the design environment. Photonics designers and researchers will also have access to IME’s device library that includes integrated active and passive devices.

The two partners also are collaborating on multiproject runs for 3D through-silicon vias (TSV) and silicon interposers (TSI), and MEMS devices. These will be available at the end of 2012 and in 1H13, respectively.

"By leveraging the expertise and resources of one of the world’s leading semiconductor research institutes, our partnership with IME will develop efficient and practical approaches in the area of silicon photonics to meet the increasing requirements of industry," stated Wes Hansford, director of MOSIS.

"We look forward to offering our MPW capabilities to the silicon photonics community to enable innovations and product development to accelerate the growth of the silicon photonics industry," added Prof. Dim-Lee Kwong, executive director of IME.

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