July 27, 2012 — At Nanya Technology
Category Archives: 3D Integration
July 25, 2012 — SEMI Europe will host a new event, the European 3D TSV Summit, January 22-23, 2013 in Grenoble, France. This inaugural meeting will revolve around the theme: "On the Road towards TSV Manufacturing," denoting how device designers and manufacturers are crossing from 2D packaging to 3D for more functionality in a smaller form factor.
Europe
July 25, 2012 — STATS ChipPAC Ltd. (SGX-ST:STATSChP), a leading semiconductor test and advanced packaging service provider, appointed Gary Tanner as a member to its Board of Directors. Tanner brings experience from Zarlink Semiconductor, Intel (INTC), Texas Instruments (TI, TXN), and other semiconductor companies.
Tanner served as director, CEO and president of Zarlink Semiconductor Inc. (2007-2011) until it was acquired by Microsemi Corporation in October 2011. Before joining Zarlink, he was VP of operations of Legerity Inc. Tanner also held various management positions during 9 years at Intel, and held fab management roles at National Semiconductor, Texas Instruments, and NCR Corporation.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com.
July 24, 2012 — Global Semiconductor Alliance (GSA) recently named Jalinous (Jay) Esfandyari, MEMS product marketing manager, STMicroelectronics, as its MEMS Working Group chairman and Ken Potts, group director of marketing, Strategic Planning, Cadence Design Systems, as the 3D IC Working Group chairman.
Micro electro mechanical systems (MEMS)
In June, the MEMS working group heard presentations on MEMS market directions for the next decade and discussed collaboration with other industry efforts, as well as a strong focus on setting impactful deliverables. The Working Group considered several possible areas of development during this inaugural meeting, including potential deliverables such as MEMS Product Design Kits, a MEMS Glossary of Terms, or providing a MEMS EDA Tools Workshop.
Esfandyari has more than 20 years of industry experience in semiconductor technology, integrated circuits fabrication processes, MEMS development and fabrication, and strategic MEMS market and business development. As the MEMS Product Marketing Manager at STMicroelectronics, he has developed new markets for MEMS products and achieved multi-million dollar business opportunities.
In his previous roles, Jay worked closely with customers to develop custom MEMS products, developed models to describe the physics of defect generation in silicon wafer during device fabrication processes, and created solutions to perform analysis and computer simulation to improve the quality of silicon wafers. Esfandyari holds a master
July 19, 2012 — 3D through silicon via (TSV) chips will represent 9% of the total semiconductors value in 2017, according to Yole D
July 17, 2012 — Ziptronix Inc., which develops direct bonding technology for advanced semiconductor applications, has licensed its technology for a high-volume cellular handset application.
The high-volume consumer application will benefit from cost savings and efficiency of Ziptronix DBI wafer stacking, the company says. The wafer bonding technology can offer smaller pitch, increased functionality, increased density and scalability, along with lower-cost manufacturing, for future generations of 3D integrated devices.
The technology saw its initial adoption in image sensor manufacturing, and is now being applied in 3D memory stacking and other applications, said Daniel Donabedian, CEO of Ziptronix. Additional licensing discussions are underway with companies targeting 3D integration, he added. Ziptronix licenses its technology throughout the semiconductor supply chain, including OEMs, IDMs and some fabrication and assembly facilities
Ziptronix develops low-temperature direct bond technology for various semiconductor applications, including backside-illuminated (BSI) sensors, RF front-ends, pico projectors, memories and 3D ICs. Ziptronix
July 13, 2012 — At SEMICON West 2012, this week in San Francisco, CA, the working groups of the International Technology Roadmap for Semiconductors (ITRS) held 3 sessions (TechXPOTs) outlining 2012 updates to the roadmap. Check out the updates to the front-end, scaling roadmap working groups here.
The ITRS undergoes major revisions on odd-numbered years. 2012 being an even-numbered year, very little change occurred to the Overall Roadmap Technology Characteristics (ORTC). However, within the working groups, some updates were worth noting.
Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show
First, the changes to the ORTC, presented at the TechXPOT by Bob Doering. Of interest were changes focused directly or indirectly on 450mm. ITRS has moved the forecast production start date to 2015-2016. The definition of
July 13, 2012 — SEMICON West, this week in San Francisco, CA, hosted 3 TechXPOT sessions on the International Technology Roadmap for Semiconductors (ITRS, http://www.itrs.net/) 2012 update. At the back-end technologies session, roadmapping for More than Moore was addressed as both a philosophical and technical matter.
Also read: 2011 ITRS: DRAM, 3D Flash, MEMS, nano-scaling steal the show
Introducing the back-end-focused working group presentations, Bob Doering, representing the Overall Roadmap Technology Characteristics (ORTC), said that the Roadmap is not just about scaling anymore. Patrick Cogez, presenting More than Moore, picked up this thread, saying that the long-time focus on semiconductor scaling now has a partner, diversification, in More than Moore process technologies. More than Moore — encompassing advanced wafer-level and 3D packaging, micro electro mechanical systems (MEMS), and related microelectronics technologies — are harder to roadmap than CMOS technologies. Scaling semiconductor nodes has always offered the combined benefits of faster, cheaper, smaller, lower-power chips (Moore
July 12, 2012 — There’s no doubt that fabless semiconductor companies are taking a keen interest in the semiconductor manufacturing supply chain and processes. To that end, SEMICON West’s Day 2 keynote speaker represented a fabless company: Ivo Bolsens, PhD, SVP and CTO of Xilinx presented on how programmable chips and innovative packaging can advance semiconductors.
Check out insights on the Day 1 keynote from Intel here.
There’s nothing new about the goals of semiconductor designers and manufacturers, Bolsens said, sharing some decade-old slides to make his point. Power density, Moore’s Law, and lowering costs have always been important, and innovation in technology and business models has always generated solutions.
The fabless semiconductor company’s goal is to add value to the system-level design. To do this, Xilinx has taken the approach of device flexibility, paired with 3D interconnection for higher performance/lower power/higher reliability. Bolsens notes that the company is collaborating much earlier with the supply chain and in a much broader fashion than ever before to achieve these goals.
Programmable chips offer flexibility, even while they may appear to have a higher cost than dedicated products. The ability to customize a chip for your functions, and use the same chip across various system-level configurations, leads to costs savings, Bolsens said, referring to time savings as a direct benefit. Logic can also be tuned to accelerate some functions, boosting performance. To save energy, FPGAs offer “fine-grain” programmability.
On the 3D and 2.5D packaging front, Bolsens shared the benefits of using multiple smaller die integrated in one package. Interconnect innovations increase the bandwidth/Watt consumed, and chip yields go up compared to fabricating one large die. When small FPGA die replace a large monolithic die, designers can use “best of breed” die for different functions. Isolation of different blocks also improves.
3D integration and other technology answers for the semiconductor industry’s challenges are in place, summarized Bolsens. Now, the supply chain must build up around them, with supporting information like process development kits (PDKs), design for manufacturing (DFM) rules, and other standardization efforts.
Bolsens recommends creating a continuous supply chain feedback loop while in the early ramp-up of a product, harkening back to his earlier points about collaborating early and often with the ecosystem that will enable your chip to reach market.
Check out Ivo Bolsens’ biography here, courtesy of SEMI.
Check out Solid State Technology’s coverage of SEMICON West 2012!
July 12, 2012 — CEA-Leti co-located its research updates presentation with SEMICON West 2012 in San Francisco, CA, this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology’s digital media editor Meredith Courtemanche to talk about their fields of interest.
Also read: Semicon West Day 1: FDSOI and TSV R&D with CEA-Leti by blogger Michael A. Fury, PhD.
Check out the videos for details on the research:
Hughes Metras, VP of strategic partnerships in North America, presented on cost and energy consumption in large-scale computing, and what technical innovations will meet the industry’s needs. Energy efficiency must improve at the circuit, interconnect, and system level, he said.
Silicon photonics waveguides are one way to significantly increase bandwidth in semiconductors. CEA-Leti is migrating to a 300mm Si photonics line in its research work. Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, presented on the question of low-cost/low-power computing architectures, and the answers available in photonics.
Maud Vinet, LETI FDSOI Manager, IBM Alliance, shared the benefits of fully depleted silicon on insulator (FDSOI) transistor architecture. The performance? Excellent parasitic capacitance resistance because of the smaller gate length than bulk CMOS. The energy efficiency? Back bias allows tuning of the devices’ threshold voltage to reduce wasted power. (We cover energy efficiency of new transistors/interconnects in more detail here.) The manufacturing parameters? Easier than a FinFET, Vinet says, as the majority of processes are the same as today’s semiconductor fab methods. The one challenge is potential silicon loss, because planar FDSOI uses thin Si films on the order of a few nanometers.
Mark Scannell and Denis Dutoit both lead 3D interconnect operations at CEA-Leti, with Scannell focused on manufacturing and Dutoit on design. Unfortunately, we did not have time to interview Scannell, though his research is summarized here. The interview below is with Dutoit. Leti has both a 200mm and 300mm line for wafer-level 3D packaging research. 2.5D passive interposers and 3D active stacks are “cousins” in device packaging, and you will see both of them used for different purposes for quite some time. While both 3D and 2.5D technologies can appear in the same package, the supply/value chains for each technology are quite different.
What’s in store in this area? “Smart” interposers are being developed with integrated passives on the interposer. 3D partitioning is enabling scaling as you like it — preventing chips from being held back to a larger device node by one of the blocks involved. Also on the horizon is via-last through silicon vias (TSV), an old technology that could now come back to offer continued TSV diameter scaling past what via-middle architectures can provide. The enabling technology here is permanent bonding. Also on CEA-Leti’s agenda is direct bonding, which spreads the stress gradient over the entire copper daisy chain, unlike today’s TSVs, and has a lower contact resistance. Finally, the researchers are considering sequential or monolithic 3D to make 50nm stacked structures on a wafer.
Before the meeting ended, Laurent Malier, CEO of Leti, spoke with Solid State Technology about the research organization’s current goals.
Check out Solid State Technology’s coverage of SEMICON West 2012!