Category Archives: 3D Integration

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs).  “The biggest trend for the last couple of years has been 3D and TSV and it continues to be that way,” said David McCann of GLOBALFOUNDRIES and ECTC conference chair.  This year, the conference features a set of sessions specifically on 3D TSVs, with minimal overlap.  There’s also an additional session specifically on interposers, otherwise known as 2.5D. “The industry really wants to see 2.5D happen as an easier way to do 3D before all the 3D tools are in place,” McCann said. “The struggle is over how much is an interposer going to cost.”

Presently, that struggle appears to be between glass and silicon, where glass is a less expensive alternative. “Glass would be a cheaper approach to silicon interposers, but is limited to line space and via diameter,” McCann said. “Glass is not able to get as dense as silicon.” He said there may be a bifurcated market on interposers, where the high end is on silicon, and the low end is on glass. High end applications are devices such as microprocessors, which need high density, 1 micron lines and spaces. Low end devices are capabilities such as RF.  

In terms of when TSVs will move into volume production for mainstream applications, McCann said that RF devices that already have TSVs because they have backside contact. Next, memory devices are in line to for TSV production. “I think there will be more and more memory stacks,” he said. Fabricating a memory stack internally for a memory company is easy (at least compared to alternative approaches) in that it doesn’t require an outside standard to be able to do the connection between the devices. “Next will be wide I/O or whatever wide I/O morphs into, maybe wide I/O2, where you get an apps processor with a wide I/O DRAM on top of it,” McCann said. “I think we’ll see those starting in 2013, first products in the industry and 2014 for adoption into 20nm. And then, following that, it’s very dependent upon standards. Wide I/O standard is critical for getting multiple memory suppliers to supply memory or a consuming company to use multiple suppliers,” he said.  “Standards are going to enable products and those first 3D products are going to use devices that already exist and put TSVs into them.”

The real potential of 3D integration will come around 2017 or 2018, McCann believe, when heterogeneous stacks with different devices with different functions, such as memory, digital, analog , RF and power, are integrated in a stack. “There will be design tools that optimize the design of those devices for placement of blocks, TSVs and bumps  for optimal performance. In the first products, we won’t have so much optimization, but more enablement, and then where we all really want to get to is that optimization of performance, “ McCann said. “What that will look like is say a bit of memory just above a processing cell, right where you want it. Or the analog the right where you want it to be placed with this very short vertical interconnect to the circuitry that it needs to communicate with. We’ll get to optimal block placement when the tools start getting available to help us co-design devices from different manufacturers for optimal performance.”  

McCann acknowledged that testing these complex 3D stacks will be a major challenge, saying is revolves very much around IP. “If you think about DRAM and how it’s tested, it’s all internal to the DRAM company and it’s very tightly protected IP. Nobody wants to let that outside, understandably. Then you start thinking about 2.5D and 3D where you’ve got integrated memory – how do you do that? The assembly of those is not going to be at the memory manufacturer,” he said.

McCann believe stacked memory will evolve in two stages. The first stage will be it will be shipped as a completed component so that the memory company can continue to adhere to the business model of shipping a completed, tested, repaired device — a know good die.” That small stack will be placed on an apps processor for 3D, or on an interposer for 2.5D,” he said. The second part of it is what IP is needed for both the microprocessor and the memory to enable test. “We’ll start seeing test IP blocks from the foundries and the memory companies to enable test by using the processor to test the memory . I think we’re still exploring what that looks like. I can’t tell you what that’s going to end up looking like, but it’s clear that we’ve got to enable that together to enable the products,” McCann said.  

May 31, 2012 – PRNewswire — Xilinx Inc. (NASDAQ:XLNX) began shipping a 3D heterogeneous all-programmable FPGA, the Virtex-7 H580T FPGA, using its stacked silicon interconnect (SSI) technology to reach up to 16 28Gbps and 72 13.1Gbps transceiver bandwidth.

May 30, 2012 – BUSINESS WIRE — Semiconductor direct bonding technology provider Ziptronix Inc. is helping a 3D memory device maker replace standard die stacking with its DBI wafer-stacking technology. Memory stacking can enable higher memory density in a given footprint, and the wafer-level stacking technology could significantly reduce packaging cost for the 3D architecture.

Traditional die stacking requires die thinning and thinned-die handling and development of reliable interconnect processes. Ziptronix DBI combines proprietary wafer-level low-temperature oxide bonding and interconnection. It creates extremely strong low-stress bonds, allowing wafers to be processed and thinned after bonding, eliminating the need to handle thinned wafers and/or dies. Interconnect density and alignment accuracy are high, and the device profile is kept low, Ziptronix notes. The process is compatible with damascene interconnect processing, and various test and repair strategies.

DBI is used for backside imaging (BSI) sensors, where Ziptronix reports that it delivers cost savings of up to 80% over copper thermo-compression bonding. The new collaboration is founded on Ziptronix DBI

May 29, 2012 — Growth in handheld, Internet-connected electronic devices — smartphones and tablets — and resurgent automotive demand are increasing IC demand. In turn, increased demand for product functionality is driving up IC packaging revenue faster — a 9.8% compound annual growth rate (CAGR) — than IC unit growth — 7.3% CAGR 2010-2016, says New Venture Research (NVR).

Figure. IC device and packaging revenue forecast ($M), 2010-2016. SOURCE: New Venture Research.

Handheld electronics will boost the growth of special purpose logic (SPL) communications chips by 16.7% CAGR revenue through 2016, versus 3.5% CAGR in units. Packages for mobile components are dominated by field-programmable gate array (FPGA) and quad flat-pack no-lead (QFN) designs. These 2 package structures are at opposite ends of the pricing structure. The third most popular packaging type, quad flat pack (QFP), is decreasing in usage over time. These devices are expected to have a 14.8% CAGR in revenue through 2016.

Wireless infrastructure products are also in high demand, which is helping boost consumption for standard cell and programmable logic device (PLD) chips. These devices will grow at a CAGR of 16.1% in terms of revenue through 2016, while the device units are projected at 15%. High I/O BGAs are the package of choice over the forecast period — package revenue growth is projected to be slightly higher, at 16.3% CAGR through 2016.

Logic chips are in demand for a host of products, pushing 32-bit MCUs to an 11.1% CAGR unit demand, although only 4.7% device revenue CAGR, through 2016. QFPs and ball grid arrays (BGAs) are the highest-demand package designs for these chips, although the QFP is waning in favor of the BGA. Thus, the package revenue is growing at a CAGR of 12.8% through 2016 for 32-bit MCUs.

This information is included in the newly released report

The 10th Annual MEMS Technology Symposium sponsored by MEPTEC (MicroElectronics Packaging and Test Engineering Council) was held May 23 at the San Jose Holiday Inn. This year’s theme was “Sensors: A Foundation for Accelerated MEMS Market Growth to $1 Trillion.” Registered attendance was ~230.

The conference opened with a keynote address by Prof. Kristofer Pister, UC Berkeley speaking on sensory swarms. Inexpensive, wireless sensor networks have moved out of the lab and are being implemented in myriad applications. A refinery in Richmond, CA has methane gas sensors at every valve to monitor emissions. Parking spaces in San Francisco and Hollywood are tagged with car sensors to provide dynamic signage directing drivers to open spaces; this system also communicates with a smart phone app (“Parker”) to take you to specific open spaces. Rail cars have temperature and vibration sensors on every truck for predictive and preventive maintenance. Wireless sensors in the field are projected to top 1.1 billion units by 2015, up from 168 million units in 2010.

Janusz Bryzek, VP Fairchild Semiconductor, revisited his theme of accelerating the MEMS market to $1 Trillion and 1 trillion units. A $1 wireless sensor unit will require a 20¢ internet access module. The HP notion of a central nervous system for the earth will call for an average of ~1,000 sensors for every person. Smart phones have spurred the initial growth burst for MEMS, but the internet of things represents the “largest growth opportunity in the history of business.” Factors slowing MEMS market development include relatively slow MEMS process R&D cycles, and a lack of industry standards for manufacturing, packaging and testing. The fusion of computing, communication and sensing has been characterized as the third industrial revolution by Vijay Ullal of Maxim. While manufacturing jobs continue to be outsourced, the profitability and job creation potential at the innovation, design and marketing end remains a lucrative economic driver for the US.

Robert Haak of MANCEF described the implementation of the $1T MEMS roadmap. The key technologies needed for success include RF, chemical measurements, energy sourcing, inertial measurements, pressure measurements, acoustic sensors and displays. The industry roadmap infrastructure needs to evolve to a 3rd generation that focuses on products that are conceived at the interface of more than one technology. Specific roadmaps proposed are sensors, data transfer and data processing equipment. These are proposed to have a 15 year outlook with a 5 year review cycle.

Richard Friedrich of HP Labs spoke of the aforementioned central nervous system for the earth, CeNSE: awareness through a trillion MEMS sensors. The subtitle of his talk proclaimed this as the decade of sensing and sense-making. True more for technology than for politics. The infrastructure behind this enterprise will require about 1,000x more bandwidth than today’s internet has available. His vision projects ~150 sensors for every person on the planet, fewer than the second speaker but with a focus specifically on CeNSE applications. A MEMS nanofinger substrate for surface enhanced Raman scattering  (SERS) provides a signal enhancement factor of 1011, enabling a detection sensitivity of 0.02 parts per trillion. The use of people as sensors is manifest in real time analysis of Tweets for regional tuning of marketing campaigns. The HP Social Computing Lab claims 97% accuracy in predicting movie revenues based on the response to pre-release advertising. Work is underway to simulate the human brain visual cortex using a system with 64,512 cores that has demonstrated the ability to learn without being taught. The root objective of a CeNSE network is to convert the flood of data into insight that leads to action. Skynet?

Greg Galvin, CEO of Kionix, presented another perspective of sensing the future on the road to a $1T market. They focus solely on inertial sensors, which had a 2004-2011 unit CAGR of ~100%. Unit prices of accelerometers, compasses and pressure sensors are already well below $1, with gyroscopes to follow by 2015. MEMS components have been averaging 2% of the end cost of products that use them. His conclusion was that a $1T market for MEMS over the next 10 years is unlikely, even though a 1T unit market is probably, and a $1T market for MEMS-enabled devices is a given.

Jérémie Bouchaud of IHS iSuppli couched his perspective as a “MEMS revolution: from billions to trillions?” The 5 year MEMS CAGR is presently running at 9.7% for revenue overall and 20.7% for shipments. Smart phones by themselves have a 17.8% revenue CAGR, and are a significant market driver. MEMS microphones are another beneficiary of smart phones, which now include multiple microphones for both speaking and for background noise suppression. Despite the myriad growth opportunities, he believes the prospect of a $1T MEMS market will require price points ≤5¢ per unit, and an expansion of the market definition to include sensors for temperature, light, humidity, UV and others.

The afternoon keynote was delivered by Steve Nasiri, founder of InvenSense, a big player in the motion interface MEMS market. Just 3 applications, mobile handsets, media tablets and gaming represent a $2.4B market by 2015. The gyro market was slow to get started until Apple put one in the iPhone in 2010. Within a year, over 70 other models were on the market with gyros, even though some didn’t seem to know what to do with them. The wearable sensor market for remote patient monitoring, home monitoring, sports & fitness will push to $150M by 2015. Does your mother live too far away to tell you not to slouch? A shirt with an embedded posture sensor can handle that for her. InvenSense has just announced an open platform infrastructure to facilitate rapid MEMS applications development.

Jean-Christophe Eloy of Yole Développement provided a status of the MEMS industry with a focus on new drivers and the path to new opportunities. The overall MEMS market is ~$10B now, growing to ~$21B by 2017. While the MEMS markets continue to grow, they are still only ~10% of the value of the end markets they enable. Accelerometer / gyroscope systems with 6 degrees of freedom (DOF) have largely been displaced by newer systems with 9 or 10 DOF. All of the growth notwithstanding, he remains skeptical of a $1T MEMS device market.

Stephen Breit of Coventor took us to the software design side of the business with his comments on realizing the full potential of MEMS design automation. If invention is the first wave, and manufacturing differentiation is the second wave, then the third wave is going to be innovation in design and integration. This is the catalyst that will be needed and has the potential to drive the hyper growth if the industry is to hit the $1T mark. Simulation of the integrated MEMS system will make it possible to compress the development cycle from the 2009 benchmark of 4-5 years. This vision includes process design kits and MEMS design kits (modules) similar to the design efficiencies achieved in ASICs. Coventor has a partnership with IMEC that was facilitated by IMEC’s integrated SiGe CMOS + MEMS integration scheme.

Russell Shumway of Amkor took us to the end of the production line with a discussion of high volume assembly and test solutions to support a rapidly growing MEMS market. He anticipates that there will be a greater tendency toward package standardization over the next 10-20 years, but the variety of packaging options is so large that the diversity will still be formidable.

Tristan Joo, Co-Chair of Mobile SIG of the Wireless Communications Alliance reviewed a few case studies of fusing sensors into mobile operating systems. Current smart phones already contain 12-18 sensors, including inertial, optical, touch, audio, magnetic, geo-positional and environmental. The future has a context-aware sensory data cloud in store for us. Smart phone apps that take full advantage of these sensors amount to less than a 0.5% share of apps downloads across all iPhone, Android and Windows OS platforms. I myself can use my smart phone as a bubble level, an audio dB sound meter, a thermometer, a compass, a ruler, a document scanner and a mechanical energy harvester to recharge my battery. But I’m a geek.

The remaining scheduled time comprised six brief presentations by companies showcasing new applications under the banner of “MEMS for the Rest of Us.”

Hillcrest Labs provides motion control systems for consumer electronics and other markets. Their flagship platform is the Freespace® MotionEngine™ that includes a gesture recognition engine and a variety of mobile, gaming and TV applications.

Movea develops data fusion software for processing sensor data into usable information. It is a spin-off of CEA-Leti in France. Fundamental elements of human motion have been compiled into a periodic table, cleverly presented as the Chemistry of Motion.

Sensor Platforms provides data fusion software in their FreeMotion™ library with the objective of being hardware agnostic. He favors mobile devices that respond to human action and context, not in the sense of obeying gestures and commands, but more in the sense of recognizing what’s going on and acting accordingly. For example, when your smart phone calendar says you’re in a meeting, a really smart phone will silence most calls and allow vibration only for a select short list of callers. The end result is to use the available data and context to anticipate intent.

Syride makes a rugged sports-oriented GPS device for tracking speed, elevation and location for hobbies such as surfing, sailing, skiing, skydiving and hang gliding. I use “Map My Walk,” which I will henceforth think of as the couch potato analog of Syride.

VectorNav Technologies is a hardware and software company that takes consumer level motion systems and upgrades them to industrial strength using established aerospace technology. Applications include human exoskeletons for the handicapped, and human motion capture for movies and medical applications. I’m pretty sure I misunderstood when I heard something about a home Cruise missile.

Xsens specializes in sensor fusion software for smart phones, tablets and sports applications. On-body MEMS sensors enable a new paradigm for body motion capture, embodied in a 17 sensor system integrated in a Lycra body suit. The system has already been used in developing video games.

May 22, 2012 — Invensas Corporation, a wholly owned subsidiary of Tessera Technologies Inc. (NASDAQ:TSRA) and provider of semiconductor technologies, debuted bond via array (BVA) technology, an ultra-high-I/O semiconductor packaging alternative to wide-I/O through silicon via (TSV) packaging.

BVA offers package performance for mobile electronics in the established package-on-package (PoP) architecture with copper wire bonds for stack interconnects. PoP designs package die and stack packages, instead of stacking die within a package with TSVs or other technologies. BVA PoP enables reduced pitch and a higher number of interconnects in the PoP perimeter stacking arrangement. It has demonstrated scalability to a 0.2mm pitch. It takes PoP from 240 pins to 1200 pins.

BVA PoP suits applications processor + memory device stacks, increasing processor-to-memory bandwidth. Simon McElrea, president of Invensas, says the PoP structure could enable higher resolution, faster frame rate video streaming, faster search, higher-resolution multi-screen, multi-application operation, more life-like gaming and high-resolution 3D applications — all requirements of mobile devices.

McElrea noted that the PoP structure of BVA is a cost-effective semiconductor assembly method to achieve these high performance requirements in a small form factor. The ultra-high I/O offered by BVA exceeds what is possible with solder ball stacking and solder-filled laser via approaches, Invensas says.

Invensas will present its BVA PoP solution at the Electronic Components and Technology Conference (ECTC) at the Sheraton San Diego Hotel and Marina in San Diego, CA. Titled "Fine Pitch Copper PoP for Mobile Applications" the paper will be part of Session 31, "Applications With 3D Technology," at 4:45 PM on Friday, June 1, 2012. Invensas will also exhibit at ECTC in booth 107 on May 30 and 31, 2012.

Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. (Nasdaq:TSRA), acquires, develops, and monetizes strategic intellectual property (IP) in areas such as circuitry design, memory modules, 3-D systems, and advanced interconnect technologies, to serve the dynamic mobile, storage and consumer electronics sectors. Internet: www.invensas.com.

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May 19, 2012 — Amkor Technology Inc. (NASDAQ:AMKR) plans to build a state-of-the-art factory and global research and development center in the Incheon Free Economic Zone, which is located in the greater metropolitan area of Seoul, Korea. The new factory and R&D center will focus on the design, development and full scale production of innovative semiconductor packaging and test services for leading semiconductor and electronic manufacturing companies.

May 14, 2012 — At the 15th Symposium on Polymers for Microelectronics (May 8-10 in Wilmington, DE), TSMC and Yole Developpement gave plenary presentations on the use of polymeric materials in wafer-level packaging (WLP) from foundry and overall industry perspectives.

The most controversial comment came from TSMC’s Doug Yu, senior director of front-end and back-end technology development, who challenged the current nomenclature and pronounced that the versatile interposer technology should be called

Solid State Technology is proud to announce that David McCann will speak at The ConFab 2012. The event will be held June 3-6, 2012 at The Encore at The Wynn in Las Vegas. David McCann is Sr Director for Packaging R&D at GLOBALFOUNDRIES in Malta, New York.  In this role, Dave is responsible for Packaging R&D and back-end strategy and implementation.

David will speak on the evolution toward silicon-based interconnect and packaging, which is having profound impact on how we think about technology development and the supply chain. “Previously, companies in incremental steps of the supply chain could develop products relatively independently,” he notes in his abstract. “Now they must work together to create solutions, or fail their common customers.  Although the shortest path to market may be for the foundry to do everything in-house, the path to the best solutions that will enable competitive costs and high volume adaption will be flexible supply chains with collaborative partnering, flexibility, and transparency.”

In a session focused on advanced packaging and progress in 3D Integration, David will be joined by fellow presenters Sandeep Bharathi, vice president of engineering, Xilinx; Ron Huemoeller, senior vice president, 3DAmkor; and Bill Chen, ASE Fellow and Sr. Technical Adviser, ASE Inc. The chair of the session is Abe Yee, Dir. Adv.Technology & Package Development, Nvidia Corp.

Prior to GLOBALFOUNDRIES, David worked at Amkor Technology for 11 years, most recently leading the BGA, Flip Chip and MEMS product groups.  He was responsible for extensions of package technology, bump, applications, and business performance.  Prior to this, Dave was responsible for the fcBGA and fcCSP business group at Amkor.  He led cross-functional teams in various areas including networking product strategy, mobile product development, large die/lead free flip chip development, and wafer level product strategy.  David worked closely with Amkor factories in Asia.

Prior to Amkor, David worked at Biotronik, GmbH in Portland, OR.  Biotronik is a developer and manufacturer of implanted medical devices including defibrillators and pacemakers.  David worked at Biotronik for 9 years and had various roles in Production, Process Engineering, Product Engineering, and Flip Chip implementation.  His last role at Biotronik was leading the assembly, interconnect, and product transition from wire bond to flip chip.

David has supported the Electronic Component and Technology Conference for more than 10 years.  This year he is Conference General Chair.

April 26, 2012 — After pioneering low-cost wafer- and panel-based glass and silicon interposers in Phase 1 of its SiGI consortium, Georgia Tech Packaging Research Center (GT-PRC) is beginning Phase 2 in June.

The industry consortium involves about ~30 semiconductor, package, and related supply-chain companies from the US, Europe, and Asia. They developed glass and silicon interposers with 10x higher I/Os than conventional organic packages, at 2-10x lower cost per mm2 than back end of line (BEOL) silicon interposers.

SiGI Phase 1 has demonstrated technologies to:

  • handle ultra-thin glass and silicon wafers and panels,
  • form small through-package vias (TPV) at fine pitches with high throughput and high reliability,
  • and make 5