Category Archives: 3D Integration

Xperi Corporation announced a partnership with global semiconductor foundry, UMC. This strategic partnership will enable the companies to support the growing demand for Invensas ZiBond and Invensas DBI 3D semiconductor technologies.

Together, Xperi and UMC will further optimize and commercialize the ZiBond and DBI technologies for a wide range of semiconductor devices including image sensors, radio frequency (RF), MEMS, display drivers, touch controllers, SoC, analog, power and mixed-signal devices. Wafer to wafer (W2W) and die to wafer (D2W) bonding and 3D interconnect implementations will be employed to address the requirements of a variety of applications within the mobile, consumer, automotive, communication, industrial and Internet of Things (IoT) industries.

“As a world-leading semiconductor foundry, we are committed to delivering leading-edge solutions to our customers,” said Wenchi Ting, vice president of specialty technologies at UMC. “By partnering with Xperi and the Invensas team, true pioneers in direct and hybrid bonding technologies, we continue to be well-positioned to meet our customers’ evolving requirements for advanced wafer bonding technologies.”

“We are excited to join forces with UMC, a premier global foundry engaged in every major sector of the electronics industry, to expand the production base for our ZiBond and DBI bonding and 3D interconnect platforms,” said Craig Mitchell, president, Invensas. “We look forward to working together to proliferate these enabling technologies into a wide range of high volume semiconductor applications.”

ZiBond is a low temperature homogenous direct bonding technology that forms strong bonds between semiconductor wafers or die with same or different coefficients of thermal expansion. This technology is used in image sensors, MEMS and various RF front-end devices.

DBI is a low temperature hybrid direct bonding technology that allows semiconductor wafers or die to be bonded with exceptionally fine pitch 3D electrical interconnect. This technology is suited for various semiconductor devices such as image sensors, DRAM, MEMS and RF devices.

Products employing these technologies are found in smartphones, tablets, laptops, cameras, televisions and gaming consoles, as well as in industrial, automotive and IoT electronic devices.

In August, Toshiba Electronic Devices & Storage Corporation (“Toshiba”) will start mass production and shipments of “TPWR7904PB” and “TPW1R104PB”, 40V N-channel power MOSFETs for automotive applications. They are housed in the DSOP Advance(WF) packages that deliver double-sided cooling, low resistance, and small size.

The new products secure high heat dissipation and low On-resistance characteristics by mounting a U-MOS IX-H series chip, a MOSFET with the latest trench structure, into a DSOP Advance(WF) package. Heat generated by conduction loss is effectively dissipated, improving the flexibility of thermal design.

The U-MOS IX-H series also delivers lower switching noise than Toshiba’s previous U-MOS IV series, contributing to lower EMI[1].
The DSOP Advance(WF) package has a wettable flank terminal structure[2].

Applications
– Electric power steering
– Load switches
– Electric pumps

Features
– Qualified for AEC-Q101, suitable for automotive applications
– Double-sided cooling package with top plate[3] and drain
– Improved AOI visibility due to wettable flank structure
– U-MOS IX-H series featuring low On-resistance and low noise characteristics

Main Specifications

　(@Ta=25 ℃)

Part
number

Absolute
maximum ratings

Drain-source
On-resistance
RDS(ON) max (mΩ)

Built-in
Zener Diode
between
Gate-Source

 Series Package

Drain-
source
voltage
VDSS
(V)

Drain
current
(DC)
ID
(A)
@VGS＝6 V @VGS=10 V
TPWR7904PB 40 150 1.3 0.79 No U-MOSⅨ-H

DSOP
Advance(WF)L
TPW1R104PB 120 1.96 1.14

DSOP
Advance(WF)M

Notes:
[1] EMI (Electromagnetic interference)
[2] Wettable flank terminal structure: A terminal structure that allows AOI (Automated Optical Inspection) of installation on boards.
[3] Be aware that the top plate has the same electric potential as the sources; however, not intended for an electrode.

In its recently released Mid-Year Update to The McClean Report 2018, IC Insights forecasts that the 2018-2022 global GDP and IC market correlation coefficient will reach 0.95, up from 0.88 in the 2010-2017 time period.  IC Insights depicts the increasingly close correlation between worldwide GDP growth and IC market growth through 2017, as well as its forecast through 2022, in Figure 1.

As shown, over the 2010-2017 timeframe, the correlation coefficient between worldwide GDP lgrowth and IC market growth was 0.88, a strong figure given that a perfect correlation is 1.0.  In the three decades previous to this timeperiod, the correlation coefficient ranged from a relatively weak 0.63 in the early 2000s to a negative correlation (i.e., essentially no correlation) of -0.10 in the 1990s.

IC Insights believes that the increasing number of mergers and acquisitions, leading to fewer major IC manufacturers and suppliers, is one of major changes in the supply base that illustrate the maturing of the industry that is helping foster a closer correlation between worldwide GDP growth and IC market growth. Other factors include the strong movement to the fab-lite business model and a declining capex as a percent of sales ratio, all trends that are indicative of dramatic changes to the semiconductor industry that are likely to lead to less volatile market cycles over the long term.

In 2017, IC industry growth was greatly influenced by the “Capacity/Capital Spending Cycle Model” as the DRAM and NAND flash markets surged and served to drive total IC industry growth of 25%.  It would initially appear that the strong correlation coefficient between worldwide GDP growth and total IC market growth that had been evident from 2010 through 2016 had disappeared in 2017.  However, IC Insights does not believe that is the case.

When excluding the DRAM and NAND flash segments from the IC market in 2017, the remainder of the IC market displayed an 11% increase, which closely correlates to what would be expected given a worldwide GDP increase from 2.4% in 2016 to 3.1% in 2017.  Moreover, the three-point decline in the total IC market growth rate forecast for 2018, when excluding DRAM and NAND flash (from 11% in 2017 to 8% in 2018), is expected to mirror the slight decline expected for worldwide GDP growth this year as compared to last year.  Thus, excluding the amazing surge for the DRAM and NAND flash markets in 2017 and 2018, IC Insights believes that the trend toward an increasingly close correlation between total IC market growth and worldwide GDP growth is still largely intact.

Figure 1

 

The VCSEL industry took a strategic turn last year with the release of the latest iPhone. Indeed the leading smartphones manufacturer, Apple revealed to the entire world a new smartphone with innovative 3D sensing function based on VCSEL technology. Apple’s technical choice directly impacted the VCSEL industry and Yole Développement (Yole) announces today impressive market figures in its new technology and market report, VCSEL – Technology, Industry and Market Trends: more than 3.3 billion units in 2023 with a 31% CAGR between 2017 and 2023. This explosion is changing the future of all players of the VCSELs supply chain including: OEMs , integrators, device manufacturers, epi houses, foundries, equipment and material suppliers.

VCSEL – Technology, Industry and Market Trends report performed by Yole, presents an in-depth analysis of the VCSEL industry with its supply chain and competitive landscape. It exposes a comprehensive review of the main VCSEL applications including in-depth analysis of the consumer and automotive landscapes with 3D sensing, LiDAR and gas sensing. Under this report, Yole details VCSEL device market size, broken down by application and segment, and the related MOCVD reactor market. In addition, Yole’s analysts bring to light a significant overview of the VCSEL IP landscape. VCSEL manufacturing processes, associated challenges, recent trends and player positioning are also well analyzed.

3D sensing – and more – in smartphones will drive the VCSEL market for the next five years, announces the market research and strategy consulting company. Make sure to get an up-to-date picture today of this explosive market.

Data communications was the first industrial application to start integrating VCSELs. Their sweet spot has been in short-distance data communication due to their low power consumption and competitive price compared to EELs . Driven by the development of datacenters, the VCSEL market and production boomed in the 2000s with the internet’s popularity, and then grew steadily. Some new applications for VCSEL emerged, like laser printers and optical mice, but weren’t strong growth drivers.

Only in 2014, almost 20 years since the first use of the technology in datacom, VCSELs started to make their way into high volume consumer smartphones. But this coupling with sensors for proximity sensing and autofocus functions was only the beginning of the VCSEL success story.
“In 2017 Apple released the iPhone X, with a 3D sensing function based on this technology,” explains Pierrick Boulay, Technology & Market Analyst at Yole. And he explains: “The iPhone X integrates three different VCSEL dies for the proximity sensor and the Face ID module, and made the VCSEL market explode in 2017, propelling overall revenue to about US$330 million.”

Only in 2014, almost 20 years since the first use of the technology in datacom, VCSELs started to make their way into high volume consumer smartphones. But this coupling with sensors for proximity sensing and autofocus functions was only the beginning of the VCSEL success story.
“In 2017 Apple released the iPhone X, with a 3D sensing function based on this technology,” explains Pierrick Boulay, Technology & Market Analyst at Yole. And he explains: “The iPhone X integrates three different VCSEL dies for the proximity sensor and the Face ID module, and made the VCSEL market explode in 2017, propelling overall revenue to about US$330 million.”

Good iPhone X sales have now triggered the interest of other smartphone brands in this breakthrough 3D sensing function. Less than one year after the release of Apple’s flagship, its competitors are now following the same trend and starting to integrate 3D sensing technologies. Xiaomi and Oppo were the quickest on the draw, with the Xiaomi Mi8 and the Oppo Find X models presented in the second quarter of 2018. Other leading smartphone players like Huawei, Vivo or Samsung are also expected to integrate VCSELs into their flagship models by 2019.

In this context, the explosion of VCSEL demand initiated in 2017 will persist for the next five years, potentially multiplying the business opportunity more than tenfold. During that time, the technology might also find some new growth drivers into some other high volume applications such as automotive Light Detection and Ranging (LiDAR) or gas sensors.

“This trend will likely cause rapid evolution in the VCSEL industry in coming years in the form of investment, new entrants and M&A ”, comments Pars Mukish, Business Unit Manager SSL & Display activities at Yole.

VCSEL market volume is expected to grow from 652 million units in 2017 to more than 3.3 billion units in 2023. This booming trend is likely to trigger interest in VCSEL technology at many industry levels, including OEMs, integrators, device manufacturers, epi houses, foundries, equipment and material suppliers. To be able to follow this booming demand, more than 100 MOCVD reactors will be needed, which is likely to please companies that supply this equipment, such as Aixtron, Veeco and Taiyo Nippon Sanso.

Yole expects therefore strong investment and proliferation in the VCSEL industry with the entry of several new players, mostly from the LED industry, whose technology is similar.
Since 2016, Yole analysts’ have already seen some M&A, like ams’ acquisition of Princeton Optronics and Osram’s deal for Vixar and investment in manufacturing expansion or supply chain reinforcement, like Apple investing US$390 million in Finisar. Yole expects the bulk of these investments to occur in the coming years.

And once VCSEL hype reaches its peak, Yole also expects a necessary consolidation phase with more M&A occurring at all level of the supply chain and to support different strategies
•  Vertical integration – from system to module and/or from module to component
•  Application diversification – from datacom to sensing
•  Business diversification – from LED or EEL devices to VCSELs

In a key move to inspire the next generation of innovators, the School District of Osceola County (SDOC) today became the first school district to join the SEMI High Tech U (HTU) Certified Partner Program (CPP), a curriculum that prepares high-school students to pursue careers in STEM fields.

Under the program sponsored by the SEMI Foundation, SDOC will independently deliver HTU programs to local students at the Osceola Technical College Campus, in Kissimmee, Florida. SEMI Foundation awarded SDOC the certification today at a graduation ceremony for HTU students.

“SDOC’s partnership with the SEMI Foundation gives young people and families in our community exposure to high-tech career opportunities and the educational pathways to reach their goals,” said Debra Pace, superintendent of School District of Osceola County. “Our industry partners – including Mercury, University of Central Florida, BRIDG, Osceola Technical College, imec, Neo City and the Osceola County Education Foundation – have all made it possible for SDOC to offer this amazing opportunity to students.”

“We are delighted to partner with SDOC in our common goal to motivate the next generation of innovators,” said Leslie Tugman, executive director of the SEMI Foundation. “The School District of Osceola County is well-positioned to put college-bound high school students on a track that speeds the time from graduation to employment in high technology. SDOC’s certification is a tremendous benefit for it students, the community and employers in the fast-growing Central Florida tech corridor.”

To win the certification, SDOC delivered HTU over the past three years with guidance and instruction from SEMI. SDOC is only the second organization to receive the certification.

The nonprofit SEMI Foundation has been delivering its flagship program, SEMI High Tech U, at industry sites around the world since 2001 to emphasize the importance of STEM skills and inspire young people to pursue careers in high-technology fields. HTU students meet engineers and STEM volunteer instructors from industry for site tours and hands-on classroom activities such as etching wafers, making circuits, coding and training for professional interviews.

SEMI’s Certified Partner Program identifies organizations that provide quality training and can recruit and educate local high-school students in the value of careers in science, technology, engineering and math (STEM). Participating organizations are trained to deliver the unique SEMI curriculum with the support of volunteer instructors from the high-tech and STEM industries. SEMI High Tech U is the longest-running STEM career exploration program in the United States with documented student impact. Since inception, SEMI has reached over 8,000 high-school students in 12 states and nine countries with its award-winning program.

SEMI Foundation is a 501(c)(3) nonprofit charitable organization founded in 2001 to support education and career awareness in the electronics and high-tech fields through career exploration programs and scholarships. For more information, visit www.semifoundation.org.

Semiconductor Research Corporation (SRC), today announced the release of $26 million in added research funding for its New Science Team (NST) Joint University Microelectronics Program (JUMP). JUMP will fund 24 additional research projects spanning 14 unique U.S. universities. The new projects will be integrated into JUMP’s six existing research centers. NST will continue to distribute funds over its five-year plan, and industrial sponsors are welcome to join to further accentuate those plans.

The awards have been given to 27 faculty and will enhance the program’s expertise in technical areas such as atomic layer deposition (ALD), novel ferroelectric and spintronic materials and devices, 3D and heterogeneous integration, thermal management solutions, architectures for machine learning and statistical computing, memory abstractions, reconfigurable RF frontends, and mmWave to THz arrays and systems for communications and sensing.

“The goal of the NST project is not only to extend the viability of Moore’s Law economics through 2030, but to also change the research paradigm to one of co-optimization across the design hierarchy stack through multi-disciplinary teams,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “Our strategic partnerships with industry, academia, and government agencies foster the environment needed to realize the next wave of semiconductor technology innovations.”

“A new wave of fundamental research is required to unlock the ultimate potential of autonomous vehicles, smart cities, and Artificial Intelligence (AI),” said Dr. Michael Mayberry, Senior Vice President and Chief Technology Officer of Intel and the elected Chairman of the NST Governing Council. “Such advances will be fueled by novel and far-reaching improvements in the materials, devices, circuits, architectures, and systems used for computing and communications.”

The JUMP program, a consortium consisting of 11 industrial participants and the Defense Advanced Research Projects Agency (DARPA), is one of two complementary research programs for the NST project—a 5-year, greater than $300 million SRC initiative launched this January. JUMP and its six thematic centers will advance a new wave of fundamental research focused on the high-performance, energy-efficient microelectronics for communications, computing, and storage needs for 2025 and beyond.

Toshiba Memory Corporation today held a groundbreaking ceremony for the first semiconductor fabrication facility (fab), called K1, in Kitakami, Iwate prefecture, in northeastern Japan. On its completion in autumn 2019, the facility will be one of the most advanced manufacturing operations in the world, dedicated to production of 3D flash memory.

Toshiba Memory continues to advance technologies in flash memory. The company is now leading the way forward with advances in its BiCS FLASH™, its proprietary 3D flash memory.

Demand for 3D flash memory is increasing significantly on fast growing demand for enterprise servers, datacenters and smartphones. Toshiba memory expects continued strong growth in the mid and long term. The new facility will make a major contribution to business competitiveness in corporation with Yokkaichi operations.

The new facility will not only be the largest Toshiba Memory fab, but it will be the most advanced as well. It will be constructed with a seismic isolation structure that allows it to absorb earthquake tremors, and it will reduce environmental loads by deployment of the latest energy-saving manufacturing facilities. It will also introduce an advanced production system that uses artificial intelligence (AI) to boost productivity. Decisions on the new fab’s equipment investment, production capacity and production plan will reflect market trends.

Toshiba Memory expects to continue its joint venture investments in the new facility based on ongoing discussions with Western Digital Corporation.

Going forward, Toshiba Memory will continue to actively cultivate initiatives aimed at strengthening competitiveness, including timely capital investments and R&D in line with market trends. The company will also contribute to the development of the regional economy of Iwate prefecture, Japan.

Toshiba Memory Corporation today announced that it has developed a prototype sample of 96-layer BiCS FLASH, its proprietary 3D flash memory, with 4-bit-per-cell (quad level cell, QLC) technology that boosts single-chip memory capacity to the highest level yet achieved.

Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September, and expects to start mass production in 2019.

The advantage of QLC technology is pushing the bit count for data per memory cell from three to four and significantly expanding capacity. The new product achieves the industry’s maximum capacity [1] of 1.33 terabits for a single chip which was jointly developed with Western Digital Corporation.

This also realizes an unparalleled capacity of 2.66 terabytes with a 16-chip stacked architecture in one package. The huge volumes of data generated by mobile terminals and the like continue to increase with the spread of SNS and progress in IoT, and the need to analyze and utilize that data in real time is expected to increase dramatically. That will require even faster than HDD, larger capacity storage and QLC products using the 96-layer process will contribute a solution.

A packaged prototype of the new device will be exhibited at the 2018 Flash Memory Summit in Santa Clara, California, USA from August 6th to 9th.

Looking to the future, Toshiba Memory will continue to improve memory capacity and performance and to develop 3D flash memories that meet diverse market needs, including the fast expanding data center storage market.

Micron (Nasdaq:MU) and Intel today announced an update to their 3D XPoint™ joint development partnership, which has resulted in the development of an entirely new class of non-volatile memory with dramatically lower latency and exponentially greater endurance than NAND memory.

The companies have agreed to complete joint development for the second generation of 3D XPoint technology, which is expected to occur in the first half of 2019. Technology development beyond the second generation of 3D XPoint technology will be pursued independently by the two companies in order to optimize the technology for their respective product and business needs.

The two companies will continue to manufacture memory based on 3D XPoint technology at the Intel-Micron Flash Technologies (IMFT) facility in Lehi, Utah.

“Micron has a strong track record of innovation with 40 years of world-leading expertise in memory technology development, and we will continue driving the next generations of 3D XPoint technology,” said Scott DeBoer, executive vice president of Technology Development at Micron. “We are excited about the products that we are developing based on this advanced technology which will allow our customers to take advantage of unique memory and storage capabilities. By developing 3D XPoint technology independently, Micron can better optimize the technology for our product roadmap while maximizing the benefits for our customers and shareholders.”

“Intel has developed a leadership position delivering a broad portfolio of Optane products across client and data center markets with strong support from our customers,” said Rob Crooke, senior vice president and general manager of Non-Volatile Memory Solutions Group at Intel Corporation. “Intel Optane’s direct connection to the world’s most advanced computing platforms is achieving breakthrough results in IT and consumer applications. We intend to build on this momentum and extend our leadership with Optane, which combined with our high-density 3D NAND technology, offer the best solutions for today’s computing and storage needs.”

By Ed Korczynski

To fulfill the promise of the Internet of Things (IoT), the world needs low-cost high-bandwidth radio-frequency (RF) chips for 5th-generation (5G) internet technology. Despite standards not being completely defined yet it is clear that 5G hardware will have to be more complex than 4G kit, because it will have to provide a total solution that is ultra-reliable with at least 10 Gb/second bandwidth. A significant challenge remains in developing new high-speed transistor technologies for RF communications with low power to allow IoT “edge” devices to operate reliably off of batteries.

At the most recent Imec Technology Forum in Antwerp, Belgium, Nadine Collaert, Distinguished MTS of imec, discussed recent research results from the consortium’s High-Speed Analog and RF Program. In addition to working on core transistor fabrication technology R&D, imec has also been working on system-technology co-integration (STCO) and design-technology co-integration (DTCO) for RF applications.

Comparing the system specifications needed for mobile handsets to those for base-stations, transmitter power consumption should be 10x lower, while the receiver power consumption needs to be 2x lower. Today using silicon CMOS transistors, four power amplifiers alone consume 65% of a transmitter chip’s power. Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) built using compound semiconductors such as gallium-arsenide (GaAs), gallium-nitride (GaN), or indium-phosphide (InP) provide excellent RF device results. However, compared to making CMOS chips on silicon, HBT and HEMT manufacturing on compound semiconductor substrates is inherently expensive and difficult.

Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) both rely upon the precise epitaxial growth of semiconductor layers, and such growth is easier when the underlying substrate material has similar atomic arrangement. While it is much more difficult to grow epi-layers of compound semiconductors on silicon wafers, imec does R&D using 300-mm diameter silicon substrates with a goal of maintaining device quality while lowering production costs. The Figure shows cross-sections of the two “tracks” of III-V and GaN transistor materials being explored by imec for future RF chips.

III-V on Silicon and GaN-on-Silicon RF device cross-sections, showing work on both Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) for 5G applications. (Source: imec)

Imec’s High-Speed Analog/RF Program objectives include the following:

  • High-speed III-V RF devices using low-cost, high-volume silicon-compatible processes and modules,
  • Co-optimization with advance silicon CMOS to reduce form factor and enable power-efficient systems with higher performance, and
  • Technology-circuit design co-optimization to enable complex RF-FEM modules with heterogeneous integration.

5G technology deployment will start with speeds below 6GHz,  because technologies in that range have already been proven and the costs are known. However, after five years the frequency will change to the “mm-wave” range with the first wavelength band at ~28GHz. GaN material with a wide bandgap and high charge-density has been a base-station technology, and it could be an ideal material for low-power mm-wave RF devices for future handsets.

This R&D leverages the III-V on silicon capability that has been developed by imec for CMOS:Photonic integration. RF transistors could be stacked over CMOS transistors using either wafer- or die-stacking, or both could be monolithically co-integrated on one silicon chip. Work on monolithic integration of GaN-on-Silicon is happening now, and could also be used for photonics where faster transistors can improve the performance of optical links.