Category Archives: 3D Integration

January 19, 2012 – BUSINESS WIRE — Optomec Inc., additive manufacturing systems provider, opened its new and expanded Advanced Applications Lab and Product Development Facility in St. Paul, MN. The facility will help Optomec grow its Aerosol Jet technology for advanced printed electronics applications.

The new facility comprises 7600 square feet of office and general laboratory space and will be utilized for both advanced development of Aerosol Jet Printed Electronics Applications and for new product engineering. Dr. Mike Renn will continue his role as Director of Aerosol Jet Advanced Application Development, and John Lees, recently appointed Director of Aerosol Jet New Product Development, will lead the product engineering team at the new facility. In conjunction with the expansion, Optomec is looking to double its local staff.

Optomec’s Aerosol Jet systems for Printed Electronics utilize a proprietary material deposition process to direct write high resolution electronic circuitry, components and even complete devices on 2D and 3D surfaces. The Aerosol Jet deposition process is highly efficient and supports a wide variety of electronic materials compared to traditional subtractive manufacturing processes. Aerosol Jet systems can be used to both lower costs and enhance performance of current electronic devices, as well as to enable the creation of next generation products, such as 3D semiconductor packaging, high efficiency solar cells and solid oxide fuel cells.

Also read: Optomec aerosol jet printing featured as wire bond, TSV alternative

Optomec provides of additive manufacturing solutions for high-performance electronics, solar, medical, and aerospace & defense applications using its Aerosol Jet printed electronics technology and LENS powder-metal fabrication technology. To learn more, visit http://www.Optomec.com

January 13, 2012 — For the first time, Apple Inc. has publicly published a list of over 150 companies that the electronics giant says represent 97% of its procurement expenditures for materials, manufacturing, and assembly of products worldwide.

See the suppliers here: http://images.apple.com/supplierresponsibility/pdf/Apple_Supplier_List_2011.pdf

The disclosure is part of a broad supplier responsibility reporting initiative at Apple. The US-based company has had its ties to China’s Hon Hai Precision Industry Co, the world’s largest contract electronics manufacturer by revenue and the parent firm of Hong Kong-listed Foxconn International, scrutinized recently.

In 2011, Apple conducted 229 audits throughout its supply chain, an 80% increase over 2010. In 2011, the company launched a specialized auditing program to address environmental concerns about certain suppliers in China. Third-party environmental engineering experts worked with Apple to audit 14 facilities. Apple also broadened its age verification program in 2011. The full progress report is available from Apple at http://images.apple.com/supplierresponsibility/pdf/Apple_SR_2012_Progress_Report.pdf

January 11, 2012 — Increased I/O density on chips, power/performance requirements, yield/cost requirements and form factor constraints (mobile) are coming to push increased use of flip chip, 2.5D and 3D technologies. This trend benefits the packaging subcontractors in the semiconductor industry, argues Credit Suisse Taiwan Analyst Randy Abrams, as outsourcing rises.

Larger packaging subcontractors, like Amkor (AMKR), ASE, and SPIL, will take market share from smaller sub-contractors, Credit Suisse predicts. Large packaging houses like Amkor have invested in 3D packaging technologies, such as through silicon via (TSV) fabrication, silicon interposers, etc. They are also well-positioned for an industry shift occuring from wire bonding to flip chip, which enables higher I/O density.

Credit Suisse reports that the flip-chip trend has led to under-utilization of traditional wirebonder assets. Even if these assets are fully depreciated, they often carry fixed costs (labor, overhead). Amkor is responding to this trend by trying to penetrate the NAND market for wirebonding. It also is in talks to purchase old packaging assets from Toshiba. ASE and SPIL are migrating their capacity aggressively from gold to copper wire. ASE is also courting Japanese IDMs to outsource their discrete low-pin count in-sourced packaging needs.

The packaging houses will need to watch for foundry TSMC, which has made special references to chip on wafer on silicon (CoWoS) in its last earnings call, Credit Suisse notes. ElectroIQ.com contributor Dr. Phil Garrou reports that TSMC pushes for a pure foundry model for 2.5 and 3DIC — quoting Doug Yu, senior director of integrated interconnect, TSMC who said that TSMC was readying to take on full beginning-to-end interposer manufacturing. Read Garrou’s TSMC repeats call for foundry-centric 2.5/3D industry. Credit Suisse asserts that fabless chip companies may prefer the packaging houses over a foundry-based 3D packaging model, and companies will leverage various chip and foundry suppliers for the best commercial position, mixing and matching chips in 3D packages.

Other than the foundry encroachment, semiconductor assembly & test service (SATS) providers need to watch out for cyclical weakness in semiconductors, due to the inventory correction in H2 2011, Credit Suisse points out. Improving cyclical momentum through the year will improve absorption of wirebonder capacity discussed above, the analysts note.

Learn more about Credit Suisse at www.credit-suisse.com/global/en/.
 
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January 10, 2012 — The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.

SMTAI papers are sought on electronics assembly as well as advanced packaging and components. Packaging papers can cover 0.3mm Pitch Area Array, 3D Packaging and Integration, BGA/CSP, Biomedical Packaging, Bumping, Chip on Board, Direct Chip Attach, Embedded and Miniature Passives, Failure Analysis, Fine Lead Pitch, Flip Chip, High Temperature Packaging, Lead Finishes, Leadless Packages (LGA/QFN/BTC), MEMS and Sensors, Package on Package (PoP), Photonics, Photovoltaics and Solar Packaging, Reliability, Solid and Collapsible Wafer Bumps, Through Silicon Vias (TSVs), Tin Whiskers, and Wafer Level Packaging (WLP). See SMTA’s Call for Papers site to check out all the suggested topics for emerging technologies, electronics assembly, supply chain/business papers, PCB technology, process control, and energy papers.

SMTA International offers Best of Conference Presentation, Best of Proceedings Paper, and Best International Paper awards at the show.

Abstracts (300 words) are due March 12, 2012, and can be submitted here: http://www.smta.org/smtai/call_for_papers.cfm. All abstracts must be submitted online and will not be accepted by e-mail.

Proposals are also solicited from individuals interested in teaching educational courses related to surface mount technology, advanced packaging, and electronics manufacturing.

Paper manuscripts and course workbooks are due by July 27, 2012. Papers should be 6-15 pages long (including graphics) and describe significant results from experiments, emphasize new techniques, or contain technical, economic, or appropriate test data. Presentation materials and papers must be original, unpublished, and non-commercial in nature.

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John Ellis will keynote IWLPC, discussing Cyber-Physical Terrorism in his presentation, "A Trojan Chip in Your Smartphone? It’s Coming…"

The topic is malicious circuits receiving commands via social networks. Hacking a few highly-followed celebrity accounts would provide a perfect avenue for distributing ‘self-destruct’ codes to millions of Trojan chips. A widespread, cyber-physical attack, which would have been almost impossible to pull off just a few years ago, could soon become reality.  

After graduating from the University of Texas with a Master’s in Mechanical Engineering, John worked at Sandia National Labs, where he focused on R&D projects for the Department of Energy, Department of Defense, National Institute of Standards and Technology, and other federal agencies. His experience includes nuclear weapons testing, missile guidance (Advanced Cruise Missile), air-borne and space-borne imaging systems (Predator UAV), and semiconductor manufacturing. John

January 10, 2012 – Marketwire — Teledyne Microelectronic Technologies, a business unit of Teledyne Technologies Incorporated, will expand its optical packaging portfolio in a partnership with Zephyr Photonics. The companies will package Zephyr Photonics’ proprietary vertical-cavity surface-emitting laser (VCSEL) technology with Teledyne Microelectronics Technologies’ multi-chip module (MCM) and fiber optic assembly technologies.

The companies’ resulting optical interconnect technologies will meet bandwidth and harsh-environment requirements for defense, aerospace, commercial aviation, and oil and gas applications. Zephyr Photonics’ proprietary high-temperature VCSELs can withstand temperatures over 155

January 10, 2012 — Inari Berhad, semiconductor packaging services provider, signed a memorandum of understanding (MOU) to acquire 100% of the equity of Amertron Global, an investment holding company incorporated in the Cayman Islands. The businesses, Amertron Incorporated in the Philippines and Amertron Technology (Kunshan) Co. Ltd in China, provide microelectronics and optoelectronics manufacturing services.

The Amertron Global Group employs approximately 3700 employees in facilities located in the Philippines and China with about 26,700 square metres of manufacturing floor space. Based on audited financial statements for the 6 months financial period ended 30 June 2011, Amertron Global registered net sales of USD66.2 million and profit after tax of USD2.9 million for the half year period. Learn more about Amertron at http://www.amertron-global.com/index.html.

The acquisition of Amertron Global is in line with the Inari Group

January 5, 2012 — Standards org JEDEC Solid State Technology Association released a new standard for wide I/O mobile DRAM: JESD229 Wide I/O Single Data Rate (SDR). Wide I/O mobile DRAM increases die integration — stacking chips with through silicon via (TSV) interconnects with a system on chip (SoC) — and improves bandwidth, latency, power, weight and form factor.

The standard defines features, functionalities, AC and DC characteristics, and ball/signal assignments. It is particularly well-suited for applications requiring extreme power efficiency and increased memory bandwidth (up to 17GBps). Wide I/O offers twice the bandwidth of the previous generation standard, LPDDR2, at the same rate of power consumption.

Also read: IPC, JEDEC devise package strain test and JEDEC releases serial NOR Flash standard

Mobile wide-I/O DRAM are used in smartphones, tablets, handheld gaming consoles and other mobile devices. Sophie Dumas, Chairman of the JC-42.6 Subcommittee for Low Power Memories, notes that the high-resolution displays, high-quality graphics, and multi-tasking capabilities of next-gen devices require technologies like wide-I/O mobile DRAM.

JESD229 may be downloaded free of charge from the JEDEC website at http://www.jedec.org/sites/default/files/docs/JESD229.pdf.

JEDEC develops standards for the microelectronics industry. All JEDEC standards are available online, at no charge. For more information, visit www.jedec.org.

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January 3, 2012 — Solid State Technology asked top analysts and technologists to provide insights on the transition to 22nm semiconductor devices. Read through all the forecasts, or click by topic, from chip design to lithography, CMP, and materials, to the packaging side of the equation.

Check out the first article, from Dean Freeman of Gartner Inc:
Semiconductor process technology challenges at 22nm

And a design perspective, from Gary Smith of Gary Smith EDA:
At 22nm, leave chip layout to the experts

Defect discussion, with Howard Ko of Synopsys:
First order effects at 22nm

The lithography point of view, with Aki Fujimura, D2S:
Mask-wafer double simulation: A new lithography requirement at 22nm

What 22nm means for the packaging providers, from E. Jan Vardaman, TechSearch International:
22nm requires foundry-to-packaging-house cooperation

An in-depth look at gate stacks and materials, with Mohith Verghese, ASM America:
Strained silicon and HKMG take the stage at 22nm

The role of a mid-node, TSVs, and 450mm at 22nm, with Art Zafiropoulo, Ultratech:
Will 22nm need a mid-node?

The CMP point of view, from Michael A. Fury, Techcet Group:
Startups pave the way to CMP at 22nm

Driving technologies for 22nm lithography, from Franklin Kalk, Toppan Photomasks:
20nm mask technology relies on SMO and DPT

How 3D IC fits into the 22nm equation, with Paul Lindner, EV Group:
3D integration key to 22nm semiconductor devices