December 6, 2011 – JCN Newswire — Singapore’s A*STAR Institute of Microelectronics (IME) and 3D IC developer Tezzaron Semiconductor signed a research collaboration agreement to develop and exploit advanced through silicon interposer (TSI) technology.
This includes improving and optimizing silicon interposers and creating standardized process, slows, and process design kits (PDKs). In the near term, the partners will look to develop TSI for MEMS and silicon photonics, based on the 3D IC experience.
Early production devices use IME’s TSI technology with 3D ICs from Tezzaron. The team will fabricate devices in IME’s state-of-the-art 300mm R&D fab.
Once a technology is established, IME will drive the TSI Consortium for further optimization and functional demonstrations, to be launched in early 2012. "To build momentum in customer adoption and technology, IME will launch a TSI Consortium in early 2012, to facilitate greater cooperation between foundry, outsourced semiconductor assembly and test providers (OSATs), equipment vendors and supply chain partners to expedite the integration of the supply chain," commented Professor Dim-Lee Kwong, executive director of IME.
Silicon interposers — often considered a bridge technology to true 3D IC — are a "vital component for heterogeneous system integration," asserts Robert Patti, CTO of Tezzaron.
IME and Tezzaron have cooperated on research since 2001. Tezzaron used IME’s copper line technologies wafer stacking development. IME researches TSVs, 3D IC cooling, vertical interconnects and interposers; Tezzaron focuses on designing and building wafer-stacked 3D-ICs in its FaStack process.
Tezzaron Semiconductor specializes in 3D wafer stacking and TSV processes, cutting-edge memory products, and wide-ranging collaborations. Information about Tezzaron is available at http://www.tezzaron.com/.
The Institute of Microelectronics (IME) is a research institute of the Science and Engineering Research Council of the Agency for Science, Technology and Research (A*STAR). For more information, visit IME on the Internet: http://www.ime.a-star.edu.sg or go to A*STAR’s website: www.a-star.edu.sg.
December 6, 2011 – Practitioners, students and other interested parties assembled in Atlanta at the recent Global Interposer Technology workshop (GIT) on the Georgia Tech campus to discuss where the technology stands and where it is going.
Xilinx, the first to reach HVM with their Vitrex-7 2000T FPGA, detailed various aspects of their 2.5D interposer product. Suresh Ramalingam, senior director of advanced package design, announced that their Virtex product, which uses a 21mm
December 2, 2011 — Using the advanced through-silicon via (TSV) fabrication process at IBM (NYSE:IBM), Micron Technology Inc. (NASDAQ:MU) will begin producing its Hybrid Memory Cube. The companies claim that this is the first CMOS design to go commercial with TSV interconnects.
HMC parts will be manufactured at IBM’s advanced semiconductor fab in East Fishkill, NY, using the company’s 32nm, high-K metal gate (HKMG) process technology. IBM will present the details of its TSV manufacturing breakthrough at the IEEE International Electron Devices Meeting (IEDM) on December 5 in Washington, DC. Check out an IEDM preview slideshow here.
"This is a milestone in the industry move to 3D semiconductor manufacturing," said Subu Iyer, IBM Fellow. "The manufacturing process we are rolling out will have applications beyond memory, enabling other industry segments as well. In the next few years, 3D chip technology will make its way into consumer products, and we can expect to see drastic improvements in battery life and functionality of devices."
Micron’s Hybrid Memory Cube (HMC) reportedly achieves speeds 15 times faster than today’s technology. It combines high-performance logic with Micron’s state-of-the-art DRAM using TSVs. HMC prototypes show bandwidth of 128 gigabytes per second (GB/s), using 70% less energy to transfer data, and boast a form factor that is 10% of the footprint of conventional memory. Applications include large-scale networking and high-performance computing, industrial automation and high-end consumer products.
"HMC is a game changer, finally giving architects a flexible memory solution that scales bandwidth while addressing power efficiency," said Robert Feurle, VP of DRAM marketing for Micron.
Micron Technology Inc. provides advanced semiconductor solutions: DRAM, NAND and NOR flash memory, as well as other innovative memory technologies, packaging solutions and semiconductor systems for use in leading-edge computing, consumer, networking, embedded and mobile products. Micron’s common stock is traded on the NASDAQ under the MU symbol. To learn more about Micron Technology, Inc., visit www.micron.com.
IBM is a leading semiconductor technology company. For more information about IBM’s advanced semiconductor products and manufacturing processes, visit www.ibm.com/chips.
3D ICs with Cu through-silicon vias (TSV) are getting a lot of attention, but some issues relating to potential damage still have to be worked out — e.g., having Cu and Si in such close proximity can lead to physical stresses, and their fabrication processes can cause damage too. IBM researchers devised annular (hollow cylindrical) Cu TSVs to connect upper-level wires in a functional 32nm SOI 3D embedded memory module (128-Mb DRAM on top of a 96Mb DRAM, each using 0.039
November 23, 2011 – BUSINESS WIRE — The Design Automation Conference (DAC) is soliciting semiconductor industry experts for participation in invited sessions, panels, and other events at the 49th DAC, June 3-7, 2012 in San Francisco, CA.
Nominees should be experts in:
Analog/Mixed-Signal and RF
Beyond Die-Integration and Package/Hybrid/Board Design
Circuit Simulation and Interconnect Analysis
Embedded HW Design and Applications
Embedded SW Tools and Design
FPGA Design Tools and Applications
High-Level Synthesis
Logic Synthesis and Circuit Optimization
New or Emerging or Specialized Design Technologies
Power Analysis and Low-Power Design
System-Level Communication and Networks on Chip
Timing Analysis and Design for Manufacturability
Physical Design and Manufacturability
Signal Integrity and Design Reliability
System-Level Design and Co-Design
Testing
Verification
The experts will be entered in the DAC Speakers’ Bureau, which acts as the resource center from which the DAC Executive Committee can contact interesting and experienced speakers from all areas of EDA for participation at the 49th DAC. Third-party nominations, highlighting prior presentations by the nominated speaker that generated substantial audience interest, are especially appreciated. Self-nominations are also accepted. Nominations can be made at http://www.dac.com/speakers+bureau.aspx.
The Design Automation Conference (DAC) covers the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. Learn more at www.dac.com.
The companies will focus on developing "new processes and solutions in the field of wafer-level packaging," said Frank P. Averdung, president and CEO, SUSS MicroTec AG, noting SVTC’s complementary skill set in research and innovation. The companies will jointly develop and characterize new lithography and wafer-bonding technologies.
SUSS MicroTec consigned alignment and bonding equipment to one of SVTC
November 11, 2011 — Backside-illuminated CMOS image sensors (BSI) capture light directly on the silicon light-sensitive layer. They have a higher sensitivity in a broader spectrum than the mainstream frontside-illuminated imagers (FSI). And in the field of high-end and specialty imagers, they have started to compete with established charged-coupled device (CCD) technology.
BSIs, however, are more difficult to fabricate than FSIs. They require advanced wafer thinning, surface passivation techniques to maximize sensitivity, and careful substrate engineering to minimize crosstalk. Using the possibilities of BSI technology, imager researchers are also looking at alternative architectures, producing pixels and readout electronics as separate dies and stacking those using high-density microbumps and TSVs.
Detecting and capturing light with image sensors: CCD versus CMOS
Silicon is an ideal material to make image capturing sensors, for use in digital cameras and other products. It absorbs that part of the electromagnetic spectrum that — through a lucky quirk of nature — matches the light that is visible with our eyes.
The first commercial sensor chips were CCDs, appearing around 1985. By the early 1990s, the CMOS process was well-established and CMOS imagers started to appear, first for low-end imaging applications or low-resolution high-end applications. Since then, the market has split into two segments. For low-cost, high-volume imagers, CMOS imagers have clearly overtaken CCDs. In high-performance, low-volume applications, CMOS and CCD imagers share the market, mainly because CCD technology still allows for a lower noise. In total, in 2010, the market share of CMOS imagers was 58% vs CCDs; this share is forecast to grow to 66% in 2015 [1].
When light strikes a CCD pixel sensor, it is stored as a small electrical charge. Next, these pixel charges are transported, one at a time, to the output stages. And only then, on a separate chip, are the voltages converted to the digital domain, to bits. A CMOS imaging chip, on the other hand, is an active pixel sensor: each pixel has its own circuitry. CMOS image sensors are fabricated using standard CMOS production processes, so they require less-specialized manufacturing facilities than CCDs. Also, they consume less energy, are faster, are better scalable, and allow integrating on-chip image processing electronics.
The roadmap in the image sensor industry is mostly concerned with decreasing price per pixel while increasing the number of pixels on a given chip surface — reducing the pixel pitch. Currently, high-volume sensor production capacity is moving from 200mm fabs to 300mm fabs, with minimum features reaching 65nm, and resolutions pushing beyond 16 megapixels [1].
But next to this, R&D centers such as imec are also concerned with improving the image quality. Not so much looking for smaller pixels, but for optimal performance. Capturing more photons (improving the quantum efficiency, QE), capturing them in the correct pixels (reducing or eliminating the crosstalk), and capturing a larger part of the light spectrum. Solutions are used in specialty imagers, e.g. for space applications (Figure 1).
Figure 1. 1 megapixel backside-illuminated hybrid imager consisting of a substrate with a passive photodiode array pixel-wise connected to a CMOS readout circuit using 22.5
November 10, 2011 — OSRAM Opto Semiconductors increased its IR Power Topled with lens (SFH 4258S/4259S) optical output by 80% over the standard version by integrating a thin-film chip. The infrared (IR) light emitting diode (LED) has the same surface area and drive current.
OSRAM Opto used Nanostack technology to create the thin-film chip with 2 p-n junctions grown one on top of the other. Because of the series circuit, the voltage is higher by approximately a factor of 2. The increased output in the same package footprint suits designs where real estate, even illumination, and cost are factors, said OSRAM’s representatives.
The IR Power Topled produces 80mW optical output power from an operating current of 70mA. The new LED emits at a wavelength of 850nm. It is available with beam angles of
November 7, 2011 — SEMATECH has created an online 3D Standards Dashboard, allowing 3D semiconductor and MEMS interconnect professionals to exchange standards activity information. This Dashboard, managed by SEMATECH’s 3D Enablement Center, will help develop standards in the 3D packaging field with the help of IEEE Standards Association, JEDEC, SEMI, and Si2.
3D heterogenous integration lacks uniform standards for key manufacturing parameters, which are neccessary for an orderly supply chain and high-volume production. Because standards are needed in many areas and over broad technology bases, the Dashboard is designed to improve information sharing, which will accelerate standard development and adoption, and avoid duplication of effort.
Companies involved in 3D production can use the 3D Standards Dashboard to find existing standards as well as to identify and track standards development activities in areas such as design, testing and production. Additionally, the 3D Standards Dashboard provides a proactive forum for facilitating collaborative discussions on perceived gaps in standardization activities and for identifying which standards development organizations (SDO) will best meet the need for a specific standardization activity.
SEMATECH, IEEE, JEDEC, SEMI, and Si2 invite fabless, fab-lite and IDM companies, outsourced semiconductor assembly and test (OSAT) suppliers, and EDA process tool and materials suppliers worldwide to participate by visiting http://wiki.sematech.org/3D-Standards.
