Category Archives: 3D Integration

November 4, 2011 — Numerous global semiconductor suppliers maintain assembly and test operations in Thailand. Many of these facilities have been affected by the disaster. IHS iSuppli pulled together a list of those affected, and those that have thus-far escaped damage.

Semiconductor suppliers whose test and assembly operations have been affected include ON Semiconductor, ROHM Semiconductor, Lapis Semiconductor, Hana Semiconductor, Stars Microelectronics, Vigilant Technology, STATS ChipPac and Toshiba.

ON Semiconductor: ON Semiconductor Corporation (Nasdaq:ONNN) believes that its SANYO Semiconductor division’s Thai operations in the Rojana Industrial Park in Ayutthaya, Thailand have been severely damaged by the flood. Another facility in Bang Pa In, previously unaffected, is now flooded. Read details on ONNN’s closings here.

ROHM: Sole facility in Thailand has been closed since Oct. 19. The facility conducts assembly and test for integrated circuits, discrete transistors, diodes, resistors and tantalum capacitors. ROHM is attempting to shift production to other locations.

Lapis: Rojana Industrial Park operation is closed. Lapis is looking to supply product from alternative locations.

Hana Semiconductor, a subcontractor for Microchip, Texas Instruments (TI) and others: Thai facility is currently flooded, and no assessment is possible. TI and Microchip are relocating as much production as possible to other qualified locations.

Stars Microelectronics: Ayutthaya facility has been flooded. A subcontractor for Microchip, Stars is relocating operations to other sites and anticipates that the impact on production of Microchip

November 1, 2011 — In a Solid State Technology webcast, presented by DigitalOptics Corporation, a wholly owned subsidiary of Tessera Technologies, Dr. Giles Humpston, Director of Applications, presented Lens Tilt in Small Auto-Focus Cameras.

What is a small camera? Most would qualify it as about 1cm3, disposable, cheap (<$1/MP) and integrated into digital cameras, cell phones, webcams, etc.

Figure 1. Simplified diagram of a miniature camera.

Small cameras range from the simplest, most rugged and most limited fixed-focus systems to higher-end auto-focus (AF) devices that are the subject of Humpston’s talk. AF cameras have electronic controls that allow them to focus much closer (as on a barcode) and in lower light than other designs.

Auto-focus cameras have evolved from large, highly mechanical, expensive devices. Today the majority of AF cameras are based on voice-coil motor (VCM) technology which works on magnetic attraction/repulsion principles.

Figure 2. A VCM miniature camera set up, with springs and magnets to control lens movement.

VCM pros? The devices are compact, almost silent, and cheap, with good focus range. Cons? They are slow, and not the best choice for video. Power consumption is in the hundreds of milliwatts (mW), and the smaller the VCM, the higher the power consumption. VCMs also suffer from lens tilt (Figure 3).

Figure 3. Lens tilt. Springs can change length, pulling the lens, or a user can tilt the lens through the influence of gravity and cause permanent changes by dropping the device. Tilt control is expensive and increases package form factor.

High-performance next-generation auto-focus cameras will not use VCMs, says Dr. Humpston.

Alternatives are in development– electrostatic silicon actuators manufactured as micro electro mechanical systems (MEMS).  The comb drive actuator — the most common design — is very low power.

Figure 4. Comb drive actuator.

Silicon MEMS can also be formed into a complete auto-focus component, with springs, etc. on one chip. With no mechanical play, MEMS actuator actions are extremely reproducible, operation is faster and optical performance is maintained through a wide range. With only one moving lens, as opposed to the entire optical train, image quality is desensitized to lens tilt. The module form factor becomes thinner as well.

Table. Key features of an auto-focus camera using VCM and MEMS.

 

MEMS

VCM

Actuator dimensions (mm)

7.4 x 7.4 x 1.7

8.5 x 8.5 x 5.0

Peak Power*

0.5mW

250mW

Repeatability

1µm

10µm

Hysteresis

3µm

20µm

Speed+

5ms

30ms 

Reliability cycles

10 million

1 million

Reflow compatible

Yes

No

* MEMS peak power <30µW, remainder is the driver chip

+ Half-stroke settling time

VCM alternatives based on MEMS will start hitting the market commercially in 2012, Humpston says. Get all the design details and in-depth discussion of lens options, reliability, and more in the webcast: Attend now.

Dr. Humpston is a metallurgist with his name on patents and publications, including articles on nanotechnology and semiconductors for ElectroIQ.

Attend the webcast: FREE WEBCAST: Lens Tilt in Small Auto-Focus Cameras

Read Dr. Humpston’s article: Nanotechnology for semiconductors

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November 2, 2011 – PRNewswire — MEMS foundry Silex Microsystems licensed its Silex Sil-Via through-silicon-via (TSV) packaging platform to Nanoshift for use in early development of complex MEMS products.

Silex Sil-Via license agreements allow customers to take complex MEMS devices from prototype to volume production faster, said Peter Himes, vice president of marketing and strategic alliances for Silex Microsystems. Through the Silex Sil-Via license, Nanoshift can bring customer designs to market faster, reducing development time and project risk. Transition to full-scale production on Silex’s 6" or 8" wafer fab lines will be "seamless."

Nanoshift chose the Silex Sil-Via platform because it has been "proven in many high-volume [MEMS] applications," said Salah Uddin, co-founder of Nanoshift.

Silex Sil-Via is a proprietary technology for through silicon via (TSV) interconnects: a full-wafer thickness via comprised of a DRIE etched post surrounded by an isolating material. The resulting interconnect is low impedance, mechanically robust, and avoids the thermal mismatch of metal-based via technologies. Silex brought it into production in 2006 and it has been used on over 100 designs. It can be implemented for wafer-level packaging (WLP) as well as MEMS interconnects.

Silex Microsystems is the world’s largest pure-play MEMS foundry. For more information, please visit www.silexmicrosystems.com.

Nanoshift LLC is a privately held design and development company that specializes in emerging technologies. For more information, please visit www.nanoshift.net.

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November 1, 2011 – Invensas and Allvia have agreed to a patent asset transfer and collaborative development of 3D IC packaging technology, though the description and terms are somewhat nebulous. (We’re awaiting further clarification from both companies.)

Here’s what we know from the official PR statement:

— Invensas is buying 64 patents from Allvia, mostly involving 3D ICs and packaging — namely through-silicon via (TSV) and silicon interposer ("2.5D") technology.
— The two firms have entered into "a two-year collaborative partnership" to further develop technology and IP in 3D IC packaging.

Updated 11/2:  Here’s what we know from a quick email back-and-forth with Invensas and Allvia reps:

— The patent transfer is for everything Allvia owns: silicon interposer for system-on-silicon, TSV, plus micro bumping for wide IO mobile and 3DS DRAM, confirmed Invensas president Simon McElrea. However, Allvia retains a "back license" to offer the IP to other customers. Essentially it’ll continue as a foundry business for any licensees, including Invensas. (McElrea adds that Invensas will hire 3-5 extra 3D engineers.)

— Allvia will continue as an "independent" and "separate" entity. CEO Sergey Savastiouk sees this deal as a way to "allow our interposer and TSV technology to reach the market more broadly and more quickly," adding "support and marketing outreach" to help it get more customers. Moreover, Allvia cleaves off the IP side of its business plan to focus on the manufacturing side. "Someone else will have a task to monetize Allvia IP and to aggressively license and enforce it as well as co-develop future IP," he noted.

"2.5D and 3D are the next technology nodes on DRAM and mobile technology roadmaps," McElrea explained in an email. The Allvia patent purchase & dev agreement will "strengthen our position to license our existing and new customers in our served markets — in short, where they go, we will be."

November 1, 2011 — 2.5D, 3D and Beyond – Bringing 3D Integration to the Packaging Mainstream will take place November 9 in Santa Clara, CA. The MEPTEC conference follows the trend of 3D (through-silicon vias [TSV]) and 2.5D packaging (side-by-side die interconnection on a silicon interposer) moving from roadmap to factory production.

Large, vertically integrated and volume-driven companies are using these advanced packaging technologies for new products, like stacked memory, or ASIC, ASSP, FPGA, and standard product designs. Opportunities include solving latency and bandwidth issues in high-end systems and combining different silicon processes or disparate functions such as MEMS, image sensors, and optics.

MEPTEC

October 25, 2011 — Xilinx Inc. (Nasdaq:XLNX) began shipping its Virtex-7 2000T field programmable gate array (FPGA), a programmable logic device with 6.8 billion transistors: 2 million logic cells, a die-stack architecture, low power consumption, and a more flexible design than large ASICS and monolithic FPGAs.

Figure 1. Xilinx Virtex-7 2000T FPGA.

Xilinx structured the FPGA using its stacked silicon interconnects, a 2.5D IC packaging technology makes the FPGA the equivalent to 20 million ASIC gates. Four separate FPGA die are interconnected on a passive silicon interposer that has 10,000+ high speed interconnects (Figure 1). Aligning die on vertical planes (side by side) avoids power, heat, and reliability issues of multiple die stacked on top of each other. The interposer actually reduces stress on the low-k dielectric atop the FPGA.

Through-silicon vias (TSVs) with 10:1 aspect ratios are used to package the device. The TSVs do not interfere with system signal integrity, Liam Madden, corporate vice president of FPGA Development and Silicon Technology at Xilinx, noted in a press event for the product launch. Microbumps are used on the die, providing a huge aerial density increase over C4NP. These fab and packaging techniques are available to the industry already, Madden said. Xilinx is just combining them in a smart way to decrease power use and increase performance.

The device consumes about 19 watts at full operation, comprable to the performance of 4 monolithic FPGAs using 112 watts. In a product demonstration, the device had all cells performing some calculation, with 180000 MIPS computing power and only 20W power consumption. The software for operation cuts down on compile time by 4x.

Figure 2. Product demonstration.

The Virtex-7 2000T shares a unified architecture with Xilinx

October 24, 2011 — The 2012 Symposia on VLSI Technology & Circuits, to be held in Hawaii, June 12-14 (Technology) and 13-15 (Circuits), will accept innovative, original work on microelectronics, ranging from gate stacks and advanced lithography to 3D packaging.

A single registration fee covers both symposia, which overlap so that technologists and circuit/system designers can interact and attend each other

October 19, 2011 — Nanotech accelerator SVTC Technologies, wet chem equipment maker Amerimade Technology, and chemicals company Shanghai Sinyang Semiconductor Materials will collaborate on electroplating processes for through-silicon via (TSV) that are production-ready for advanced packages and micro electro mechanical systems (MEMS).

By combining a commercialization specialist with tool and materials providers, this partnership will be able to develop new electroplated film processes for TSV in over 95,000 square feet of state-of-the-art cleanroom, staffed 24/7 with SVTC’s engineering team, electroplating toolsets from Amerimade, and chemical formulae from Shanghai Sinyang.

The aim is a commercially viable process for electroplating through-silicon via interconnects that can be ramped up to volume production at advanced packaging houses, semiconductor manufacturers, and MEMS fabrication and packaging facilities.

Shanghai Sinyang Semiconductor Materials Co. Ltd. provides research and development, design, and manufacturing of advanced chemicals for the electronics industry, specifically for semiconductor manufacturing, packaging test and assembly, solar cell manufacturing, and avionics. More information can be found at www.sinyang.com.cn.

Amerimade Technology Inc. designs, manufactures and provides long-term field support for wet chemical processing systems. More information can be found at www.amerimade.com.

SVTC Technologies provides development and commercialization services for innovative semiconductor process-based technologies and products, cost effectively and in an IP-secure manner. More information can be found at www.svtc.com.

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October 18, 2011 — Semiconductor equipment supplier SUSS MicroTec, in partnership with temporary bonding adhesive maker TMAT, will deliver SUSS MicroTec’s new-generation high-volume temporary wafer bond tool clusters to a leading IDM.

The integrated device manufacturer (IDM) will temporarily bond thinned 300mm wafers to carrier wafers for 3D packaging processes. The company makes logic and memory devices. Installation will take place in Q4 2011.

Also read: Thin wafers win majority in electronics by 2016

TMAT adhesive materials and the TMAT process for temporary bonding will be implemented on the SUSS cluster. TMAT and SUSS MicroTec collaborated to tweak the tools and materials to enable the customer’s wafer and process requirements over several months. High throughput was a main purchasing factor for the IDM.

SUSS MicroTec Group is a supplier of equipment and process solutions for microstructuring applications, including back-end packaging. Learn more at www.suss.com.

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October 11, 2011 – PRNewswire — EV Group (EVG) and All Silicon System Integration Dresden (ASSID) of Fraunhofer IZM will jointly develop high-volume 3D IC manufacturing processes, focusing on temporary bonding and debonding processes to support chip-to-wafer bonding with up to 600um-thick topographies.

ASSID will host the collaboration with its 300mm 3D manufacturing/packaging line in Dresden, using EVG850 TB/DB systems already installed there. The partners will also use ASSID test samples and demonstrator materials. EVG will contribute 3D IC fab tool and process expertise. ASSID’s established network with other research institutes and universities can be used to verify viability of new developments.

Chip-to-wafer bonding allows manufacturers to test die prior to 3D bonding, resolving low-yield wastage associated with bad die. Also, heterogeneous technologies (different sizes, feature dimensions, etc.) can be bonded in 3D die stacks with a broad range of functionality (logic, memory, mixed signal, photonics, etc.) in a compact form factor.

Today’s advanced temporary bonding/debonding processes support bonded wafer topographies up to 100um thick. More complex die structures require thicker wafers. EVG and ASSID will work on improving rigid backgrinding support during wafer thinning and low-vertical-force debonding to avoid defects during debonding.

ASSID also announced today that it has installed an Altatech Semiconductor 300mm CVD system for advanced TSV fab.

Fraunhofer IZM-ASSID is tasked with developing 3D packaging technologies, including new interconnect and assembly processes. As part of the Fraunhofer IZM Institute, which specializes in transferring IC advanced packaging and system integration research results to industry, ASSID is integrated into a technology network of applied research institutes and universities.

EV Group (EVG) makes wafer-processing tools for semiconductor, MEMS and nanotechnology applications. More information is available at www.EVGroup.com.

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