Category Archives: 3D Integration

October 11, 2011 – PRNewswire — MEMS supplier STMicroelectronics (NYSE:STM) has implemented through-silicon vias (TSV) in high-volume micro electro mechanical system (MEMS) devices. ST is using TSV in its smart sensors and multi-axis inertial modules.

The leading-edge packaging technology creates short vertical interconnects instead of wire bonds in ST’s multi-chip MEMS devices.

ST’s Benedetto Vigna, corporate VP and GM of ST’s Analog, MEMS and Sensor Group, reports that its high-volume MEMS packages using TSV are smaller, suiting the needs of consumer products integrating MEMS, such as smartphones.

STMicroelectronics has been producing high-volume MEMS devices for the consumer electronics sector for 5 years. More than 1.6 billion ST MEMS chips has been sold to date.

Also read: MEMS motion sensors’ continuing evolution in commercial markets by Jalinous (Jay) Esfandyari, STMicroelectronics, in association with MEMS Industry Group (MIG)

STMicroelectronics supplies semiconductors for multimedia convergence and power applications. Further information on ST can be found at www.st.com.

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October 11, 2011 — All Silicon System Integration Dresden (ASSID), a microelectronics packaging center under the Fraunhofer IZM Institute, installed a single-wafer, multi-chamber AltaCVD 300 from Altatech Semiconductor in its 970sq.m. Dresden cleanroom.

ASSID started pilot production of 3D ICs using the 300mm chemical vapor deposition (CVD) tool. The AltaCVD 300 deposits conformal dielectric liners inside through silicon vias (TSV) in die stacks for 3D ICs and system-in-packages (SiP). TSV aspect ratios are up to 10:1, with hole diameters as small as 10

October 6, 2011 — Thanks to MEMS, 3D packaging, LEDs, power devices, and other applications, thinned wafers will be the majority of wafers in the market by 2016, according to Yole D

October 4, 2011 – Bryan Rice, SEMATECH’s newly appointed director of strategic initiatives, tells SST what his new job entails: what he sees as his biggest challenges, which areas will keep SEMATECH’s main attention (hint: the "once and future king" of resources), and what new areas are being explored.

Prior to his litho directorship (replacing Michael Lercel who returned to his assignor IBM), Rice was SEMATECH’s immersion program manager, leading research into high-refractive index lens and immersion fluid materials, and also helped form the group’s double-exposure program (focusing on novel materials for litho-litho-etch patterning). He’s been at SEMATECH since 2006 as an Intel assignee.

Looking back on his tenure as SEMATECH’s litho director, Rice agreed that EUV’s slow progress was "obvious," with the biggest problem being high-power scanner sources. "We as an industry, including SEMATECH, didn’t get the job done; source power still isn’t where it needs to be," he said. The industry is now pouring resources into that problem. For SEMATECH itself, he noted that their competency is in masks, not sources, so they’ve focused on reducing mask defects. (Should SEMATECH have pushed harder to develop its own expertise and leadership in source development? "I grappled with that," he said, but "in the end, there have been multiple companies and maybe hundreds of millions of dollars spent and it’s still not solved. It’s an extremely difficult problem.")

In his new role as director of strategic initiatives, Rice will be tasked with putting together plans to extend SEMATECH’s core missions through the next 5-7 years — work that had been encroaching into the jobs of the individual SEMATECH program directors, to a point where it needed to be centralized into a standalone role. (It was simply "good timing," Rice said, that his tenure as litho director was simultaneously ending.) "Every so often we have to refresh the ideas, problems we have, that have reached their tipping point and ready to change direction," he told SST. "My job is to make certain that the direction changes we make are compatible with what the industry needs." ("The industry" means both SEMATECH members and potential future members, since SEMATECH is looking out several years into some emerging areas, he added.)

Though he only hinted at possible areas of special focus under his new leadership — "some ideas are in a very sensitive point, I can’t discuss publicly" — Rice noted that SEMATECH’s structure has changed, and it needs a "refresh" every couple of years to align with what the industry and member companies require. "Look at what we’re capable of doing and what we’d like to be capable of doing — those two, combined with problems that exist in the industry, I have to mesh them together," he said. That applies not only to SEMATECH’s four core areas (frontend processing/transistors, lithography, metrology, 3D integration) but other branches too, including possibly creating new programs that exploit synergies between those existing divisions. "Nothing is off the table," he said.

The biggest challenge Rice sees is personal: known as a litho expert, he’s now trying to come up to speed on the details in other technology areas. "I felt that I understood that subject matter extremely well — but I can’t say the same for the other areas I’m working on now," he said. As a result, he’s having to rely more heavily on expert advice from other team members at SEMATECH, "more than I had to in litho […] accepting the technical inputs at face-value without having the core experience." A similar challenge will be making sure those deeply involved in the SEMATECH technology programs are advancing them in the right direction: "they don’t work *for* me, but I have to convince them what work is going to be most effective. That’s going to be challenging," he said.

What’s the next big thrust for SEMATECH, to be pursued with the same zeal as its EUV efforts? Will it be III-V materials, 3D TSVs, or other next-generation structures? "The next EUV is …EUV," Rice declared. "Until that’s in production, it’s the once and future king of resources." Assuming EUV is "the workhorse technology" that will "take us through critical layer patterning through the end of the decade," there’s plenty of work to be done in the next 5-7 years to keep it at the top of SEMATECH’s priorities. Once that goal is reached, though, he sees "plenty of challenges coming" in the future: "Other litho areas are on the way," he added, declining to offer specifics. (New SEMATECH litho director Stefan Wurm also hinted at new litho work to be pursued, also declining to offer details.)

October 3, 2011 – BUSINESS WIRE — Rudolph Technologies Inc. (NASDAQ:RTEC), semiconductor and related process characterization equipment supplier, shipped its Wafer Scanner 3880 3D Inspection System, multiple NSX Macro Defect Inspection Systems and its Discover Yield Management Software Suite to a leading semiconductor manufacturer for use in developing through silicon via (TSV) structures in advanced 3D ICs. Rudolph cites system speed, accuracy, and flexibility in the multiple-tool win.

September 29, 2011 — Samsung Electronics Co. Ltd. developed a high-performance 64GB embedded memory with 64Gb NAND. The package contains an 8 die stack in a low profile for smartphones, tablets and other mobile devices.

Samsung showcased the package at the 8th annual Samsung Mobile Solutions Forum held at the Westin Taipei. The company also introduced a 32nm dual-core application processor, Exynos 4212; an ultra high-speed LPDDR3 memory; and advanced CMOS image sensors, including a 1/8.2-inch 1.2 Megapixel (Mp) imager and a 1/2.3-inch 16Mp high-sensitivity imager.

The 64GB embedded multimedia card (e-MMC) houses Samsung

September 20, 2011 — The first annual Global Interposer Technology Workshop (GIT 2011) will take place November 14-15 at Georgia Institute of Technology (GA Tech), convening industry experts, global academic researchers, and student leaders to share interposer technology research, development, applications, markets and manufacturing infrastructure.

Interposers are used to create "More than Moore" 3D or 2.5D semiconductor packaging.

To present at the conference, submit a title for consideration (presentation or poster) by October 2 at http://www.prc.gatech.edu/git2011/papers.html. Selected submitters will be notified by October 15.

Technical sessions will cover electrical and mechanical design, silicon and glass interposers, chip- and board-level interconnect, interposer applications and markets, and the manufacturing infrastructure for these technologies.

The plenary keynote lineup is as follows:

  • Subramanian Iyer, IBM – "Silicon Inteposers: The First Step Towards Three Dimensional Integration"
  • Doug C.H. Yu, TSMC – "Semiconductor Paradigm Shift and the Advantages of Foundry Integration"
  • Suresh Ramalingam, Xilinx – "Stacked Silicon Intereconnet: Road to Production"
  • Jerome Baron, Yole – "Interposer markets and Applications"
  • Rao Tummala, Georgia Tech – "3D Packaging Perspective at Georgia Tech 3D ICs vs 3D Interposer"

The event will feature posters presented by students along with the industry, research, and academia speakers.

GIT 2011 is sponsored by IEEE, CPMT, IMAP, iNEMI, and SEMI. Learn more at www.prc.gatech.edu/git2011.

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September 19, 2011 – At SEMICON Taiwan 2011, the SiP Global Summit consisted of forums on 3D IC technology, 3D IC test and embedded substrates. In the 3D IC technology forum leaders representing key segments of the eco-system shared their experiences in 2.5D and 3D ICs with a focus on technology roadmaps, supply chain manufacturing readiness, business models, and standardization.

Victor Peng, SVP at Xilinx, updated the audience on the ongoing commercialization of the company’s 7V2000T FPGA with "stacked silicon interconnect technology" (SSIT). The FPGA 28nm slices are assembled "side by side" on a silicon interposer with 65nm interconnect wiring. They found the interposer was an excellent way to handle the 28nm chip low-k fragility. Chip fabrication, interposer fabrication, and bumping are being done by TSMC; chip bumping and module assembly are being done by Amkor. Peng reports that they are on schedule for sampling in calendar year 2011. He also noted that Xilinx "believes in full 3D IC stacking (no interposer)" but that it will take a little longer for that technology to become standardized in the infrastructure.

Takayuki Watanabe, VP of Elpida‘s TSV packaging development group, described the company’s memory TSV production flow and how its 16Gb DDR3 module — two stacks, each stack consists of four low-power, 2Gb DDR3 SDRAMs fitted to a single interface chip using TSV — occupies 70% less space (11mm

September 16, 2011 — The Burn-in & Test Socket Workshop (BiTS Workshop) will change its name to The Burn-in & Test Strategies Workshop to reflect the "evolution of packaged ICs," announced Fred Taber, general chairman of the workshop.

The 2012 BiTS Workshop takes place March 4-7, 2012, in Mesa, AZ.

The event will cover next-generation solutions to burn-in and test while still gathering new work on traditional technologies, Taber continued. The BiTS Workshop is not deviating from its mission to present relevant work on "burn-in and test tooling for today’s IC package technologies," said Taber. It is now expanding to cover "what’s next."

Burn-in and test have changed along with the emergence and market adoption of advanced packaging technologies, including wafer-level packaging (WLP) and fan-out WLP, system in package (SiP), wafer-level test of chip scale packages (CSP), embedded die packages, flip chip packages, package-on-package (PoP), and other 3D packaging.

For more information about the BiTS Workshop, visit www.bitsworkshop.org.

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September 8, 2011 – BUSINESS WIRE — Invensas Corporation, a Tessera Technologies Inc. (Nasdaq:TSRA) wholly owned subsidiary, will demonstrate dual-face down (DFD) implementation of its new multi-die face-down (xFD) semiconductor packaging technology at the Intel Developer’s Forum this month.

The multi-die package is wire bonded, mounting ICs upside down and staggering them in a shingle-like configuration. The short wire bonds required resemble those of a window-BGA package. The design creates 25-35% vertical form factor savings from conventional packages. Speed-bin yield increases 50-70% thanks to the symmetric top and bottom die performance. Thermal management is improved with 20-30% better heat dissipation than conventional dual-die packages (DDPs), according to the company.

Invensas XFD is a "market-ready" packaging technology that can be performed on existing wire-bond lines. A parallel process packaging flow reduces manufacturing costs for the multi-die DRAM packages, specifically reducing materials usage, including gold.

The packages improve DRAM/memory capacity and performance, targeting data center servers, tablets/smartphones, and other applications. Simon McElrea, president of Invensas Corporation, touts "single-die package performance in a multi-die configuration" with density and cost advantages.

Invensas will demonstrate its DFD technology at the Intel Developers Conference in San Francisco’s Moscone Center, West Hall, Booth #414, September 13-15, 2011.

Invensas Corporation, a wholly owned subsidiary of Tessera Technologies, Inc. (Nasdaq: TSRA), acquires, develops and monetizes strategic intellectual property (IP) in areas such as circuitry design, 3D systems, memory modules and other enabling technologies. Go to www.invensas.com.

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