Category Archives: 3D Integration

(December 6, 2010) — ALLVIA, through-silicon via (TSV) foundry, will present its latest analysis on silicon interposers and embedded capacitors during the 3D Architectures for Semiconductor Integration and Packaging Forum in Burlingame, CA, December 9-11. Dr. Nagesh Vodrahalli, vice president of technology and manufacturing at ALLVIA, will present a discussion on December 9 titled "Silicon Interposers with TSVs and Embedded Capacitors for Advanced Logic Applications."

His discussion will address:

  • Drivers and status: VLSI packaging and 3D technologies
  • Silicon interposer as the next logical step in the evolution of VLSI packaging
  • Implementation of silicon interposers with embedded capacitors

ALLVIA  offers services for prototyping and full volume production of both front side and back side TSVs and have integrated embedded capacitors on silicon interposers, a key interface between a silicon device and an organic substrate needed for managing high interconnect densities.  Capacitance values higher than 1,500 nF/cm2 have been achieved for the embedded capacitors developed for delivering power to the devices.  3D integration with ALLVIA’s through-silicon via technology allows much closer access to high value capacitors than previously possible, leading to a much higher level of electrical performance.
 
3D Integration & Packaging Conference will be held at the Hyatt Regency San Francisco Airport Hotel in Burlingame, California, Dec. 8-10, 2010. See http://techventure.rti.org/
 
ALLVIA is a through-silicon via (TSV) foundry for prototyping and full volume production of both front side and back side TSVs to the MEMS and semiconductor industries as well as silicon etching, copper plating, photolithography, CMP, etc. For more information, visit www.allvia.com

(December 1, 2010 – BUSINESS WIRE) — This week at SEMICON Japan, Tegal Corporation (Nasdaq: TGAL), maker of specialized production solutions for the fabrication of advanced MEMS, power ICs and 3D ICs, will launch a new member of its ProNova family of high-density inductively coupled plasma (ICP) reactors for the company’s deep reactive ion etching (DRIE) series wafer processing products. The ProNova2 is targeted for fast-growing 200mm MEMS and 3D IC applications.

It is designed to improve on etch rates of comparative tools and increase DRIE productivity and yield benefits. In addition to demonstrating sustained high etch rates, the new reactor offers a three-fold improvement in ion uniformity. For some applications, the higher uniformity enables a 40%+ improvement in etch selectivity. The ProNova2 also allows users to adjust selected etch parameters across the ICP reactor plasma and diffusion zones. This allows for better control of etch process performance across the wafer which boosts the silicon DRIE etch flexibility needed for some advanced applications.

The first ProNova2 tool has been installed in a Japanese development laboratory where it is meeting the performance expectations set by Tegal’s France-based R&D team.

Porting established MEMS processes onto 200mm tools and then improving on the baseline process results has been a key challenge for 200mm MEMS fabrication. For silicon DRIE, these challenges include achieving higher etch rates, along with tighter control of tilt angles and etch profiles, and better etch depth uniformity across 200mm wafers. The ProNova reactor family was developed to address all key market requirements identified by the 200mm MEMS community which include Tegal’s 3D IC Through Silicon Via (TSV) commercial partners. With an improved ICP reactor geometry and plasma source design, the ProNova products target better etch depth uniformity and etch profiles, as well as better etch tilt angles across 200mm wafers when compared to traditional ICP sources.

The ProNova2 is immediately available to ship on Tegal 110, 200, 3200 and 4200 DRIE wafer processing systems. It is also compatible as a retrofit with Tegal and AMMS DRIE systems already in the field. As with the first member of the ProNova family, the product supports Tegal’s Super High Aspect Ratio Process (SHARP), which achieves etched feature aspect ratios of greater than 100:1 in production environments.

Tegal will showcase the new ProNova2 at SEMICON Japan 2010, Dec. 1-3 at the Makuhari Convention Center in Chiba, Japan. For more information, please visit Tegal at the Canon Marketing Japan booth, Number 3C-701.

Tegal provides specialized production solutions for the fabrication of advanced MEMS, power ICs and 3D ICs found in products like smart phones, networking gear, solid-state lighting, and digital imaging. For more information, visit www.Tegal.com.

Also read: DRIE from MEMS to wafer-level packaging

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by Dr Phil Garrou, contributing editor

December 1, 2010 – The first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits "3D-TEST" was held earlier this month in Austin TX, chaired by Yervent Zorian of Virage Logic and Erik Jan Marinissen of IMEC.

"The 3D topic is really being picked up by the test community now, commented Marinissen. "At the ITC [International Test Conference] last year coverage of 3D testing was limited. This year we see significant coverage in the main ITC meeting, followed by a this workshop dedicated to 3D Test issues which was attended by nearly 100 professionals."

Marinissen presented the early results of the IEEE Computer Societies standardization study group on 3D Test. The 42 corporate and institute participants include: AMD, ARM, Cadence, Cascade Microtech, Cisco, IBM, IMEC Infineon, ITRI, Mentor Graphics, Qualcomm, ST Micro, Synopsys, TI, TSMC and Verigy. The following standardization needs were identified:

Bob Patti, CTO of Tezzaron, discussed their form of built in self test (BIST) called Bi-STAR. He claims that Bi-STAR tests and compares 2304 bits/clock cycle, "more than 100× faster than can be achieved by any external memory tester." Reportedly Bi-STAR can test and repair bad memory cells, line drivers, and sense amps; shorted word lines and bitlines; leaky bits; and bad secondary bus drivers.

Sanjiv Taneja, VP for front-end design at Cadence, showed a long list of test challenges. Integration of design and test, he offered, is the only way to solve these complex issues, and concurrent optimization for area, timing, power, and testability is the only means to achieve required predictability.

Ken Smith of Cascade Microtech showed details on their high-density MEMS probe card technology, which makes 1g tip forces feasible and very low pad damage (and scrub marks <100nm deep) possible at 40μm array pitch.

 

Such lithographically fabricated probe cards "enable scalability which will lower cost just as IC linewidth scaling has reduced the cost of IC functions," Smith said. "Instead of probe costs being roughly proportional to pincount, the cost of a MEMS probe should be roughly proportional to the probe area."

Chen Hao, test engineer at TSMC, presented an assessment of the failure modes seen when fabricating 3D ICs with microbumps including issues with alignment, TSV voids, impurities at the bonding interfaces, nonuniformity in the insulation liner, and TSV delamination from the substrate due to the thermal stress and warpage.

Besides testing, thermal issues, electromigration, TSV redundancy, and ESD also need attention, Hao added.

Dr. Phil Garrou from Microelectronic Consultants of NC is a contributing editor for Solid State Technology and Advanced Packaging on www.ElectroIQ.com. Read his blog, Insights from the Leading Edge.

(November 30, 2010) — Rudolph Technologies Inc. (NASDAQ: RTEC), process characterization equipment and software provider for wafer fabs and advanced packaging facilities, is partnering with a major outsourced semiconductor assembly and test (OSAT) services manufacturer to provide its inspection and metrology capability in the development of stacked packaging processes. The process uses silicon interposer technology, sometimes referred to as 2.5D IC, as an intermediate step toward full blown 3D ICs.

“The NSX System will measure via depth, inspect for defects and provide 3D metrology of solder bumps. Rudolph is collaborating with several leading-edge companies in the assembly and test sector, and we believe this effort will help to ensure the continued successful development of our NSX Systems for 3D IC applications,” said Rajiv Roy, Rudolph’s vice president of business development and director of back-end marketing.

Roy adds, “We were selected for this development project because we were able to meet the customer’s current specifications, and they are willing to work with us to make adjustments to the NSX System as we move forward with this project.”

Silicon interposer technology allows manufacturers to stack multiple chips to improve performance and increase the computing power in a small volume. It is particularly attractive to makers of cell phones and other handheld devices that must combine various chips with different functionality in a small space. The silicon interposer provides high density, short path signal routing between the stacked chips without requiring drastic changes in the design and manufacture of the chips themselves. Also read: Xilinx stacked silicon interconnect creates multi-die FPGA

"This is an important step toward full-blown 3D ICs,” Roy continued. “There are still a number of hurdles, however, such as lack of standards and high manufacturing costs for through-silicon-via based 3D ICs in high volume.” Silicon interposer technology allows manufacturers to roll out production-worthy devices without the TSV standards in place, and without the need to modify existing devices already in production.

Rudolph’s NSX Series Macro Defect Inspection Systems help to reduce the manufacturing costs and time-to-market of integrated circuits (ICs). Their high throughput and high repeatability are well established in high-volume applications throughout the device manufacturing process. The NSX System, equipped with Discover Defect Analysis and Data Management software, quickly and accurately detects yield-inhibiting defects, providing quality assurance and valuable process information.

Rudolph Technologies Inc. designs, develops, manufactures and supports defect inspection, process control metrology, and data analysis systems and software used by semiconductor device manufacturers worldwide. Additional information can be found at www.rudolphtech.com.

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(November 30, 2010) — Alchimer S.A., a provider of nanometric deposition technology for through-silicon vias (TSVs), semiconductor interconnects and other electronic applications, said its Electrografting (eG) technology has been validated by scientists at RTI International (RTI).

RTI, the latest third-party organization to validate eG, presented its research findings at the IEEE 3D System Integration Conference (3DIC) in Munich, Germany, in November. The paper confirmed that electrografting is a proven technology for depositing "insulator, barrier and seedlayer into high aspect ratio TSVs for 3D integration applications."

Electrografting is Alchimer’s electrochemical process that enables the growth of extremely high-quality polymer and metal thin films. The company’s deposition technology reduces overall cost of ownership for high-aspect-ratio TSV metallization by up to two-thirds compared to conventional dry processes, and shortens time to market.

The RTI study analyzed a variety of film properties, including leakage current, breakdown voltage, flat-band capacitance, and voltage. 

"The eG films in particular had effective interface trap densities in the range of 1011 per cm2, which is an excellent result that is comparable to device-grade SiO2 and high-k gate dielectrics," the study said.

Scientists in the Center for Materials and Electronic Technologies at RTI integrated electrografted layers in RTI test vehicles and exposed them to autoclave (AC) and high-temperature storage (HTS) reliability testing. The autoclave test was conducted during 96 hours under 121°C, 100% relative humidity and 2 bar absolute pressure. High-temperature storage was performed during 20 hours at 205°C.

"Both tests showed strong results with no significant difference in film performance before and after the tests," said Claudio Truzzi, Alchimer’s chief technology officer. "Alchimer’s films have been vetted by multiple third parties and have been validated as conforming with several industry-standard, package-level reliability tests."

RTI International provides research and technical expertise to governments and businesses in more than 40 countries in the areas of health and pharmaceuticals, education and training, surveys and statistics, advanced technology, international development, economic and social policy, energy and the environment, and laboratory and chemistry services.

Alchimer develops and markets chemical formulations, processes and IP for the deposition of nanometric films used in a variety of microelectronic and MEMS applications, including wafer-level interconnects and TSVs (through-silicon vias) for 3D packaging. Visit www.alchimer.com for more information.

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(November 26, 2010) — Di Ma, VP, field technical support at TSMC, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) on technical challenges in 28nm CMOS and beyond. TSMC is trying to determine when to deploy FinFETs; and high-mobility channels (using Ge) are also being investigated.

Listen to Di Ma’s talk: Download or Play Now

Di Ma spoke with Debra Vogler, senior technical editor, ElectroIQ, at the symposium, about silicon interposers, die stacking with through-silicon vias (TSV), and gate-last transistor fab.

Click to Enlarge

Figure. Packaging and 3D IC trend. SOURCE: TSMC

Ma commented on TSMC’s work with Xilinx on silicon interposers. Going forward, it’s a matter of how large the interposer will be, i.e., whether or not to build different passive devices in the interposer to improve signal integrity, as well as die stacking using TSVs, said Ma (Figure). 

Read about Ma’s gate-last points here.

(November 24, 2010) — CEA-Leti will present 10 papers, including two invited papers, at the IEDM/IEEE 2010 International Electron Devices Meeting December 6-8, in San Francisco, CA. The papers will cover More than Moore, FDSOI, memory (phase-change and charge-trapping), silicon nanowires, TSVs, high-k dielectrics, and more.

IEDM Previews:
 
U. of Tokyo first to demo III-V self-aligned source/drain
IBM, Macronix identify phase-change memory failure mode
Record photodiode quantum efficiency from Taiwan lab
How strain can protect devices from ESD
SEMATECH tipping III-V MOSFET, FinFET, and resistive RAM
TSMC anneal for gate-last HKMG process
Imec IEDM presentations to cover More than Moore, ITRS
When do TSV stresses affect device operation?
Multi-threshold-voltage flexibility in FDSOI
CMOS imager works from light to night
Carbon nanotube vias approach production densities
IBM Alliance simplifies pFET HKMG
IM Flash details 25nm NAND

The two invited papers include an overview on FDSOI (the alternative to bulk technologies for 20nm nodes and below) and an overview of new-generation substrates enabling future devices in the More Moore and More Than Moore topics. A paper on the latest results in the integration of the metallic dual gate on FDSOI technology, with UTBOX, clearly positions Leti on the sub-16nm CMOS technologies. Leti will present two papers on memory, including one on the impact of N-doping in GeTe to boost the data-retention performances of phase-change memory (PCM), and an in-depth study on the role of defects in the Al2O3 blocking layer for charge-trapped memories.

Leti also will present findings of a futuristic study on the mobility of carriers in 10nm silicon nanowires for tomorrow’s CMOS (end of ITRS roadmap), and the latest results of its 3D through-silicon-via integration.

Two additional papers include results from Leti’s work on the reliability of oxide gate based on high-k dielectrics doped with Lanthanum, and CMOS ICs on SiGe on insulator and silicon constrain (co-integration into CMOS SRAM cell on FDSOI). 

CEA is a French research and technology public organization, with activities in four main areas: energy, information technologies, healthcare technologies and defence and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro and nanotechnologies and their applications, from wireless devices and systems, to biology and healthcare or photonics. Nanoelectronics and microsystems (MEMS) are at the core of its activities. For more information about Leti, please visit www.leti.fr.  

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(November 17, 2010) — In his keynote address at the MEPTEC Semiconductor Packaging Roadmaps conference (9/10/10, Santa Clara, CA), Bill Bottoms, chairman of Third Millennium Test Solutions (3MTS), gave attendees a dose of reality as he summarized the predicament facing the industry as it pursues 3D ICs.

"Everything becomes more difficult at deep sub-micron," said Bottoms. "Deep sub-micron implies changes in every parameter and makes package functions of device protection, power delivery, and signaling into and out of the device more challenging." A few of the challenges facing the industry as it implements 3D ICs will be: 1) the need to control power and enhance performance, 2) dealing with transistors that wear out within an expected product’s lifetime, 3) the introduction of new sources of stress, 4) thermal density increases, 5) operating voltage decreases, etc.

Listen to Bill Bottom’s interview: Download (iPhone/iPod) or Play Now

In an interview with Debra Vogler, senior technical editor, Bottoms details some of the methods that will be needed to address the 3D IC conundrum (e.g., redundancy, continuous testing, dynamic self-repair, graceful degradation). He also takes listeners on a kind of "back to the future" discussion as many of the solutions that will be needed for 3D ICs, he observes, were used years ago in mainframe computers 20-30 years ago. "It’s not an issue of invention, but one of integration with what is already known," said Bottoms.

Another challenge with die stacking is the need to establish known-good die (KGD). The testing challenges will be tremendous. For example, Bottoms told attendees that no test equipment will handle the number of vectors (which can be close to a trillion) at a reasonable cost and no one has a probe solution for 17GHz.

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(November 15, 2010) — In his presentation at the MEPTEC Semiconductor Packaging Roadmaps conference (Santa Clara, CA; 11/10/10), Lee Smith, VP, business development at Amkor, made a case for full supply chain collaboration as the industry moves to 3D ICs with TSVs. Among the drivers for collaboration in 3D packaging development are the rising R&D costs and capital intensity, shorter product and technology life cycles and the attendant margin "squeeze" along with the consolidation of demand to achieve ROI requirements.

One collaboration integrated design manufacturer (IDM)/outsourced semiconductor assembly and test (OSAT) provider case study is Amkor’s work with TI; in July 2010, the companies announced qualification and high-volume manufacturing of fine pitch copper pillar technology. Smith said that the new lead-free technology enables bump pitches of ≤50µm and is cost competitive with wire bonding. 

Listen to Lee Smith’s interview: Download or Play Now

In this podcast interview, Smith discusses the three generations in the transition to 3D packaging and how the OSATs shape the development roadmap. In the first generation of die stacking, it was the memory industry and their OSAT suppliers who collaborated; then logic plus memory integration led to further collaboration. In the second generation (package stacking), OEMs were the key drivers in initiating collaboration: the logic, memory, OSATs, plus EMS industry, all enabled package stack solution in high-volumes. And as the industry enters the third stage of 3D packaging — a complete 3D architecture with TSVs — Smith says that we need complete supply chain collaboration: EDA tool suppliers, equipment/materials suppliers, logic, memory, fabless, IDMs, and the SATs, to develop and deploy the technologies.

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by Dr Phil Garrou, contributing editor

November 11, 2010 – Under the leadership of newly inaugurated president Rajen Chanchani of Sandia National Labs (see sidebar below) and president-elect Voya Markovich of Endicott Interconnect, the International Microelectronics & Packaging Society (IMAPS) held its 43rd annual meeting last week in Raleigh, NC. Industry veteran Dave Seeger of IBM served as general chair and local Lord Corp. chemist Sara Paisner served as technical chair for the meeting.

In an invited plenary lecture, Cree co-founder John Edmond made the strong case for the imminent proliferation of LED lighting. Another invitee, Rao Tummala, professor and director of the Georgia Tech Packaging Research Consortium (PRC), made the case for moving to glass and silicon 600mm panel production to lower the cost for 3D interposers for mechanically sensitive 32nm and below IC and 3D interposers.

Dave Miller, president of DuPont’s electronics & communications division, focused his invited talk on the use of DuPont’s thick film materials for solar panel fabrication and made an argument for grid parity being within reach. Another invitee, Leo Linehan, global business director of advanced packaging technologies for Dow Chemical’s advanced electronic materials division, commented that materials companies need to look for "common demands and requirements" for new product development expenses to make sense. He discussed two new Dow products: a new low viscosity, high-speed capillary underfill (CUF) which uses <3μm filler and a new aqueous developable low-k dielectric (k = 2.85). Regarding 3D IC technology, Linehan thinks that "soon everyone will be using it," but since much of the driving force is low latency high-bandwidth memory access, ultimately 3D through-silicon vias (TSV) "will be paid for by the DRAM manufacturers."

The global microelectronic conference trend of focus on 3D ICs certainly continued at IMAPS, with 4 technical sessions and a panel session.

In the session "3D Interconnect Technologies in Research Triangle Park," practitioners from the region (Microelectronic Consultants of NC, RTI International, Ziptronix, and NC State U.) detailed their latest 3D-related work. Paul Enquist, CTO of Ziptronix, sees their direct bond oxide technology catching on with fabricators of backside illuminated CMOS image sensors. He also shared the first released cross-sections (below) of a 10μm pitch, 463,000 connection daisy-chain built with the Ziptronix DBI process with Cu filled TSV fully protected by barrier layers, and he reported a 99.999% yield on such structures.

John Lannon, engineer at RTI, warned of electrical failures on 3D test vehicles bonded with Cu/Sn/Cu intermetallics: "The yield goes to zero after 96 hours standard autoclave testing," he asserted. Standard epoxy underfills do not seem to solve the problem, but he pointed to a silicon underfill that allows device survival through the autoclave testing. More work is needed, he noted, to completely understand this issue and all potential solutions.

Rhett Davis, Professor of EE at NC State, showed 3D specific designs which achieved 65% power reduction and an 800% increase in memory bandwidth.

3D veteran Rozalia Beica of Applied Materials’ Semitool division updated the audience on the company’s 3D work, and the activities of the global EMC3D consortium (Applied is a member). A 3D line at Applied’s Maydan Technology Center has run >50 integrated demos, he said, and the company’s newer via fill processes show a 50% reduction in overburden and significantly purer copper, which results in significantly less Cu extrusion (Cu pumping) and micro voiding.

A 3D panel session headed up by RPI Professor James Lu addressed the 3D commercial timeline. Phil Garrou from Microelectronic Consultants of NC — yours truly — commented that roadmaps of many companies (TSMC, UMC, Elpida, ASE, etc.) now appeared in sync and all point toward commercialization in the 2011-2012 timeframe. Urmi Ray, senior staff engineer from Qualcomm, commented that his company, a very public supporter of 3D IC technology, sees "two years out (2012)" as "about right". Klaus Hummler, senior principal engineer from SEMATECH, was a little more hesitant about timing, indicating that Nokia is pointing toward product introduction in 2013, "but we believe this will be a stretch."

When asked about standards, Qualcomm’s Ray, herself involved in several standards initiatives, pleaded for more work on standards "now." And for fabless companies, such standards a "matter of survival," Hummler added.

Chanchani takes the helm at IMAPS US

At last weeks 43rd IMAPS annual meeting, Dr. Rajen Chanchani of Sandia National Labs took over as president of IMAPS.

Founded in 1967 as ISHM (International Society for Hybrid Microelectronics), the society merged with the International Electronic and Packaging Society (IEPS) in 1996 to become IMAPS. Now with 23 North American chapters and 21 international chapters, IMAPS hosts a variety of technical workshops, conferences, and professional development courses throughout the year, and its IMAPS Foundation provides annual grants to students involved in electronic packaging disciplines.

Chanchani has worked in many leading-edge technology areas, but his most influential work, many believe, was on the Sandia "mini-BGA" — widely acknowledged as the first wafer-level package. He received his PhD from the U. of Florida, and worked at AVX and AT&T Bell Labs prior to joining Sandia in 1990. He was made an IMAPS Fellow in 2004.

IMAPS new president Rajen Chanchani (center) receives congratulations from past president Howard Imhof (left) and IMAPS executive director Michael O’Donoghue.

 

Dr. Phil Garrou is a contributing editor for Solid State Technology and Advanced Packaging on www.ElectroIQ.com. Read his blog, Insights from the Leading Edge.