Category Archives: Applications

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that, for the fourth successive year, it has earned all three awards resulting from VLSIresearch Inc.’s annual Customer Satisfaction Survey. For 2016, EVG was ranked as one of the 10 BEST Focused Chip Making Equipment Suppliers, having steadily increased its overall ratings since 2013. EVG was also cited as one of THE BEST Suppliers of Fab Equipment and received a RANKED 1st award in Specialty Fab Equipment.

According to VLSIresearch, EVG excelled in the supplier performance categories, which include trust in supplier, technical leadership, recommended supplier, partnering and commitment. Moreover, EVG scored well across the board, increasing its scores in eight of the 15 total categories. The milestones in this year’s rankings continue: 2016 is the 14th consecutive year that EVG has been listed among “THE BEST” suppliers, and the fourth year in which EVG was the highest ranked supplier of wafer bonding equipment.

“EVG continues to rank highly and grow its position on our annual survey, thanks to its strong, global customer-focused strategy,” noted G. Dan Hutcheson, VLSIresearch CEO and chairman. “The company’s approach integrates an emphasis on high-volume manufacturing with its long-running commitment to technology invention, innovation and implementation. The results of our annual survey exemplify EVG’s continued success in delivering leading wafer bonding and lithography solutions.”

Hermann Waltl, executive sales and customer support director at EV Group, stated, “Ensuring our customers’ success is paramount to EVG’s business. Receiving recognition from our customers with these three coveted awards for the fourth year in a row is a true honor, and we thank them for their participation in VLSIresarch’s annual customer satisfaction survey. We look forward to continuing not only to meet but to exceed their requirements through a comprehensive approach of providing leading-edge technology, extensive process technology teams and world-class development and production services around the globe.”

Nowadays, our world is in search of cleaner energy sources to power our increasing industrial and economical needs. Solar energy is becoming an alternative source to fossil fuels, however, due to the accelerating pace at which we are consuming energy, we need to develop ubiquitous PV technologies that can be employed everywhere: on buildings, clothes, consumer electronics and wearables. This necessitates ultra-thin film, low-cost and ideally flexible solar cells without compromising the environment during production, use, or disposal.

Most of us know that the most common inorganic solar cells, displayed over roof tops and in solar farms, are made of silicon. However, the production of silicon solar cells can be expensive and energy demanding and the final modules are heavy and bulky. Many lower-cost thin film solar cells, alternative to silicon, are composed of toxic elements such as lead or cadmium, or contain scarce elements such as indium or tellurium.

Now ICFO researchers Dr. Maria Bernechea, Dr. Nicky Miller, Guillem Xercavins, David So, and Dr. Alexandros Stavrinadis, led by ICREA Prof. at ICFO Gerasimos Konstantatos have found a solution to this increasing problem. They have fabricated a solution-processed, semi-transparent solar cell based on AgBiS2 nanocrystals, a material that consists of non-toxic, earth-abundant elements, produced in ambient conditions at low temperatures. These crystals have shown to be very strong panchromatic absorbers of light and have been further engineered to act as effective charge-transporting medium for solution-processed solar cells.

This image shows a semi-transparent solar cell based on AgBiS2 nanocrystal. Credit: ICFO

This image shows a semi-transparent solar cell based on AgBiS2 nanocrystal. Credit: ICFO

What is special about these cells? As researcher Dr. Maria Bernechea comments, “They contain AgBiS2 nanocrystals, a novel material based on non-toxic elements. The chemical synthesis of the nanocrystals allows exquisite control of their properties through engineering at the nanoscale and enables their dissolution in colloidal solutions. The material is synthesized at very low temperatures (100ºC), an order of magnitude lower than the ones required for silicon based solar cells.´´

The team of researchers at ICFO developed these cells through a low temperature hot-injection synthetic procedure. They first dispersed the nanocrystals into organic solvents, where the solutions showed to be stable for months without any losses in the device performance. Then, the nanocrystals were deposited onto a thin film of ZnO and ITO, the most commonly used transparent conductive oxide, through a layer-by-layer deposition process until a thickness of approximately 35nm was achieved.

“A very interesting feature of AgBiS2 solar cells is that they can be made in air at low temperatures using low-cost solution processing techniques without the need for the sophisticated and expensive equipment required to fabricate many other solar cells. These features give AgBiS2 solar cells significant potential as a low-cost alternative to traditional solar cells.” as Dr. Nicky Miller states.

These cells, in this first report, have already achieved power conversion efficiencies of 6.3%, which is on par with the early reported efficiencies of currently high performance thin film PV technologies. This highlights the potential of AgBiS2 as a solar-cell material that in the near future can compete with current thin film technologies that rely on vacuum-based, high-temperature manufacturing processes.

As ICREA Prof at ICFO Gerasimos Konstantatos concludes, “This is the first efficient inorganic nanocrystal solid-state solar cell material that simultaneously meets demands for non-toxicity, abundance and low-temperature solution processing. These first results are very encouraging, yet this is still the beginning and we are currently working on our next milestone towards efficiencies > 12%”.

The results obtained from this study, which was financially supported by European Commission within the NANOMATCELL project, signifies a turning point in the concept and production of solar cells, moving from silicon cells to low-cost environmentally friendly solar cells that will definitely imply a safer and more sustainable world for the future.

Leading companies within critical industry segments answer questions about the state of technology preparedness for the Internet-of-Things.

BY ED KORCZYNSKI, Senior Technical Editor

The Internet-of-Things (IoT) is expected to add new sensing and communications to improve the functionality of all manner of things in the world: bridges sensing and reporting when repairs are needed, parts automatically informing where they are in storage and transport, human health monitoring, etc. Solid-state and semiconducting materials for new integrated circuits (IC) intended for ubiquitous IoT appli- cations will have to be assembled at low-cost and small- size in High Volume Manufacturing (HVM). Micro-Electro- Mechanical Systems (MEMS) and other sensors are being combined with Radio-Frequency (RF) ICs in miniaturized packages for the first wave of growth in major sub-markets.

To meet the anticipated needs of the different IoT application spaces, we asked leading companies within critical industry segments about the state of technology preparedness:

  • Commercial IC HVM – GLOBALFOUNDRIES,
  • Electronic Design Automation (EDA) – Cadence and Mentor Graphics,
  • IC and complex system test – Presto Engineering.

Korczynski: Today, ICs for IoT applications typically use 45nm/65nm-node which are “Node -3” (N-3) compared to sub-20nm-node chips in HVM. Five years from now, when the bleeding-edge will use 10nm node technology, will IoT chips still use N-3 of 28nm-node (considered a “long-lived node”) or will 45nm-node remain the likely sweet-spot of price:performance?

Timothy Dry, product marketing manager, GLOBALFOUNDRIES
In five years’ time, there will be a spread of technology solutions addressing low, middle, and high ends of IoT applications. At the low end, IoT end nodes for applica- tions like connected smoke detectors, security sensors will be at 55, 40nm ULP and ULL for lowest system power, and low cost. These applications will be typically served by MCUs

In the mid-range, applications like smart-meters and fitness/medical monitoring will need systems that have more processing power

High-end products like smart-watches, learning thermo- stats, home security/monitoring cameras, and drones will require MPU-class IC products (~2000DMIPs) and run high-order operating systems (e.g. Linux, Android). These products will be made in leading-edge nodes starting at 22FDX, 14FF and migrating to 7FF and beyond. Design for lowest dynamic power for longest battery life will be the key driver, and these products typically require human machine Interface (HMI) with animated graphics on a high resolution displays. Connectivity will include BLE, WiFi and cellular with strong security.

Steve Carlson, product management group director, Cadence
We have seen recent announcements of IoT targeted devices at 14nm. The value created by Moore’s Law integration should hold, and with that, there will be inherent advan- tages to those who leverage next generation process nodes. Still, other product categories may reach functionality saturation points where there is simply no more value obtained by adding more capability. We anticipate that there will be more “live” process nodes than ever in history.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering
It is fair to say that most IoT devices will be a heterogeneous aggregation of analog functions rather than high power digital processors. Therefore, and by similarity with Bluetooth and RFID devices, 90nm and 65nm will remain the mainstream nodes for many sub-vertical markets, enabling the integration of RF and analog front-end functions with digital gate density. By default, sensors will stay out of the monolithic path for both design and cost reasons. The best answer would be that the IoT ASIC will follow eventually the same scaling as the MCU products, with embedded non-volatile memories, which today is 55-40nm centric and will move to 28nm with industry maturity and volumes.

Korczynski: If most IoT devices will include some manner of sensor which must be integrated with CMOS logic and memory, then do we need new capabilities in EDA-flows and burn-in/ test protocols to ensure meeting time-to-market goals?

Nicolas Williams, product marketing manager, Mentor Graphics

If we define a typical IoT device as a product that contains a MEMS sensor, A/D, digital processing, and a RF-connection to the internet, we can see that the funda- mental challenge of IoT design is that teams working on this product need to master the analog, digital, MEMS, and RF domains. Often, these four domains require different experience and knowledge and sometimes design in these domains is accomplished by separate teams. IoT design requires that all four domains are designed and work together, especially if they are going on the same die. Even if the components are targeting separate dice that will be bonded together, they still need to work together during the layout and verification process. Therefore, a unified design flow is required.

Stephen Pateras, product marketing director, Mentor Graphics
Being able to quickly debug and create test patterns for various embedded sensor IP can be addressed with the adoption of the new IEEE 1687 IP plug-and-play standard. If a sensor IP block’s digital interface adheres to the standard, then any vendor-provided data required to initialize or operate the embedded sensor can be easily and quickly mapped to chip pins. Data sequences for multiple sensor IP blocks can also be merged to create optimized sequences that will minimize debug and test times.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering
From a testing standpoint, widely used ATEs are generally focused on a few purposes, but don’t necessarily cover all elements in a system. We think that IoT devices are likely to require complex testing flows using multiple ATEs to assure adequate coverage. This is likely to prevail for some time as short run volumes characteristic of IoT demands are unlikely to drive ATE suppliers to invest R&D dollars in creating new purpose-built machines.

Korczynski: For the EDA of IoT devices, can all sensors be modeled as analog inputs within established flows or do we need new modeling capability at the circuit level?

Steve Carlson, product management group director, Cadence
Typically, the interface to the physical world has been partitioned at the electrical boundary. But as more mechanical and electro-mechanical sensors are more deeply integrated, there has been growing value in co-design, co-analysis, and co-optimization. We should see more multi-domain analysis over time.

Nicolas Williams, product marketing manager, Mentor Graphics
Designers of IoT devices that contain MEMS sensors need quality models in order to simulate their behavior under physical conditions such as motion and temperature. Unlike CMOS IC design, there are few standardized MEMS models for system-level simulation. State of the art MEMS modeling requires automatic generation of behav- ioral models based on the results of Finite Element Analysis (FEA) using reduced-order modeling (ROM). ROM is a numerical methodology that reduces the analysis results to create Verilog-A models for use in AMS simulations for co-simulation of the MEMS device in the context of the IoT system.

Korczynski: For test of IoT devices which may use ultra-low threshold voltage transistors, what changes are needed compared to logic test of a typical “low-power” chip?

Steve Carlson, product management group director, Cadence
Susceptibility to process corners and operating conditions becomes heightened at near-threshold voltage levels. This translates into either more conservative design sign-off criteria, or the need for higher levels of manufacturing screening/tests. Either way, it has an impact on cost, be it hidden by over-design, or overtly through more costly qualification and test processes.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering
We need to make sure that the testability has also been designed to be functional structurally in this mode. In addition, sub-threshold voltage operation must account for non-linear transistor characteristics and the strong impact of local process variation, for which the conventional testability arsenal is still very poor. Automotive screening used low voltage operation (VLV) to detect latent defects, but at very low voltage close to the transistor threshold, digital becomes analog, and therefore if the usual concept still works for defect detection, functional test and @speed tests require additional expertise to be both meaningful and efficient from a test coverage perspective.

Korczynski: Do we have sufficient specifications within “5G” to handle IoT device interoperability for all market segments?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES
The estimated timeline for standardization availability of 5G is around 2020. 5G is being designed keeping three classes of applications in mind: Enhanced Mobile Broadband, Massive IoT, and Mission-Critical Control. Specifically for IoT, the focus is on efficient, low-cost communication with deep coverage. We will start to see early 5G technologies start to appear around 2018, and device connectivity, interoperability and marshaling the data they generate that can apply to multiple IoT sub-segments and markets is still very much in development.

Korczynski: Will the 1st-generation of IoT devices likely include wide varieties of solution for different market-segments such as industrial vs. retail vs. consumer, or will most device use similar form-factors and underlying technologies?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES
If we use CES 2016 as a showcase, we are seeing IoT “Things” that are becoming use-case or application-centric as they apply to specific sub-segments such as Connected Home, Automotive, Medical, Security, etc. There is definitely more variety on the consumer front vs. industrial. Vendors / OEMs / System houses are differentiating at the user- interface design and form-factor levels while the “under- the-hood” IC capabilities and component technologies that provide the atomic intelligence are fairly common.

Steve Carlson, product management group director, Cadence
Right now it seems like everyone is swinging for the fence. Everyone wants the home-run product that will reach a billion devices sold. Generality generally leads to sub-optimality, so a single device usually fails to meet the needs and expectations of many. Devices that are optimized for more specific use cases and elements of purchasing criteria will win out. The question of interface is an interesting one.

Korczynski: Will there be different product life-cycles for different IoT market-segments, such as 1-3 years for consumer but 5-10 years for industrial?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES
That certainly seems to be the case. According to Gartner’s market analysis for IoT, Consumer is expected to grow at a faster pace in terms of units compared to Enterprise, while Enterprise is expected to lead in revenue. Also the churn-cycle in Consumer is higher / faster compared to Enterprise. Today’s wearables or smart-phones are good reference examples. This will however vary by the type of “Thing” and sub-segment. For example, you expect to have your smart refrigerator for a longer time period compared to smart clothing or eyewear. As ASPs of the
“Things” come down over time and new classes of products such as disposables hit the market, we can expect even larger volumes.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering
The market segments continue to be driven by the same use cases. In consumer wearables, short cycles are linked to fashion trends and rapid obsolescence, where consumer home use has longer cycles closer to industrial market requirements. We believe that the lifecycle norms will hold true for IoT devices.

Korczynski: For the IoT application of infrastructure monitoring (e.g. bridges, pipelines, etc.) long-term (10-20 year) reliability will be essential, while consumer applications may be best served by 3-5 year reliability devices which cost less; how well can we quantify the trade-off between cost and chip reliability?

Steve Carlson, product management group director, Cadence
Conceptually we know very well how to make devices more reliable. We can lower current densities with bigger wires, wecanrunatcoolertemperatures,andsoon. Thedifficulty is always in finding optimality for a given criterion across the, for practical purposes, infinite tradeoffs to be made.

Korczynski: Why is the talk of IoT not just another “Dot Com” hype cycle?

Rajeev Rajan, Vice President of Internet of Things (IoT) at GLOBALFOUNDRIES
I participated in a panel at SEMICON China in Shanghai last month that discussed a similar question. If we think of IoT as a “brand new thing” (no pun intended), then we can think of it as hype. However if we look at the IoT as as set of use-cases that can take advantage of an evolution of Machine-to-Machine (M2M) going towards broader connectivity, huge amounts of data generated and exchanged, and a generational increase in internet and communication network bandwidths (i.e. 5G), then it seems a more down-to-earth technological progression.

Nicolas Williams, product marketing manager, Mentor Graphics
Unlike the Dot Com hype, which was built upon hope and dreams of future solutions that may or may not have been based in reality, IoT is real business. For example, in a 2016 IC Insights report, we see that last year $63.4 billion in revenue was generated for IoT systems and the market is growing at about 20% CAGR. This same report also shows IoT semiconductor sales of over $15 billion in 2015 with a CAGR of 21.1%.

Jon Lanson, vice president worldwide sales & marketing, Presto Engineering
It is the investment needed up front to create sensing agents and an infrastructure for the hardware foundation of the IoT that will lead to big data and ultimately value creation.

Steve Carlson, product management group director, Cadence
There will be plenty of hype cycles for products and product categories along the way. However, the foundational shift of the connection of things is a diode through which civili- zation will only pass through in one direction.

In collaboration with the National Institute of Information and Communications Technology (NICT), Associate Professor Hiroyuki Ito and Professor Kazuya Masu, et al., of the Tokyo Institute of Technology, developed a new algorithm and circuit technology allowing high-frequency piezoelectric resonators to be used for phase locked loops (PLL). It was confirmed that these operate with low noise and have an excellent Figure of Merit (FoM) compared to conventional PLLs.

This technology allows high-frequency piezoelectric resonators to be used in place of crystal oscillators which was a problem for realizing compact and low-cost radio modules. This greatly contributes to the creation of compact, low-cost, high-speed radio communication systems for the IoT age. High-frequency piezoelectric resonators are compact, can be integrated, have an excellent Q value, and oscillators that use these have excellent jitter performance. High-frequency piezoelectric resonators had greater issues with resonance frequency variance and temperature dependability compared to crystal resonators. However, these issues were resolved by the development of a PLL that uses a channel adjustment technique, which is a new algorithm.

A prototype was fabricated by a silicon CMOS process with a minimum line width of 65 nm, and a maximum frequency output of approximately 9 GHz was achieved with a phase fluctuation of only 180 femtoseconds. Power consumption was 12.7 mW. This performance is equivalent to a PLL Figure of Merit (FoM) of -244 dB, and it has the world’s top-class performance as a fractional-N PLL. This can contribute to the realization of compact, low-cost, high-speed radio communication systems.

The study results will be announced in local time June 17 in “The 2016 Symposium on VLSI Circuits” to be held in Hawaii from June 14.

ams acquires CCMOSS


June 16, 2016

ams, a manufacturer of high performance sensor and analog solutions, has signed an agreement to acquire 100% of the shares in Cambridge CMOS Sensors Ltd (CCMOSS), a developer of micro hotplate structures for gas sensing and infrared applications, in an all-cash transaction.

CCMOSS’ micro hotplates are MEMS structures that are used in gas sensors for volume applications in the automotive, industrial, medical, and consumer markets. The company’s deep expertise in this area is highly synergetic with ams’ technology leadership in MOX gas sensing materials to detect gases like CO, NOx, and VOCs. CCMOSS’ manufactures these MEMS structures on CMOS wafers allowing the creation of complete monolithically integrated CMOS sensor ICs. This makes CCMOSS’ solutions highly cost-efficient, besides offering other significant advantages over competing technologies like low power consumption, small footprint and the ability to integrate additional sensor modalities like relative humidity, temperature, and pressure.

In addition, CCMOSS commands a portfolio of IR technology comprising high performance IR radiation sources and detectors for sensor applications. Highly complementary to ams’ spectral sensing strategy for next generation optical sensor technologies, CCMOSS’ IR sensing is based on the same monolithic CMOS structures as for gas sensing, enabling miniaturized implementations and efficient integration with other on-chip functions. Applications include CO2 gas sensing and human presence detection and will extend into spectroscopic identification of organic materials.

Founded in 2008 as a spin-off from Cambridge University, with the start of technology development dating back to 1994 in collaboration with the University of Warwick, CCMOSS has built an outstanding expertise in micro hotplate design and manufacturing for gas and infrared sensing over more than 20 years. CCMOSS’ corporate headquarters are located in Cambridge, UK, and the company has 33 employees. The Cambridge region has become a center of innovation for sensor technologies globally so ams values the ability to gain direct access to this attractive ecosystem going forward. CCMOSS currently has product revenues on a small scale but is not yet profitable.

The parties to the transaction, which is expected to close within a week given that no regulatory approvals are needed, have agreed to keep the consideration confidential. ams plans to fully integrate CCMOSS’ activities into its existing environmental sensor business, which has development locations in Eindhoven, the Netherlands, and Reutlingen, Germany.

Alexander Everke, CEO of ams, commented on the transaction, “The addition of CCMOSS makes ams the clear leader in gas and infrared sensor technology worldwide, and completes ams’ portfolio of products and technologies for the environmental sensor market. This highly strategic acquisition is therefore another key step in making ams the world’s leading provider of sensor solutions for consumer, automotive, industrial, and medical applications.”

Researchers at the Texas Analog Center of Excellence(TxACE), a Semiconductor Research Corporation(SRC)-funded research effort centered at the University of Texas at Dallas (UT Dallas), are working to develop an affordable electronic nose that can be used in breath analysis for a wide range of health diagnosis.

While devices that can conduct breath analysis using compound semiconductors currently exist, they are bulky and too costly for commercial use, said Dr. Kenneth O, one of the principle investigators of the effort and director of TxACE. The UT Dallas researchers and collaborators at the Ohio State University and Wright State University determined that using CMOS integrated circuits technology will make the electronic nose affordable. CMOS is the integrated circuits technology that is used to manufacture the bulk of electronics that have made possible the smartphones, tablets and other electronic devices used in daily life.

Their research on the CMOS electronic nose was presented today in a paper entitled 200-280GHz CMOS Transmitter for Rotational Spectroscopy and Demonstration in Gas Spectroscopy and Breath Analysis, at the 2016 IEEE Symposia on VLSI Technology and Circuits in Hawaii.

“Smell is one of the senses of humans and animals, and there have been many efforts to build an electronic nose,” said Dr. Navneet Sharma, the lead author of paper. “We have demonstrated that you can build an affordable electronic nose that can sense many different kinds of smells. When you’re smelling something, you are detecting chemical molecules in the air. Similarly, an electronic nose detects chemical compounds using rotational spectroscopy.”

The rotational spectrometer generates and transmits electromagnetic waves over a wide range of frequencies and analyzes how the strength of waves are attenuated to determine what chemicals are present as well as their concentrations in a sample. The system can detect low levels of chemicals present in human breath.

“Think about where breath comes from,” said Professor Philip Raskin, M.D., of University of Texas, Southwestern. “Parts come from gases in your stomach, so this involves the digestive system. Molecules in breath also come from the blood when it comes into contact with the air in the lungs. The breath test is really a blood test without taking blood samples. Breath contains information about practically every part of your body.”

“This is the really opportune moment for the development of these breath sensors, rooted in enabling confluence of semiconductor innovation and system designs rooted in molecular spectroscopy,” said Professor Ivan Medvedev of Wright State University, another member of team. “The device can detect gas molecules with far more specificity and sensitivity than currently used breathalyzers, which can confuse acetone for ethanol in the breath. The distinction is important, for example, for patients with Type 1 diabetes who have high concentrations of acetone in their breath.”

“If you think about the industry around sensors that emulate our senses, it’s huge,” O said. “Imaging applications, hearing devices, touch sensors — what we are talking about here is developing a device that imitates another one of our sensing modalities and making it affordable and widely available. The possible use of the electronic nose is almost limitless. Think about how we use smell in our daily lives.”

The researchers envision the CMOS-based device will first be used in industrial settings and then in doctors’ offices and hospitals. As the technology matures, they could become household devices. The need for blood work and gastrointestinal tests could be reduced, and diseases could be detected earlier — lowering the costs of health care.

The researchers are working toward construction of a prototype programmable electronic nose that can be made available for beta testing sometime in early 2018.

The Texas Analog Research Center and this work are supported in large part by SRC and Texas Instruments. Additional support was provided by Samsung Global Research Outreach.

“SRC and its members, including Texas Instruments, Intel, IBM, Freescale, Mentor Graphics, ARM and GLOBALFOUNDRIES, have been following this work for several years,” said Dr. David Yeh, SRC senior director. “We are excited by the possibilities of the new technology and are working to rapidly explore its uses and applications. It is a significant milestone, but there is still much more research needed for this to reach its potential.”

TxACE, created in 2008 under the umbrella of the SRC, is the largest analog circuit design research center based in an academic institution. The center focuses on analog and mixed signal integrated circuits engineering that improve public safety and security, enhance medical care and help the U.S. become more energy independent.

The research team includes UT Dallas doctoral students Navneet Sharma, Zhong Qian and Jing Zhang; Dr. Mark Lee, professor and head of physics; Dr. David Lary, associate professor of physics; Dr. Hyunjoo Nam, assistant professor of bioengineering, Dr. Rashaunda Henderson, associate professor of electrical engineering; and Dr. Wooyeol Choi, assistant research professor. Other team members include Prof. Philip Raskin, M.D. of UT Southwestern, Professor Frank C. De Lucia, C. F. Neese, and J. P. McMillan of Ohio State University, and Professor Ivan R. Medvedev and R. Schueler of Wright State University.

Leti, an institute of CEA Tech, is hosting a one-day conference covering “System Reliability & Security in a Connected World” in Lyon, France, on June 23.

Held at the Lyon Congress Center, this Leti Innovation Day event will explore novel, effective ways to ensure security in the emerging new phase of the digital revolution launched by the Internet of Things.

According to Alain Merle, Leti’s strategic marketing manager for security, this rapidly changing digital environment requires new paradigms for reliability, privacy and security in order to ensure a safe ecosystem for both industrials and consumers.  Hacking, data and identity theft, all digital threats to the real world, immediately follow the introduction or expansion of new applications of digital technology. The frontier between physical and digital security has vanished, he said.

“Companies must start implementing IoT security solutions at the start of the production cycle, and every new industrial project should be ruled not only by cost control, performance enhancement and energy savings, but also by security control,” added Lionel Rudant, Leti’s strategic marketing manager for IoT.

Presenters include Leti experts and industry leaders whose companies are collaborating with Leti on new security and reliability solutions for the next phase of the digital revolution. The lineup includes executives from Bureau Veritas, GLOBALFOUNDRIES, Intel, Mentor Graphics, Oberthur Technologies, Safran and STMicroelectronics, who will share their insights on topics such as enabling a connected world, assessing security and reliability, anticipating security challenges and how advanced technologies can strengthen security.

Leti is a world leader in security evaluations through advanced technology, applications and medical platforms prototyping new digital services and driving innovative requirements for integrated system architectures.

Visit Leti Innovation Day for the complete program, list of speakers and registration information.

By Paula Doe, SEMI

The changing market for ICs means the end of business as usual for the greater semiconductor supply chain. Smarter use of data analytics looks like a key strategy to get new products more quickly into high yield production at improved margins.

Emerging IoT market drives change in manufacturing

The emerging IoT market for pervasive intelligence everywhere may be a volume driver for the industry, but it will also put tremendous pressure on prices that drive change in manufacturing. Pressure to keep ASPs of multichip connected devices below $1 to $5 for many IoT low-to-mid end applications, will drive more integration of the value chain, and more varied elements on the die. “The value chain must evolve to be more effective and efficient to meet the price and cost pressures for such IoT products and applications,” suggests Rajeev Rajan, VP of IoT, GLOBALFOUNDRIES, who will speak on the issue in a day-long forum on the future of smart manufacturing in the semiconductor supply chain at SEMICON West 2016 on July 14.

“It also means tighter and more complete integration of features on the die that enable differentiating capabilities at the semiconductor level, and also fewer, smaller devices that reduce the overall Bill of Materials (BOM), and result in more die per wafer.” He notes that at 22nm GLOBALFOUNDRIES is looking to enable an integrated connectivity solution instead of a separate die or external chip. Additional requirements for IoT are considerations for integrating security at the lower semiconductor/hardware layers, along with the typical higher layer middleware and software layers.

This drive for integration will also mean demand for new advanced packaging solutions that deliver smaller, thinner, and simpler form factors. The cost pressure also means than the next nodes will have to offer tangible power/performance/area/cost (PPAC) value, without being too disruptive a transition from the current reference flow. “Getting to volume yields faster will involve getting yield numbers earlier in the process, with increasing proof-points and planning iterations up front with customers, at times tied to specific use-cases and IoT market sub-segments,” he notes.

Rapid development of affordable data tools from other industries may help

Luckily, the wide deployment of affordable sensors and data analysis tools in other industries in other industries is developing solutions that may help the IC sector as well.  “A key trend is the “democratization” – enabling users to do very meaningful learning on data, using statistical techniques, without requiring a Ph.D. in statistics or mathematics,” notes Bill Jacobs, director, Advanced Analytics Product Management, Microsoft Corporation, another speaker in the program. “Rapid growth of statistics-oriented languages like R across industries is making it easier for manufacturers and equipment suppliers to capture, visualize and learn from data, and then build those learnings into dashboards for rapid deployment, or build them directly into automated applications and in some cases, machines themselves.”

Intel has reported using commercially available systems such as Cloudera, Aquafold, and Revolution Analytics (now part of Microsoft) to combine, store, analyze and display results from a wide variety of structured and unstructured manufacturing data. The system has been put to work to determine ball grid placement accuracy from machine learning from automatic comparison of thousands of images to select the any that deviate from the known-good pattern,  far more efficiently than human inspectors, and also to analyze tester parametrics to predict 90% of potential failures of the test interface unit before they happen.

“The IC industry may be ahead in the masses of data it gathers, but other industries are driving the methodology for easy management of the data,” he contends. “There’s a lot that can be leveraged from other industries to improve product quality, supply chain operations, and line up-time in the semiconductor industry.”

Demands for faster development of more complex devices require new approaches

As the cost of developing faster, smaller, lower power components gets ever higher, the dual sourcing strategies of automotive and other big IC users puts even more pressure on device makers to get the product right the first time. “There’s no longer time to learn with iterations to gradually improve the yield over time, now we need to figure out how to do this faster, as well as how to counter higher R&D costs on lower margins,” notes Sia Langrudi, Siemens VP Worldwide Strategy and Business Development,   who will also speak in the program.

The first steps are to recognize the poor visibility and traceability from design to manufacturing, and to put organizational discipline into place to remove barriers between silos. Then a company needs good baseline data, to be able to see improvement when it happens. “It’s rather like being an alcoholic, the first step is to recognize you have a problem,” says Langrudi. “People tell me they already have a quality management system, but they don’t. They have lots of different information systems, and unless they are capturing the information all in one place, the opportunity to use it is not there.”

Other speakers discussing these issues in the Smart Manufacturing Forum at SEMICON West July 14 include Amkor SVP Package Products Robert Lanzone, Applied Materials VP New Markets & Services Chris Moran, Intel VP IoT/GM Industrial Anthony Neal Graves, NextNine US Sales Manager Don Harroll, Optimal+ VP WW Marketing David Park, Qualcomm SVP Engineering Michael Campbell, Rudolph Technologies VP/GM Software Thomas Sonderman, and Samsung Sr Director, Engineering Development, Austin, Ben Eynon.

Learn more about the speakers at the SEMICON West 2016 session “Smart Manufacturing: The Key Opportunities and Challenges of the Next Generation of Manufacturing for the Electronics Value Chain.” To see all sessions in the Extended Supply Chain Forum, click here.

Scientists at UC San Diego, MIT and Harvard University have engineered “topological plexcitons,” energy-carrying particles that could help make possible the design of new kinds of solar cells and miniaturized optical circuitry.

The researchers report their advance in an article published in the current issue of Nature Communications.

Within the Lilliputian world of solid state physics, light and matter interact in strange ways, exchanging energy back and forth between them.

“When light and matter interact, they exchange energy,” explained Joel Yuen-Zhou, an assistant professor of chemistry and biochemistry at UC San Diego and the first author of the paper. “Energy can flow back and forth between light in a metal (so called plasmon) and light in a molecule (so called exciton). When this exchange is much faster than their respective decay rates, their individual identities are lost, and it is more accurate to think about them as hybrid particles; excitons and plasmons marry to form plexcitons.”

Materials scientists have been looking for ways to enhance a process known as exciton energy transfer, or EET, to create better solar cells as well as miniaturized photonic circuits which are dozens of times smaller than their silicon counterparts.

“Understanding the fundamental mechanisms of EET enhancement would alter the way we think about designing solar cells or the ways in which energy can be transported in nanoscale materials,” said Yuen-Zhou.

The drawback with EET, however, is that this form of energy transfer is extremely short-ranged, on the scale of only 10 nanometers (a 100 millionth of a meter), and quickly dissipates as the excitons interact with different molecules.

One solution to avoid those shortcomings is to hybridize excitons in a molecular crystal with the collective excitations within metals to produce plexcitons, which travel for 20,000 nanometers, a length which is on the order of the width of human hair.

Plexcitons are expected to become an integral part of the next generation of nanophotonic circuitry, light-harvesting solar energy architectures and chemical catalysis devices. But the main problem with plexcitons, said Yuen-Zhou, is that their movement along all directions, which makes it hard to properly harness in a material or device.

He and a team of physicists and engineers at MIT and Harvard found a solution to that problem by engineering particles called “topological plexcitons,” based on the concepts in which solid state physicists have been able to develop materials called “topological insulators.”

“Topological insulators are materials that are perfect electrical insulators in the bulk but at their edges behave as perfect one-dimensional metallic cables,” Yuen-Zhou said. “The exciting feature of topological insulators is that even when the material is imperfect and has impurities, there is a large threshold of operation where electrons that start travelling along one direction cannot bounce back, making electron transport robust. In other words, one may think about the electrons being blind to impurities.”

Plexcitons, as opposed to electrons, do not have an electrical charge. Yet, as Yuen-Zhou and his colleagues discovered, they still inherit these robust directional properties. Adding this “topological” feature to plexcitons gives rise to directionality of EET, a feature researchers had not previously conceived. This should eventually enable engineers to create plexcitonic switches to distribute energy selectively across different components of a new kind of solar cell or light-harvesting device.

Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.