Category Archives: Device Architecture

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $88.3 billion for the third quarter of 2016, marking the industry’s highest-ever quarterly sales and an increase of 11.5 percent compared to the previous quarter. Sales for the month of September 2016 were $29.4 billion, an increase of 3.6 percent over the September 2015 total of $28.4 billion and 4.2 percent more than the previous month’s total of $28.2 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has rebounded markedly in recent months, with September showing the clearest evidence yet of resurgent sales,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The industry posted its highest-ever quarterly sales total, with most regional markets and semiconductor product categories contributing to the gains. Indications are positive for increased sales in the coming months, but it remains to be seen whether the global market will surpass annual sales from last year.”

Regionally, month-to-month sales increased in September across all markets: China (5.4 percent), the Americas (4.6 percent), Asia Pacific/All Other (4.2 percent), Japan (2.3 percent), and Europe (1.6 percent). Compared to the same month last year, sales in September increased in China (12.0 percent), Japan (4.2 percent), and Asia Pacific/All Other (1.7 percent), but decreased in the Americas (-2.4 percent) and Europe (-4.0 percent).

“China stood out in September, leading all regional markets with growth of 5 percent month-to-month and 12 percent year-to-year,” Neuffer said. “Standouts among semiconductor product categories included NAND flash and microprocessors, both of which posted solid month-to-month growth in September.”

September 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.43

5.68

4.6%

Europe

2.71

2.76

1.6%

Japan

2.74

2.80

2.3%

China

8.99

9.47

5.4%

Asia Pacific/All Other

8.37

8.73

4.2%

Total

28.24

29.43

4.2%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.82

5.68

-2.4%

Europe

2.87

2.76

-4.0%

Japan

2.69

2.80

4.2%

China

8.45

9.47

12.0%

Asia Pacific/All Other

8.58

8.73

1.7%

Total

28.41

29.43

3.6%

Three-Month-Moving Average Sales

Market

Apr/May/Jun

Jul/Aug/Sept

% Change

Americas

4.94

5.68

15.0%

Europe

2.68

2.76

3.0%

Japan

2.53

2.80

10.8%

China

8.29

9.47

14.2%

Asia Pacific/All Other

7.97

8.73

9.5%

Total

26.41

29.43

11.5%

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016.

For more than six decades, the annual IEEE International Electron Devices Meeting (IEDM) has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors and related micro/nanoelectronics devices.

That tradition continues this year with a few new twists, including a supplier exhibition and a later paper- submission deadline (August 10) of a final, four-page paper. Accepted papers will appear in the proceedings without any changes. This streamlined process will ensure that even as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016, beginning with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events will precede a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of greatinterest,IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

Here are some of the noteworthy events that will take place at this year’s IEDM:

Special Focus Sessions

• Wearable Electronics and Internet of Things (IoT) – Wearable technology offers great promise for communica- tions, fitness tracking, health monitoring, speech therapy, elder care/assisted living and many other applications. This Special Focus Session has been organized to benchmark wearable electronics technologies, to address applications with comprehensive system demonstrations, and to learn indus- trial perspectives about the gaps, challenges and opportu- nities for wider uses of wearable and IoT technologies. Papers on flexible/stretchable electronics, MEMs, display devices, sensors, printed electronics, organic devices and 2-D material devices enabling wearables/IoT devices also will be featured.

• Quantum Computing – As traditional CMOS scaling enters the post-Moore’s Law era, quantum computing has emerged as a possible candidate for further device scaling because it exploits the laws of quantum physics and may make much more powerful computers possible. This Special Focus Session will explore relevant semiconductor-related fabri- cation issues and will brainstorm R&D directions for new materials, devices, circuits, and manufacturing approaches for the scalable integration of a large number of qubits with CMOS technology, operating at cryogenic temperatures for the realization of quantum computers.

• System-Level Impact of Power Devices – While there are forums that serve circuit experts for the exchange of ideas and the reporting of breakthroughs, there hasn’t been a suitable forum for bringing device and circuit experts together to consider impacts at the system level, even though that would be fruitful due to the interactions of circuits and devices. IEDM aims to serve as the forum for their dialogue, and so this Special Focus Session has been organized. Papers are expected to explore the system-level impact of power devices, and also to describe various types of power devices targeting the full range of power/power conversion applications such as hybrid vehicles, utility and grid control, computing/telecom power supplies, motor drives, and wireless power transfer.
• Ultra-High-Speed Electronics – There have been many advances and breakthroughs in ultra-high-speed electronics for communications, security and imaging applications, but technology gaps continue to prevent spectrum above milli- meter-wave frequencies from being fully used. This Special Focus Session has been organized to discuss, showcase and benchmark advanced ultra-high speed devices and circuits based on high-electron-mobility transistors (HEMTs), hetero- junction bipolar transistors (HBTs) and conventional CMOS devices; high-speed interconnect; antennas for ultra-high- speed systems; ultra-high-frequency oscillators; and to discuss other possible applications.

90-Minute Tutorials – Saturday, Dec. 3

A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, to bridge the gap between textbook-level knowledge and leading-edge current research. Advance regis- tration is recommended.

• The Struggle to Keep Scaling BEOL, and What We Can Do Next, Dr. Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries – Looking ahead, it’s the interconnect that threatens further cost-effective scaling. The tutorial will cover challenges and trade-offs in back- end-of-the-line(BEOL)scaling,andwillevaluateemerging devices from a scaled-BEOL viewpoint.

• Electronic Circuits and Architectures for Neuro- morphic Computing Platforms, Prof. Giacomo Indiveri, Univ. of Zurich and ETH Zurich – This tutorial will cover the principles and origins of neuromorphic (i.e., brain-inspired) engineering, examples of neuromorphic circuits, how neural network architectures can be used to build large-scale multi-core neuromorphic processors, and some specific application areas well-suited for neuromorphic computing technologies.

• Physical Characterization of Advanced Devices, Prof. Robert Wallace, Univ. Texas at Dallas – This tutorial will cover the hardware, physics, and chemistry that enable modern physical characterization of novel electronic materials, and will explore how these techniques can shed light on electronic materials research and development, and on the resultant devices. In addition to introducing examples of novel electronic materials for device applications, example techniques discussed will include high-resolution electron microscopy, scanning tunneling microscopy and spectroscopy, dynamic x-ray photoelectron spectroscopy, and ion mass spectrometry. The detection limits of these techniques and how they relate to device behavior also will be discussed.

• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Dr. Ben Kaczer, Principal Scientist, Imec – This tutorial will introduce the main degradation mechanisms occurring in present-day CMOS. The reliability of novel devices (SiGe, IIIV, gate-all-around nanowires, junctionless FETs, tunnel FETs), of deeply-scaled devices, and of circuits (e.g., “reliability-aware” designs) will be covered in detail. The tutorial will give attendees an overview and background in this area sufficient to allow them to follow and participate in any discussion on reliability in general, and on front-end- of-the-line (FEOL) reliability in particular.

• Spinelectronics: From Basic Phenomena to Magneto- resistive Memory (MRAM) Applications, Dr. Bernard Dieny, Chief Scientist, Spintec CEA — This tutorial will cover spintronics phenomena, magnetic tunnel junctions (growth, magnetic and transport properties), field-written MRAM (toggle and thermally assisted MRAM), STT-MRAM (principle and status of development), 3-terminal MRAM andinnovativearchitecturesthatbenefitfromthesehigh- endurance non-volatile memories.

• Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Dr. Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor — This tutorial will coverarangeoftechnologyopportunitiesforIoTandwearable applications, including embedded non-volatile memories (eNVM), IPs and integrated solutions based on charge-trap memory technologies such as SONOS for low power (LP) and ultra-low-power (ULP) for advanced technology nodes. Technologies will be described for various integrated IoT, wearableandenergy-harvestingsystemsusingprogrammable systems-on-chips (SoCs) with digital and analog capabilities, along with low-energy Bluetooth radio, WiFi radio, solar cells, sensors, actuators, and power management ICs. Advanced small form-factor packaging technologies useful for system integration also will be described.

Short Courses – Sunday, Dec. 4

The Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance regis- tration is recommended.

1. Technology Options at the 5-Nanometer Node, organized by An Steegen and Dan Mocuta of Imec (Sr. Vice President of Technology Development/Director of Logic Device and Integration, respectively) – This course will describe the complex technological challenges at the 5nm node and explore innovative potential solutions. It begins with an in-depth discussion of patterning strategies being pursued to print critical features. Then, a pair of lectures will provide an overview of current transistor technologies and their relative strengths/ weaknesses in the context of various applications such as mobility, data centers and IoT. Strategies for effective mitigation of performance-limiting parasitic resistance and capacitance will be discussed, and advanced interconnect technologies including post- copper materials options for BEOL and MEOL appli- cations will be addressed. Lastly, metrology challenges for in-line and end-of-line process technologies will be discussed. The intent of the course is to provide a thorough understanding in process technology targets at the 5nm node and their potential solutions. Attendees will have the opportunity to learn about advanced technology options that are being actively pursued in the industry from leading technologists.

The course consists of lectures from six distinguished speakers:

• Nano Patterning Challenges at the 5nm Node, Akihisa Sekiguchi, VP & Deputy GM, SPE Marketing and Process Development Division, Tokyo Electron, Japan

• Novel Channel Materials for High-Performance and Low-Power CMOS, Nadine Collaert, Distinguished Member of the Technical Staff, imec, Belgium

• Transistor Options & Challenges for 5nm Technology, Aaron Thean, Professor of Electrical & Computer Engineering, National University of Singapore

• Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance, Reza Arghavani, Managing Director, Lam Research, USA

• Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology, Theodorus Standaert, Sr. Engineering Mgr., Manager, Process Integration, IBM, USA

• Metrology Challenges for 5nm Technology, Ofer Adan, Technologist and Global Product Manager, Member of the Technical Staff, Applied Materials, Israel

2. Design/Technology Enablers for Computing Applications, organized by John Chen, Vice President of Technology and Foundry Management, NVIDIA – This course will describe how various design techniques and process technologies can enable computing applications, beginning with the relative advantages and disadvantages of processors such as CPU, GPU and FPGA with regard to today’s high data demands. It then will cover how memory becomes a bottleneck, and will discuss various emerging memory technol- ogies to mitigate the problem. Because managing power dissipation has become critical, it also will offer a broad perspective on power efficiency in computing and how interconnect plays a pivotal role in both performance and energy efficiency. Finally, 2.5-D and 3-D advanced packaging technology is discussed for system integration.

The course consists of lectures from five distinguished speakers:

• The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape, Liam Madden, Corporate VP, Hardware & Systems Development, Xilinx, USA

• Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective, Gabriel Molas, PhD Engineer, Leti, France

• Power Management with Integrated Power Devices… and how GaN Changes the Story, Alberto Doronzo, Power System/Apps Engineer, Texas Instruments, USA

• Interconnect Challenges for Future Computing, William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor, USA

• Advanced Packaging Technologies for System Integration, Douglas Yu, Sr. Director, TSMC, Taiwan

This article was originally posted on SemiMD.com and was featured in the October 2016 issue of Solid State Technology.

By Ed Korczynski, Sr. Technical Editor

3D-NAND chips are in production or pilot-line manufacturing at all major memory manufacturers, and they are expected to rapidly replace most 2D-NAND chips in most applications due to lower costs and greater reliability. Unlike 2D-NAND which was enabled by lithography, 3D-NAND is deposition and etch enabled. “With 3D-NAND you’re talking about 40nm devices, while the most advanced 2D-NAND is running out of steam due to the limited countable number of stored electrons-per-cell, and in terms of the repeatability due to parasitics between adjacent cells,” reminded Harmeet Singh, corporate vice president of Lam Research in an exclusive interview with SemiMD to discuss the company’s presentation at the Flash Memory Summit 2016.

“We’re in an era where deposition and etch uniquely define the customer roadmap,” said Singh,“and we are the leading supplier in 3D-NAND deposition and etch.” Though each NAND manufacturer has different terminology for their unique 3D variant, from a manufacturing process integration perspective they all share similar challenges in the following simplified process sequences:

1)    Deposition of 32-64 pairs of blanket “mold stack” thin-films,

2)    Word-line hole etch through all layers and selective fill of NAND cell materials, and

3)    Formation of “staircase” contacts to each cell layer.

Each of these unique process modules is needed to form the 3D arrays of NVM cells.

For the “mold stack” deposition of blanket alternating layers, it is vital for the blanket PECVD to be defect-free since any defects are mirrored and magnified in upper-layers. All layers must also be stress-free since the stress in each deposited layer accumulates as strain in the underlying silicon wafer, and with over 32 layers the additive strain can easily warp wafers so much that lithographic overlay mismatch induces significant yield loss. Controlled-stress backside thin-film depositions can also be used to balance the stress of front-side films.

Hole Etch

“The difficult etch of the hole, the materials are different so the challenges is different,” commented Singh about the different types of 3D-NAND now being manufactured by leading fabs. “During this conference, one of our customer presented that they do not see the hole diameters shrinking, so at this point it appears to us that shrinking hole diameters will not happen until after the stacking in z-dimension reaches some limit.”

Tri-Layer Resist (TLR) stacks for the hole patterning allow for the amorphous carbon hardmask material to be tuned for maximum etch resistance without having to compromise the resolution of the photo-active layer needed for patterning. Carbon mask is over 3 microns thick and carbon-etching is usually responsive to temperature, so Lam’s latest wafer-chuck for etching features >100 temperature control zones. “This is an example of where Lam is using it’s processes expertise to optimize both the hardmask etch as well as the actual hole etch,” explained Singh.

Staircase Etch

The Figure shows a simplified cross-sectional schematic of how the unique “staircase” wordline contacts are cost-effectively manufactured. The established process of record (POR) for forming the “stairs” uses a single mask exposure of thick KrF photoresist—at 248nm wavelength—to etch 8 sets of stairs controlled by a precise resist trim. The trimming step controls the location of the steps such that they align with the contact mask, and so must be tightly controlled to minimize any misalignment yield loss.

Lam is working on ways to tighten the trimming etch uniformity such that 16 sets of stairs can be repeatably etched from a single KrF mask exposure. Halving the relative rate of vertical etch to lateral etch of the KrF resist allows for the same resist thickness to be used for double the number of etches, saving lithography cost. “We see an amazing future ahead because we are just at the beginning of this technology,” commented Singh.

—E.K.

Analog Devices, Inc. (NASDAQ: ADI) today announced the acquisition of Innovasic Inc., a provider of Deterministic Ethernet semiconductor and software solutions. The acquisition adds a suite of multiprotocol Industrial Ethernet solutions and key enabling technologies to ADI’s Smart Automation Solutions portfolio for industrial automation and Industrial Internet of Things (IoT).

With the industrial automation market already transitioning from serial fieldbus to Ethernet connectivity, and with the simultaneous push toward a ubiquitous Industrial IoT, there is a clear need for highly reliable, real-time Ethernet connectivity for sensitive industrial automation applications. The acquisition of Innovasic will give ADI customers immediate access to a set of innovative solutions for today’s Industrial Ethernet applications while also creating a best-in-class roadmap for future connectivity needs like Industrial IoT. These solutions will complement ADI’s existing high-performance Industrial Automation solutions, including Software Configurable IO, Field Instruments, and efficient servo drives.

“In environments such as automotive manufacturing, where teams of robots are working in tandem in harsh and noisy conditions, our automation customers demand robust, synchronized, network technology,” said Kevin Carlin, General Manager of ADI’s Automation Business Unit. “These customers also strive to achieve the efficiency and cost improvements promised by wider deployment of Ethernet with the upcoming Industrial IoT. The IEEE has recognized that new standards will be required to enable Ethernet to meet the determinism demands for these emerging applications and is developing the new Time Sensitive Networks (TSN) standards. Innovasic technology not only addresses today’s Industrial Ethernet, but has also been demonstrated to address some of the early requirements of these new IEEE TSN standards. With this acquisition, ADI is now able to offer its customers a path forward from the sensor to the connected future of Industrial IoT.”

The Innovasic team will join ADI’s Industrial Automation Business Unit and operate as a key technology group, developing the company’s Deterministic Ethernet technology solutions and continuing to supply industrial customers with its portfolio of long life-cycle semiconductors. The team will be led by Jordon Woods, Innovasic’s co-founder and COO, and continue to be based in Albuquerque, New Mexico.

“We are excited to become part of Analog Devices and its ‘Smart Automation’ solution set,” said Woods. “Innovasic and ADI have both pursued solutions to customers’ most challenging technical problems while committing to maintain long product life cycles to meet the unique requirements of the industrial market. Together, we will be able to effectively and efficiently solve the communications needs of customers serving the most demanding industrial automation environments on the planet.”

The Global Semiconductor Alliance (GSA) announced the winner of the 2016 Dr. Morris Chang Exemplary Leadership Award: President and CEO of Cadence Design Systems, Inc. and Founder and Chairman of Walden International, Mr. Lip-Bu Tan. He will be presented with this achievement award during the GSA Awards Dinner Celebration on Thursday, December 8, 2016, at the Santa Clara Convention Center in Santa Clara, Calif.

“Lip-Bu Tan epitomizes what the Dr. Morris Chang Exemplary Leadership Award encompasses,” said Jodi Shelton, president of GSA. “We are honored to present this year’s award to someone who is a true global technology visionary that first helped pioneer the concept of venture capitalism worldwide and then lead Cadence Design Systems to the success, growth and strong customer focus that it enjoys today. Tan’s contribution to GSA and the entire semiconductor industry has and will continue to make a lasting impact.”

Established in 1999, the first GSA “Exemplary Leadership Award” was given to Dr. Morris Chang, chairman and chief executive officer of Taiwan Semiconductor Manufacturing Corporation (TSMC). Today, the Dr. Morris Chang Exemplary Leadership Award recognizes individuals for their exceptional contributions, exemplifying how their vision and global leadership have transformed and elevated the entire semiconductor industry.

“I am extremely honored and humbled to receive this award named after my close friend and role model Morris Chang, and which has been bestowed earlier on many amazing pioneers in our industry,” said Lip-Bu Tan. “I have learned so much from my peers in the global semiconductor industry and it has been my privilege to contribute in some way to their success through investments by Walden and collaboration by Cadence, leading to the delivery of some truly inspiring end products.”

Tan has served as President and CEO of Cadence Design Systems, Inc. since January 2009 and has been a member of the Cadence Board of Directors since February 2004. In 2015 and 2016, Cadence was named to FORTUNE’s list of the “100 Best Companies to Work For”. Tan founded Walden International in 1987 and currently serves as Chairman. Tan has been active in the venture capital industry for more than two decades. He specializes in cross border & early-stage technology investment. Prior to Walden International, he was Vice President at Chappell & Co. and held management positions at EDS Nuclear and ECHO Energy.

Tan is Co-Chairman of the Board of Directors of the Electronic System Design Alliance (ESD Alliance) and serves on the board of Global Semiconductor Association (GSA), as well as the boards of Ambarella Inc., Hewlett Packard Enterprise Co., and Semiconductor Manufacturing International Corp. He also serves on the Board of Trustees and the School of Engineering Dean’s Council at Carnegie Mellon University (CMU).

Tan holds an M.S. in Nuclear Engineering from Massachusetts Institute of Technology, an M.B.A. from the University of San Francisco, and a B.S. in Physics from Nanyang University in Singapore.

Each year the GSA recognizes companies that have demonstrated excellence through their vision, strategy, execution and future opportunity. The celebration honors the achievements of semiconductor companies in several categories ranging from outstanding leadership to financial accomplishments, as well as overall respect within the industry. The Awards Dinner Celebration will start at 5:00 p.m. with a networking reception, followed by dinner at 6:15 p.m. To make reservations to attend the Awards Dinner, visit the event website.

Qualcomm to acquire NXP


October 27, 2016

Qualcomm Incorporated (NASDAQ:  QCOM) and NXP Semiconductors N.V. (NASDAQ:  NXPI) today announced a definitive agreement, unanimously approved by the boards of directors of both companies, under which Qualcomm will acquire NXP.  According to Qualcomm’s official press release, a subsidiary of Qualcomm will commence a tender offer to acquire all of the issued and outstanding common shares of NXP for $110.00 per share in cash, representing a total enterprise value of approximately $47 billion.

NXP is a developer of high-performance, mixed-signal semiconductor electronics, with products and solutions and leadership positions in automotive, broad-based microcontrollers, secure identification, network processing and RF power.  As a semiconductor solutions supplier to the automotive industry, NXP also has leading positions in automotive infotainment, networking and safety systems, with solutions designed into 14 of the top 15 infotainment customers in 2016.  NXP has a broad customer base, serving more than 25,000 customers through its direct sales channel and global network of distribution channel partners.

“With innovation and invention at our core, Qualcomm has played a critical role in driving the evolution of the mobile industry.  The NXP acquisition accelerates our strategy to extend our leading mobile technology into robust new opportunities, where we will be well positioned to lead by delivering integrated semiconductor solutions at scale,” said Steve Mollenkopf, CEO of Qualcomm Incorporated.  “By joining Qualcomm’s leading SoC capabilities and technology roadmap with NXP’s leading industry sales channels and positions in automotive, security and IoT, we will be even better positioned to empower customers and consumers to realize all the benefits of the intelligently connected world.”

The combined company is expected to have annual revenues of more than $30 billion, serviceable addressable markets of $138 billionin 2020 and leadership positions across mobile, automotive, IoT, security, RF and networking.  The transaction has substantial strategic and financial benefits:

  • Complementary technology leadership in strategically important areas: The transaction combines leadership in general purpose and automotive grade processing, security, automotive safety sensors and RF; enabling more complete system solutions.
    • Mobile: A leader in mobile SoCs, 3G/4G modems and security.
    • Automotive: A leader in global automotive semiconductors, including ADAS, infotainment, safety systems, body and networking, powertrain and chassis, secure access, telematics and connectivity.
    • IoT and Security: A leader in broad-based microcontrollers, secure identification, mobile transactions, payment cards and transit; strength in application processors and connectivity systems.
    • Networking: A leader in network processors for wired and wireless communications and RF sub-segments, Wave-2 11ac/11ad, RF power and BTS systems.
  • Enhanced go-to-market capabilities to serve our customers:  The combination of Qualcomm’s and NXP’s deep customer and ecosystem relationships and distribution channels enables the ability to deliver leading products and platforms at scale in mobile, automotive, IoT, industrial, security and networking.
  • Shared track record of innovation and commitment to operational discipline: Both companies have demonstrated a strong commitment to technology leadership and best-in-class product portfolios with focused investments in R&D.  Qualcomm and NXP have both taken action to position themselves for profitable growth, while maintaining financial and operational discipline.  
  • Substantial financial benefits: Qualcomm expects the transaction to be significantly accretive to non-GAAP EPS immediately upon close.  Qualcomm expects to generate $500 million of annualized run-rate cost synergies within two years after the transaction closes.  The transaction utilizes Qualcomm’s strong balance sheet and will be efficiently financed with offshore cash and new debt. The transaction structure allows tax efficient use of offshore cash flow and enables Qualcomm to reduce leverage rapidly.

Mollenkopf continued, “We have taken significant action to build a foundation for profitable growth and the acquisition of NXP is strongly aligned with our strategy.  Our companies both have substantial expertise in delivering industry-leading solutions to our global customers, built upon a shared commitment to technology innovation, focused R&D investments and strong financial and operational discipline.”

“The combination of Qualcomm and NXP will bring together all technologies required to realize our vision of secure connections for the smarter world, combining advanced computing and ubiquitous connectivity with security and high performance mixed-signal solutions including microcontrollers. Jointly we will be able to provide more complete solutions which will allow us to further enhance our leadership positions, and expand the already strong partnerships with our broad customer base, especially in automotive, consumer and industrial IoT and device level security,” said Rick Clemmer, NXP Chief Executive Officer. “United in a common strategy, the complementary nature of our technologies and the scale of our portfolios will give us the ability to drive an accelerated level of innovation and value for the whole ecosystem. Such a strong fit will bring opportunities for our employees and customers, as well as provide immediate attractive value for our shareholders, in creating the semiconductor industry powerhouse.”

Sir Peter Bonfield, Chairman of NXP’s Board of Directors, said, “This is a major step in my ten years’ Chairmanship of NXP, and I am very pleased to see that the board of NXP has unanimously approved the proposed transaction and fully supports and recommends the offer for acceptance to NXP shareholders.”

Semiconductor Manufacturing International Corporation (“SMIC”) (NYSE:  SMI; SEHK: 981), China’s largest and most advanced semiconductor foundry and one of the world’s largest foundries, and Synopsys, Inc. (Nasdaq:  SNPS) today announced that it has adopted Synopsys’ StarRC product as the standard solution for signoff parasitic extraction for its 28-nanometer (nm) process technology. This standardization is a result of a growing collaboration between SMIC and Synopsys to provide best-in-class solutions to mutual customers to meet their increasing needs for accuracy, performance and efficiency at advanced nodes. The StarRC solution delivered silicon-accurate extraction and productivity validated by SMIC for its 28nm process. The qualified StarRC technology files are available as the default in SMIC’s 28nm process design kits (PDKs) for both digital and custom designs.

“Continuing to build on the momentum of our 28nm process technology, a favorite node for semiconductor companies, is a priority for us, and the availability of qualified design tools is critical to support our expanding global customer base,” said Anderson Huang, senior director of technology development at SMIC. “The partnership with Synopsys represents an enduring commitment to providing customers with the high-quality technologies and standards for use with our world-class manufacturing process. The deployment of StarRC in our 28nm PDKs bolsters the resources available to our mutual customers through StarRC’s proven silicon accuracy and comprehensive capabilities for both digital and custom designs, allowing them to develop advanced designs with increased confidence and productivity.”

The StarRC product, an integral part of the Synopsys Galaxy Design Platform signoff solution, is the market leader and industry gold standard for gate-level and transistor-level parasitic extraction. It achieves superior performance and efficiency with its ultra-scalable multi-core architecture, simultaneous multi-corner (SMC) extraction and fast ECO capabilities, while maintaining industry-standard golden accuracy. The StarRC product provides extraction capabilities across a wide range of applications, from 100+ million instance digital system-on-chip (SoC) designs to custom memory, IP, standard cell and analog designs. Integration with Synopsys IC Compiler II place and route and PrimeTime® static timing analysis solutions allows designers to achieve even faster ECO design closure, while reducing disk space and processor core resources. In custom design environments, designers can cross-probe between parasitic and schematic views, annotate schematics with parasitics and perform visual debug. Significantly faster simulation runtimes and reduced disk space resources are realized through highly optimized extraction tuned for performance. The result of the collaboration between SMIC and Synopsys delivers qualified StarRC technology files in SMIC’s 28nm PDK that enable mutual customers to use a silicon-accurate and efficient extraction solution for their designs targeting SMIC’s 28nm node.

“Meeting customers’ increasing needs to address complexity and accelerate design and analysis cycles are critical to propel them to silicon success at advanced process technologies,” said Bijan Kiani, vice president of marketing for the Design Group at Synopsys. “SMIC’s standardization on StarRC for parasitic extraction for its 28nm process technology highlights the strong trust in our technology to deliver on these important requirements and supports the innovations being driven by our mutual customers.”

One of the mainstays of the System-on-a-Chip (SoC) market is the continued growth of the 3rd Party Semiconductor Intellectual Property (SIP) market. The products developed and marketed by the SIP market enable SoC designers to create amazing cutting-edge silicon solutions employed in every niche of today’s semiconductor market. A new Semico Research report, Licensing, Royalty and Service Revenues for 3rd Party SIP: A Market Analysis and Forecast for 2016, forecasts the market to exceed $8 billion by 2020. However, the ‘law of large numbers’ will assert itself, and the torrent of growth over the past 10 years will start to slow.

“The number of SIP blocks in all types of SoCs continues to climb, and the number of SoCs that have SIP blocks also continues to increase each year, a sure sign of a healthy market,” said Rich Wawrzyniak, Principal Analyst for ASIC & SoC at Semico Research Corp. “It is then appropriate to focus on the individual market segments instead of only on the total market revenue to discern where the strongest growth lies,” said Wawrzyniak.

Key findings of the report include:

  • The CPU IP market will account for 31.3% of total market revenues by 2020;
  • A licensable programmable fabric is entering the market from several companies bringing new capabilities and functionality to SoC designers;
  • The Asia Pacific IP market will have a CAGR of 13.1% through 2020;
  • New embeddable memory architectures are entering the market as licensable SIP, and for the first time they are supported by major silicon foundries. MRAM, STTRAM and ReRAM are poised to debut;
  • The China IP market is forecast to reach $1.4 billion by 2020.

This report includes the SIP market broken down by geographical region (Americas, Europe, Japan, Asia Pacific, and China) and provides a forecast for each region for Licensing, Royalty and Service revenues.

Aura Semiconductor, a provider of high performance analog mixed signal solutions, today announced that it has completed Series A round of equity investment from Bay Area based WRV Capital.

Aura has innovative semiconductor technology related to the Internet of Things (IoT) Radios, Timing and Portable Audio markets. Aura’s products bring significant differentiation with emphasis on high performance, low area and reduced power consumption.

“We have developed state of the art solutions across multiple verticals that are sampling with customers worldwide,” said Srinath Sridharan, CEO of Aura. “We stand to benefit immensely from WRV’s unmatched semiconductor sector knowledge and relationships to accelerate our growth.”

“We are excited to support Aura in all their product verticals,” said Lip-Bu Tan, Founder Partner of WRV Capital. “Their accomplished management team is tackling compelling market opportunities, with differentiated products that have clear benefits to end customers. We look forward to helping them scale globally.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced that its Custom Compiler tool has been certified by Samsung Electronics Co., Ltd. to support their 10-nanometer (nm) LPP (Low Power Plus) process. This included providing and validating a Custom Compiler process design kit (PDK) in the industry-standard iPDK format. The kit is available on request from Samsung.

The newly developed Samsung 10LPP iPDK includes all technology information needed to create schematics and layout for customer designs using the Custom Compiler tool with Samsung’s 10LPP process. This comprehensive kit includes support for the groundbreaking Custom Compiler visually-assisted automation flow. Custom Compiler features enabled by the kit include full coloring for triple-patterning, fast placement of FinFET device arrays with the Symbolic Editor, in-design resistance and capacitance reporting during layout, and high-performance in-design design rule checking (DRC).

“We worked with Synopsys to include Custom Compiler support for Samsung’s foundry process offerings,” said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. “This new 10LPP iPDK adds to our existing portfolio of iPDKs that are available for Synopsys Custom Compiler users.”

Unified with Synopsys circuit simulation, physical verification and digital implementation tools, Custom Compiler technology provides Samsung 10LPP process users with a comprehensive custom design solution that reduces FinFET layout time.

“Custom Compiler users include leading-edge customers that demand support for the latest process technologies,” said Bijan Kiani, vice president of product marketing at Synopsys. “Samsung and Synopsys worked together to enable Custom Compiler for Samsung’s 10LPP process, which can shorten layout time from days to hours.”