Category Archives: Device Architecture

By Paula Doe, SEMI

As the rate of traditional scaling slows, the chip sector looks increasingly to materials and design to move forward on multiple paths for multiple applications. Figuring out more effective ways to collaborate across silos will be crucial.

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

Source: IBM [IBM slide 6 in Strategic Materials Conference deck]

  1. Paradigm shift requires co-optimization

SMC-Image2

“Scaling has hit a wall, and there is no longer any single path forward,” noted Larry Clevenger, BEOL Architect and Technology Definition, IBM Research, at the SEMI Strategic Materials Conference 2016 (September 20-21). “The materials set we use in the middle and back end of line is running out of steam. We need new materials and design co-optimization.”  He noted EUV would much improve the critical tight pitch areas for the memory and BEOL for 7nm-5nm logic. But reducing the parasitics in the metal interconnect in middle of the line and BEOL will also be critical, with good results demonstrated from new materials like Si:P and Ge:Ga meta-stable alloys, cobalt instead of tungsten, self-forming encapsulation of copper by cobalt, and airgaps, all of which would require optimization of an ecosystem of appropriate cleaning, deposition and wet process technologies for integration. Changing the design to route the critical paths directly up to higher wiring levels where the wires are larger would also help reduce resistance.

“It’s a paradigm shift that what was once a process deviation is now an excursion,” said Archita Sengupta, Intel senior technologist, noting the need for new specialized tools to measure, monitor and control the process to detect ever tinier defects sooner. “We need more proactive cooperation across the supply chain for bottom up control of quality from suppliers.”

Showing impressive examples of imaging and computation enabling doctors to reduce errors in breast cancer detection by 85 percent, and even to operate on a beating heart, using Nvidia GPUs and artificial intelligence, Nvidia’s director of Advanced Technology John Hu noted, “We are at a real inflection point for demand for more compute power, and we can’t get there by just process scaling any more. We are going to have to rely on new architectures to rescue us from the increasingly imperfect reality of materials and processes.”

While almost every speaker stressed the increasing need for the different segments of the supply chain from materials to design to work more closely together to move technology forward along many new paths, the materials suppliers in the audience felt that progress could be better to make this happen. Some audience members talked among themselves of now being invited more often into the fabs to discuss material development, but still not being told much detail about the key target parameters. Material suppliers in the audience raised the issues of the time and expense needed to qualify their second sources for raw materials and precursors, to get the needed environmental certifications, and to find access to the expensive exotic multi-technology metrology tools capable of finding contaminates too small to see with conventional methods, before they could even bring in any potential material to be evaluated for use several years in the future.

Although speakers kept referring to the past Golden Age of Moore’s Law of regular two-year dimensional scaling, before the proliferation of alternatives, Tim Hendry, retiring Intel VP, Fab Materials, pointed out that it hadn’t really seemed like a Golden Age at the time. “As I remember, we thought it was pretty hard back then too.”

  1. Look to self-aligned and selective processes as scaling boosters

As lithography scaling slows down, new approaches will make creative use of deposition and etch to keep improving pattern resolution. “14nm is a real sweet spot technically for lithography that will be with us for a long time,” noted Anton DeVilliers, Tokyo Electron America director of Patterning Technology, suggesting a toolkit of assorted self-alignment and selective deposition and etch processes likely to see increasing use as resolution boosters as an alternative to pushing the lithography, such as collars at key points to protect the pattern, or self aligned patterning by selective etching.

Adding a protective ALD collar holds a key region open during etch to widen the process window and prevent shorts from process variation in tight pattern areas.

SMC-Image3

ALD snap collar holds the critical part of M1 pattern open to widen window in LELELE process…

SMC-Image4

So that overlay variation that would typically create a short…

SMC-Image5

Instead creates the desired pattern. Source: TEL

Using materials with different etch selectivity for different parts of a pattern, such as for alternate lines, enables the creation of a self aligned pattern at higher resolution than the lithography.  Different etch selectivity in alternate metal tracks could also reduce the number of exposure passes and improve overlay tolerance. “For 5nm nanowires, we’ll have to use selective ALD and ALE, controlled by self assembling monolayers,” noted DeVilliers. “We’ve done each of these steps on a tool, but now the challenge is to put them all together.”

  1. Progress on 3D alternatives

“To maintain the pace of progress we’ll have to change everything—we can’t do it with Moore’s Law,” said Bill Bottoms, chairman and CEO, Third Millennium Test Solutions, updating on the international effort to create a Heterogeneous Integration Roadmap. “Future progress will come from bringing active elements closer together through integration at the system level, with interconnect with photonics and plasmonics.” The aim is to map future needs to better enable precompetitive collaboration. The first edition of the roadmap is now slated to come out in March.

SMC-Image6

CEA-Leti researchers meanwhile are reporting good progress on lowering the temperatures of the various processes needed to build a second chip directly on top of a first, for monolithic 3D CMOS-on-CMOS integration.  Performance of the bottom chip degrades if the process temperatures for the top chip are >500°C, mainly because the NiPt silicide deteriorates, but replacing the NiPt with a more stable NiCo and adding an Si cap looks promising to increase stability. The 8nm active active layer for the top device is bonded atop the bottom device at room temperature and annealed 300C. Nanosecond laser thermal annealing and low temperature solid phase epitaxy regrowth help bring down temperatures for dopant activation. Cycles of deposition and etch replace selective epitaxy for the source and drain, while different precursors reduce process temperatures to 500-550C. “Later this year at IEDM we’ll demonstrate top CMOS made at 500°C with these developments,” said Philippe Rodriguez, CEA-Leti research engineer.

  1. Get used to the slow growth world 

The semiconductor industry will see silicon demand (MSI) pick up from this year’s 0.6 percent increase to  ~3.8 percent growth in 2017, and ~6.3 percent in 2018, as some uncertainty about interest rates and government policy in major countries resolves, according to the econometric semiconductor forecast from Hilltop Economics and LINX Consulting. “We got comfortable with 3 percent GDP growth in the world that we sell chips into, but since the 2009 recession we are only seeing about 2.4 percent growth,” said Duncan Meldrum, chief economist, Hilltop Economics. He noted that economists keep saying the world will get back to its regular 3 percent growth next quarter or year, but it hasn’t happened, probably because high government debt levels in most major economies tends to reduce growth by about reduces it. Silicon demand grows a little faster than GDP, but its trends generally track that global growth number more than in the past as the electronics industry matures.

  1. Wafer level fan out will shake up package materials sector

Now that it appears the 40 to 50 percent improvement in performance in the newest Apple A10 processor is largely from its wafer-level fan out packaging from TSMC, demand for the packaging approach is ramping fast. “This is one of the fastest ramps we’ve seem for a package in a long time,” said TechSearch International president Jan Vardaman. “It’s a very disruptive technology that will have a big impact on the industry.” The thinner, lower-cost packaging approach is also showing up in RF and audio codec chips in mobile phones, with  ~2 billion units just in Samsung and Apple phones, potentially bringing big changes to the packaging materials market. Laminate substrate suppliers will see demand plunge, copper post suppliers will see little change, and makers of wafer-level dielectrics could potentially see 3X growth in volume. “But don’t think you’ll see that in revenue, since customers will really beat the prices down.”

And in a final note, the gathered materials sector paused in a moment of silence for Dan Rose, who passed away on September 19.  Dan was a well-known market researcher and founder of Rose Associates with a focus on materials market data.

Originally published on the SEMI blog.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry business. An excerpt from the September Update, describing foundry sales by feature size, is shown below.

Figure 1

Figure 1

TSMC has long been the technology leader among the major pure-play foundries. As shown in Figure 1, 54% of TSMC’s 2016 revenue is expected to come from <40nm processing. GlobalFoundries, which has dedicated a large portion of its capacity to making advanced processors over the past few years, also generates a large portion of its sales based on leading-edge process technology and feature sizes. In 2016, 52% of GlobalFoundries’ sales are forecast to come from <40nm production.

Although GlobalFoundries and TSMC are forecast to have a similar share of their sales dedicated to <40nm technology this year, TSMC is expected to have almost 6x the sales volume at <40nm as compared to GlobalFoundries in 2016 ($15.6 billion for TSMC and $2.6 billion for GlobalFoundries). In contrast, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.

Because TSMC has a very large percentage of its sales targeting <40nm production, its revenue per wafer is forecast to increase at a CAGR of 3% from 2011 through 2016 as compared to a -1% CAGR expected for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC over this same timeperiod. Only 2% of SMIC’s 2016 sales are expected to come from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so low as compared to TSMC and GlobalFoundries.

It is interesting to note that the increase in pure-play foundry sales this year is forecast to be almost entirely due to <40nm feature size device sales (Figure 2). Although it is expected to represent 60% of total pure-play foundry sales in 2016, the ≥40nm pure-play IC foundry market is forecast to be flat this year. In contrast, the leading-edge <40nm pure-play foundry market in 2016 is expected to surge by 23%, increasing by a hefty $3.6 billion.

Figure 2

Figure 2

INVECAS Inc., an IP, ASIC and embedded software solutions provider, and GLOBALFOUNDRIES today announced the availability of foundation IP for GLOBALFOUNDRIES’ 14nm FinFET technology. The silicon-proven IP from INVECAS is optimized for the performance, power, and area requirements of high-performance “all-the-time” applications such as high-end smartphones, networking, server, and graphics processors. This application-tailored library enables customers to rapidly develop high-performance and power-efficient systems.

INVECAS IP taps the benefits of FinFET to deliver more processing power in a smaller footprint for the most demanding applications. The comprehensive IP portfolio includes foundation IP such as general-purpose I/O (GPIO), memories, standard cell libraries, and a full set of interface and analog IP solutions.

“GLOBALFOUNDRIES’ 14LPP offers a silicon-proven solution for customers seeking to differentiate their products and accelerate time-to-volume of designs on complex technologies,” said Alain Mutricy, senior vice president of product management at GLOBALFOUNDRIES. “We further enhance our technology through early engagement with ecosystem partners like INVECAS, to ensure a robust infrastructure with a low-risk, silicon-proven, and efficient design strategy. Our strategic relationship with INVECAS provides our customers with the 14LPP performance and power optimized IP platforms to push their SoC designs to new levels and deliver the highest performance silicon for a broad set of applications.”

“INVECAS is dedicated to overcoming SoC design challenges with optimized IP and silicon realization services on GLOBALFOUNDRIES’ processes,” said Dasaradha Gude, chairman and CEO of INVECAS Inc. “By combining our proven system-level expertise with GLOBALFOUNDRIES’ advanced 14nm FinFET technology, we are uniquely positioned to provide complete solutions for the compute, communication, mobile, and automotive markets.”

INVECAS will showcase its silicon-proven IP solutions during GLOBALFOUNDRIES Technology Conference (GTC) on September 29 at the Sofitel Munich Bayerpost in Munich, Germany.

North America-based manufacturers of semiconductor equipment posted $1.75 billion in orders worldwide in August 2016 (three-month average basis) and a book-to-bill ratio of 1.03, according to the August Equipment Market Data Subscription (EMDS) Book-to-Bill Report published by SEMI.  A book-to-bill of 1.03 means that $103 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in August 2016 was $1.75 billion. The bookings figure is 2.3 percent lower than the final July 2016 level of $1.80 billion, and is 5.0 percent higher than the August 2015 order level of $1.67 billion.

The three-month average of worldwide billings in August 2016 was $1.71 billion. The billings figure is approximately the same as the final July 2016 level of $1.71 billion, and is 8.4 percent higher than the August 2015 billings level of $1.58 billion.

“The book-to-bill ratio has been at or above parity since December of last year with current monthly bookings and billings levels at $1.7 billion,” said Denny McGuirk, president and CEO of SEMI.  “Given the current data trends, North American equipment suppliers are clearly benefiting from strong investments by device manufacturers in the second half of the year.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

  Billings
(3-mo. avg)		 Bookings
(3-mo. avg)		 Book-to-Bill
March 2016  $1,197.6 $1,379.2 1.15
April 2016  $1,460.2 $1,595.4 1.09
May 2016  $1,601.5 $1,750.5 1.09
June 2016  $1,715.2 $1,714.3 1.00
July 2016 (final) $1,707.9 $1,795.4 1.05
August 2016 (prelim) $1,708.1 $1,753.9 1.03

Source: SEMI (www.semi.org), September 2016

The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

The data are contained in a monthly Book-to-Bill Report published by SEMI. The report tracks billings and bookings worldwide of North American-headquartered manufacturers of equipment used to manufacture semiconductor devices, not billings and bookings of the chips themselves. The Book-to-Bill report is one of three reports included with the SEMI Equipment Market Data Subscription (EMDS).

At NXP FTF China today, NXP Semiconductors N.V. (NASDAQ:NXPI), officially announced the i.MX 6ULL applications processor which delivers up to 30 percent more power efficiency than its nearest competitors. The i.MX 6ULL was specifically designed for value-conscious engineers and developers working on cost-effective solutions for the growing IoT consumer and industrial, mass markets. The processor features secure encryption, advanced implementation of a single ARM® Cortex®-A7 core, provides various memory interfaces and includes an integrated power management module to reduce complexity.

“i.MX 6ULL maximizes cost efficiency, ease of use and low power – all of which are essential for innovative Internet of Things applications,” said Geoff Lees, senior vice president and general manager of the microcontroller business line at NXP. “The combination of better performance with aggressive pricing allows customers to deliver better digital interface experiences.”

i.MX 6ULL Features

This latest addition to the i.MX 6 series introduces a single Cortex-A7 processor core running up to 528 MHz with 128 KB of L2 cache and 16-bit DDR3/LPDDR2 support. Its integrated power management, security unit and wide range of connectivity interfaces, provides new ways to address performance scalability and low power for secure IoT applications. The i.MX 6ULL processor has compatible and scalable package options including the 14 x 14mm, ideal for simple and low-cost PCB design, and the 9 x 9mm, offering a smaller form factor for space-constrained applications.

“This product provides a natural upgrade from the previous ARM7 and ARM9 based architecture to a more power efficient, Cortex-A class core,” said George Zhou, President of ZLG Electronics Corporation. “The feature set, price point and power efficiency of i.MX 6ULL will enable us to develop the next generation smart grid monitoring system for all of China.”

Pricing and Availability 

The i.MX 6ULL applications processor will start at $3.50 USD in 10,000 unit quantities. The i.MX 6ULL applications processor is sampling now and is expected to be in full production in October 2016 along with the GA release of the Linux BSP. The i.MX 6ULL processor is supported by the i.MX 6ULL evaluation kit that includes a CPU module and a base board. A training class and demonstration of the i.MX 6ULL processor and EVK will be given during NXP FTF China. For more information, please visit www.nxp.com/iMX6ULL.

i.MX 6 Series Applications Processors

The i.MX 6 series of applications processors is a feature and performance scalable multicore platform that includes single-, dual- and quad-core families based on the ARM® Cortex® architecture, including Cortex-A9, combined Cortex-A9 + Cortex-M4 and Cortex-A7 based solutions up to 1.2 GHz. The series combines broad levels of integration and power-efficient processing capabilities all the way up to 3D and 2D graphics, as well as high-definition video and targets consumer, industrial and automotive applications.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it is increasing its focus on bringing its high-volume manufacturing process solutions and services to the biotechnology and medical device market. EVG products supporting this market include the company’s substrate bonding, hot-embossing, micro contact printing and UV-based nanoimprint lithography (NIL) systems. In addition, EVG will offer its world-class applications support, rapid prototyping and pilot-line production services. Customers in the biotechnology and medical markets can now leverage these patterning and sealing solutions–which have been production-proven in other industrial markets such as semiconductors, MEMS and photonics–for volume production of next-generation biotechnology devices featuring micrometer or nanometer-scale patterns and structures on larger-format substrates.

EV Group nanoimprint lithography solutions enable parallel processing of biotechnology and medical devices on large-area substrates.

EV Group nanoimprint lithography solutions enable parallel processing of biotechnology and medical devices on large-area substrates.

Over the past several decades, miniaturization of biotechnology devices has significantly improved clinical diagnostics, pharmaceutical research and analytical chemistry. Modern biotechnology devices–such as biomedical MEMS (bioMEMS) for diagnostics, cell analysis and drug discovery–are often chip-based and rely on close interaction of biological substances at the micro- and nanoscale. According to the market research and strategy consulting firm Yole Développement, an increasing number of healthcare applications are using bioMEMS components, while the bioMEMS market is expected to triple from US$2.7 billion in 2015 to US$7.6 billion in 2021. Microfluidic devices will represent the majority (86 percent) of the total bioMEMS market in 2021, driven by applications such as Point-of-Need testing, clinical and veterinary diagnostics, pharmaceutical and life science research, and drug delivery*.

Precise and cost-effective micro-structuring technologies are essential to successfully commercialize these products in a rapidly growing market that has stringent requirements and high regulatory hurdles. Traditional process approaches such as injection molding are often unable to produce the extremely small structures and surface patterns with the precision, quality and repeatability increasingly required for these demanding applications, or they require extensive effort in process development. At the same time, solutions are needed to scale up from discrete production of devices to batch processing of multiple devices on a single substrate in order to achieve the economies of scale required to commercialize these products.

NIL has evolved from a niche technology to a powerful high-volume manufacturing method that is able to produce a multitude of structures of different sizes and shapes on a large scale–such as highly complex microfluidic channels and surface patterns–by imprinting either into a biocompatible resist or directly into the bulk material. In addition to structuring technologies, sealing and encapsulation is a central process for establishing confined microfluidic channels. Thus, bonding of different device layers, capping layers or interconnection layers is a key process that can be implemented together with NIL in a cost-effective large-area batch process. As the pioneer as well as market and technology leader in NIL and wafer bonding, EVG is leading the charge in supporting the infrastructure and growth of the biotechnology market by leveraging its products for use in biotechnology applications.

EVG’s NIL solutions can produce a wide range of small structures (from hundreds of micrometers down to 20 nm) on a variety of substrate materials used in biotechnology applications, including glass, silicon and a variety of polymers (e.g., COC, COP, PMMA and PS). Each EVG NIL solution is uniquely suited for different production applications. For example, hot-embossing allows precise imprinting of larger structures as well as combinations of micro- and nanostructures, and is superior when replicating high-aspect ratio features or when using very-thin substrates. UV-NIL provides very-high precision, pattern fidelity and throughput in the nanometer-range. Micro contact printing, which is another NIL option, can transfer materials such as biomolecules onto a substrate in a distinct pattern.

With its established wafer-scale bonding equipment, EVG can also offer sealing and bonding processes that are well-aligned with NIL structuring technologies. A variety of different bonding options are available, ranging from advanced room-temperature bonding techniques to plasma activated bonding as well as high-quality hermetic sealing and vacuum encapsulation. Examples of typical solutions include EVG’s thermal bonding equipment for glass and polymer substrates, which provides excellent results by enabling high-pressure and temperature uniformities over large areas. EVG also offers its room-temperature selective adhesive transfer technology, which eases incorporation of bio-molecules prior to the encapsulation of the device.

“EVG has a long history of providing products and solutions for biomedical R&D, having installed the first hot embossing system for emerging bioMEMS and microfluidic research applications more than 15 years ago,” stated Dr. Thomas Uhrmann, director of business development at EV Group. “The knowledge that EVG has built up in this space coupled with our experience in bringing innovative technologies into volume production in other markets has positioned us well to provide proven high-volume manufacturing processes and services to the bio-medical industry to support the production of next-generation biotechnology devices.”

In addition to equipment and process solutions, EVG also offers prototyping and pilot-line production services to customers out of its cleanroom facilities at its corporate headquarters in Austria as well as its subsidiaries in North America and Japan.

Analogix Semiconductor, Inc. and Beijing Shanhai Capital Management Co, Ltd. (Shanhai Capital), today jointly announced that they have entered into a definitive merger agreement under which a consortium led by Shanhai Capital will acquire all of the outstanding shares of Analogix for over $500 million. China Integrated Circuit Industry Investment Fund Co., Ltd. (China IC Fund) also joined Shanhai Capital’s fund as one of the limited partners. The transaction is subject to regulatory approvals and is expected to close in late 2016.

Analogix’s high-speed, mixed-signal semiconductor integrated circuits (ICs) for high-performance display applications are used in mobile devices, virtual/augmented reality (VR/AR), and other high-performance electronic products from leading electronics brands including Apple, Samsung, LG, Microsoft, Google, Lenovo, Dell, HP, Asus, and HTC. The company is headquartered in Santa Clara, California, and the majority of its engineering operations are located in Beijing, China. Current investors include leading venture capital firms: DCM Ventures, Globespan Capital Partners, Keytone Ventures, and the Woodside Fund.

“We are very happy to have reached this agreement, which provides significant value to our shareholders,” said Dr. Kewei Yang, Analogix Semiconductor’s chairman and CEO. “The financial support of Shanhai Capital propels our growth while maintaining the direction, organization, and determination to serve our customers. I am especially excited that we all share the same vision of building Analogix into a much broader and more capable global semiconductor leader.”

“We are pleased to establish our relationship with Analogix, a company whose technology leadership is recognized by the world’s leading OEMs, and we look forward to facilitating Analogix’s continued growth,” said Mr. Xianfeng Zhao, Chairman of Beijing Shanhai Capital Management Co, Ltd. “With the added investment, we can leverage the strength of the company’s core technology and business expertise, extend our business into adjacent high-growth markets, and build a world-leading semiconductor company. We expect an IPO in China in the near future.”

The Semiconductor Industry Association (SIA), in consultation with Semiconductor Research Corporation (SRC), today presented its University Research Award to professors from the University of Chicago and the University of Michigan in recognition of their outstanding contributions to semiconductor research.

Dr. Paul Nealey, professor of molecular engineering at the University of Chicago, received the honor for excellence in technology research, while Dr. David T. Blaauw, professor of electrical engineering and computer science at the University of Michigan, was recognized for excellence in design research.

“Research brings to life the tremendous innovations that underpin the U.S. semiconductor industry, the broader tech sector, and our economy,” said John Neuffer, president and CEO of the Semiconductor Industry Association, which represents U.S. leadership in semiconductor manufacturing, design, and research.

“Professors Nealey and Blaauw have led research efforts that have advanced semiconductor technology and strengthened America’s global technology leadership. It is an honor to recognize Dr. Nealey and Dr. Blaauw for their landmark accomplishments.”

“SRC’s mission is to drive focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry,” said Ken Hansen, SRC President and CEO. “Dr. Nealey and Dr. Blaauw exemplify that spirit of innovation, and we’re pleased to honor them for their achievements.”

Dr. Nealey is a pioneer of directed self-assembly, which is becoming very important in microelectronics processing to create patterns for integrated circuits. He is one of the world’s leading experts on patterning organic materials. This entails creating physical patterns of structure and composition in organic materials at the nanometer length scale, where the patterns affect the function of the materials. Dr. Nealey holds 14 patents and is the author of more than 180 publications.

Dr. Blaauw worked for Motorola, Inc. from 1993-2001, where he was the manager of the High Performance Design Technology group. Since August 2001, he has been on the faculty at the University of Michigan where he is currently a full professor. His work has focused on VLSI design with particular emphasis on adaptive and low-power design. Dr. Blaauw received his B.S. from Duke University in 1986 and his Ph.D. from the University of Illinois, Urbana, in 1991.

The University Research Award was established in 1995 to recognize lifetime research contributions to the U.S. semiconductor industry by university faculty.

IC Insights recently released its September Update to the 2016 McClean Report. This Update included Part 2 of an extensive analysis of the IC foundry industry and a look at the current state of the merger and acquisition surge in the semiconductor industry. An excerpt from the M&A portion of this Update is shown below.

After an historic surge in semiconductor merger and acquisition agreements in 2015, the torrid pace of transactions has eased (until recently), but 2016 is already the second-largest year ever for chip industry M&A announcements, thanks to three major deals struck in 3Q16 that have a combined total value of $51.0 billion. As of the middle of September, announced semiconductor acquisition agreements this year have a combined value of $55.3 billion compared to the all-time high of $103.8 billion reached in all of 2015 (Figure 1). Through the first three quarters of 2015, semiconductor acquisition pacts had a combined value of about $79.1 billion, which is 43% higher than the total of the purchasing agreements reached in the same period of 2016, based on M&A data compiled by IC Insights.

In many ways, 2016 has become a sequel to the M&A mania that erupted in 2015, when semiconductor acquisitions accelerated because a growing number of suppliers turned to purchase agreements to offset slower growth in major existing end-use equipment applications (such as smartphones, PCs, and tablets) and to broaden their businesses to serve huge new market potentials, including the Internet of Things (IoT), wearable electronics, and strong segments in embedded electronics, like highly-automated automotive systems. China’s goal of boosting its domestic IC industry is also driving M&A. In the first half of 2016, it appeared the enormous wave of semiconductor acquisitions in 2015 had subsided substantially, with the value of transactions announced between January and June being just $4.3 billion compared to $72.6 billion in the same six-month period in 1H15. However, three large acquisition agreements announced in 3Q16, including SoftBank’s purchase of ARM, Analog Devices’ intended purchase of Linear Technology, and Renesas’ potential acquisition of Intersil) have insured that 2016 will be second only to 2015 in terms of the total value of announced semiconductor M&A transactions.

Figure 1

Figure 1

A major difference between the huge wave of semiconductor acquisitions in 2015 and the nearly 20 deals being struck in 2016 is that a significant number of transactions this year are for parts of businesses, divisions, product lines, technologies, or certain assets of companies.  This year has seen a surge in the agreements in which semiconductor companies are divesting or filling out product lines and technologies for newly honed strategies in the second half of this decade.

Solid State Technology announced today that its premier semiconductor manufacturing conference and networking event, The ConFab, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. A 30% increase in attendance in 2016 with a similar uplift expected in 2017, makes the venue an ideal meeting location as The ConFab continues to expand.

    

For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collaborate on critical issues.

“The semiconductor industry is maturing, yet opportunities abound,” said Pete Singer, Editor-in-Chief of Solid State Technology and Conference Chair of The ConFab. “The Internet of Things (IoT) is exploding, which will result in a demand for “things” such as sensors and actuators, as well as cloud computing. 5G is also coming and will be the key technology for access to the cloud.”

The ConFab is the best place to seek a deeper understanding on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportunities facing semiconductor manufacturers. “In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities,” Singer added.

Dave Mount

David Mount

Solid State Technology is also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees that will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GLOBALFOUNDRIES, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For details on attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].