Category Archives: Device Architecture

By Ted Shafer, Business Manager, Mature Product Sales, ASML

Ted Shafer of ASML reports on the highlights from the ≤200mm manufacturing session during SEMICON West, organized by the SEMI Secondary Equipment and Applications Special Interest Group. Your next opportunity to catch up on latest trends on ≤200mm manufacturing trends and its impact on the secondary equipment and applications market is SEMICON Europa 2016 and the Secondary Equipment Tech Arena session

Wednesday July 13th at SEMICON West a seminar and panel discussion were held to discuss the longevity and growth of the 200mm equipment market, and responses from IDMs, OEMs and 3rd parties to the challenges this growth presents.

Tim Tobin of Entrepix was the first speaker.  Entrepix is a premier 3rd party refurbisher of CMP and other process equipment.  Tim was the first to remark on a phenomenon that the other speakers and panelists also noted: a huge portion of the die in the devices we use daily do not require state of the art 300mm manufacturing.  For example, 60% – 80% of the chips in your smartphone or tablet are manufactured on 200mm – or smaller – wafers.  These wafers are created using mature equipment, which is frequently purchased from the secondary market, often from refurbishers such as Entrepix.

SEMI’s Christian Dieseldorff next provided a great overview of 200mm market trends, titled “200mm Fab: Trends, Status, and Forecast”.  Driven by the growth of IoT (Internet of Things), new 200mm fabs are being built and additional capacity is being added at existing fabs.  Key take-away is that after peaking in 2006, then declining for several years, 200mm wafer starts per month are now forecasted to exceed 2006’s level of 5.4M by 2019.  The question on everyone’s mind is, once that level is exceeded, where will the tools come from to manufacture those wafers?

200mm-image1

Pierric Gueguen of Yole spoke of the increased adoption of exotic substrates like GaN, Sapphire and Silicon Carbide.  These substrates provide many performance advantages, such as lower power consumption, faster switching speed, and high temperature resistance.  Yet the substrates cannot scale to 12”, and sometimes not to 8”.  So the increased adoption of these substrates is driving additional demand for 150mm/200mm tools.

As a counter-point to the 200mm discussions, Karen Erz of Texas Instruments gave a very well-received presentation on TI’s pivot to 300mm for analog, which has traditionally been manufactured on 200mm wafers.  A key to TI’s success is to embrace without fear buying opportunities for used equipment when they present themselves.  TI does not compete at the leading edge – their minimum feature size is 130nm – and thus mature, pre-owned, cost-effective equipment is always their first choice.  In fact, surplus 300mm is often more available, and less expensive, than comparable 200mm tools.  TI capitalized on the bankruptcies of the 300mm fabs of Qimonda Dresden, Qimonda Richmond, and PROMOS, also surplus tools at Powerchip, to scoop up large batches of inexpensive 300mm tools.  They continue to buy surplus 300mm tools when they come on the market, even in advance of actually requiring the tools.  As a result, 92% of RFAB’s analog production is done with pre-owned 300mm equipment.

Emerald Greig of Surplus Global, in addition to organizing the seminar, also provided a well-researched presentation on surplus equipment trends, titled “The Indispensable Secondary Market”.  Surplus Global is one of the largest surplus equipment traders, and they track the used equipment market very closely.  Emerald discussed how the supply of tools per year is trending dramatically downwards.  In 2009 they saw 6,000 tools come on the market, and that run-rate has steadily decreased to the point where by last year it was under 1,000/year.  This year we are at just 600.

200mm-image2

AMAT’s John Cummings provided the first OEM perspective on the 200mm market.  John showed how over 70% of the chips in the segments of automotive, wearables and mobile are produced on <=200mm wafers.  These segments are growing – for example a BMW i3 contains an astonishing 545 total die, and 484 of them are manufactured on <=200mm wafers.   AMAT reports that there are not enough used 200mm tools on the market to support the demand, and thus AMAT supplies their customers with new 200mm tools to augment the upgrades and refurbs they perform on pre-owned tools.  AMAT also provides new functionality for their mature 200mm products, increasing their usefulness and extending their lifetime.

Finally there was the OEM panel discussion, consisting of Kevin Chasey of TEL, David Sachse of LAM, Hans Peters from Ebara, and Ted Shafer of ASML.  Emerald Greig of Surplus Global provided some initial questions and solicited additional ones from the audience.   The OEMs echoed one common theme of the presentations, that 200mm demand is robust, and core tools are increasingly hard to find.  TEL additionally noted that China is a growing player in this market, and that OEMs must now support their 200mm product lines much longer than initially planned.  LAM said that 200mm core supply is so tight that the prices are rising above even comparable 300mm cores.  In response, LAM augments the supply of used tools by creating new 200mm tools.  Ebara added that the core tools coming on the market are often undesirable first-generation tools or tools in very bad condition.  On the other hand, this creates a role for the OEM, who has the expertise to make these tools production-worthy.  ASML noted that many of their larger 200mm customers are considering a migration from the PAS 5500 platform to ASML’s TWINSCAN platform for 200mm production.  Although developed for 300mm, and in general larger and more expensive than the 200mm 5500 series, ASML has spent the last 15 years making TWINSCANs increasingly productive and reliable, to the point where they often offer superior cost of ownership at 200mm than ASML’s 5500 platform.  Furthermore, customers buying TWINSCAN for 200mm production have an easy upgrade to 300mm when/if their plans call for it.

200mm-image3

In summary, the seminar showcased a robust exchange of ideas, where the presenters and panelists examined the resurgent 200mm market, and described many solutions to the common challenge of limited and expensive 200mm cores.

Attend SEMICON Europa and the Secondary Equipment & Applications session on October 26 to find out the latest trends and discuss in what areas OEMs, IDMs and secondary  market operators can cooperate more closely to improve sustainable access to legacy manufacturing equipment.

Find out more about SEMI’s Secondary Equipment and Applications Special Interest Group and the Secondary Equipment Legacy Management Program that is currently under development. For more information and to get involved, contact [email protected] (Ms. Rania Georgoutsakou, Director Public Policy for Europe, SEMI).

By Zvi Or-Bach, President & CEO, MonolithIC 3D Inc.

As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

Our March 2014 blog Moore’s Law has stopped at 28nm has recently been re-confirmed. At the time we wrote: “From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.” This reconfirmation can be found in the following IBS cost analysis table slide, presented at the early Sept FD-SOI event in Shanghai.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

As reported by EE Times – Chip Process War Heats Up, and quoting Handel Jones of IBS “28nm node is likely to be the biggest process of all through 2025”.

IBS prediction was seconded by “Samsung executive showed a foil saying it believes 28nm will have the lowest cost per transistor of any node.” The following chart was presented by Samsung at the recent SEMICON West (2016).

Zvi 2

And even Intel has given up on its “every two years” but still claims it can keep reducing transistor cost. Yet Intel’s underwhelming successes as a foundry suggests otherwise. We have discussed it in a blog titled Intel — The Litmus Test, and it was essentially repeated by SemiWiki’s Apple will NEVER use Intel Custom Foundry!

This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, with a few products pursuing scaling to 7nm while the majority of designs use 28nm or older nodes.

The following chart derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Zvi 3

Yes, the 50-year march of Moore’s Law has ended, and the industry is now facing a new reality.

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new markets and products such as the emerging market of IoT.

A good opportunity to learn more about these new scaling technologies is the IEEE S3S ’16, to be held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. It starts with 3D and FDSOI tutorials, the emerging technologies for the IC future. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from an imec, MIT, and Korea university collaboration will present their work on advanced monolithic 3D integration technologies. Many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.

GLOBALFOUNDRIES today introduced a scalable, embedded magnetoresistive non-volatile memory technology (eMRAM) on its 22FDX platform, providing system designers with access to 1,000x faster write speeds and 1,000x more endurance than today’s non-volatile memory (NVM) offerings. 22FDX eMRAM also features the ability to retain data through 260°C solder reflow, industrial temperature operation, while maintaining an industry-leading eMRAM bitcell size.

GLOBALFOUNDRIES’ eMRAM will be offered initially on its 22FDX platform, which leverages the industry’s first 22nm fully-depleted silicon-on-insulator (FD-SOI) technology. This versatile eMRAM technology is designed for both code storage (flash) and working memory (SRAM) to enable ultra-efficient memory sub-systems that can be power cycled without any energy or performance penalty. The power efficiency of FDX and eMRAM, coupled with the available RF connectivity IP, makes 22FDX an ideal platform for battery-powered IoT products and automotive MCUs.

“Customers are looking for a high-performance non-volatile memory solution that expands their product capabilities,” said Gregg Bartlett, senior vice president CMOS Platforms Business Unit, GLOBALFOUNDRIES. “Our introduction of 22FDX eMRAM enables system designers with new capabilities, allowing them to build greater functionality into their MCUs and SoCs, while enhancing performance and power efficiency.”

The emergence of autonomous vehicles is rapidly driving the need for increased on-chip memory capacities required for real-time vision processing, high-precision, continuous 3D mapping data and next-generation automotive MCUs that update over-the-air. GLOBALFOUNDRIES’ eMRAM uniquely addresses these advanced driving assistance system (ADAS) requirements by combining greater memory density than SRAM, with the fast write, very high endurance, and non-volatility that only magnetoresistive memory can provide.

“Emerging non-volatile memories are moving from the lab to the fab,” said Thomas Coughlin, President of Coughlin Associates. “GLOBALFOUNDRIES’ 22FDX eMRAM will offer a major advancement in SoC capabilities, by leveraging the key performance attributes of embedded MRAM. Designers of battery powered IoT devices, automotive MCUs and SoCs and SSD storage controllers will certainly want to take advantage of this versatile embedded NVM technology.”

The introduction of GLOBALFOUNDRIES’ 22FDX eMRAM is a result of the company’s multi-year partnership with MRAM pioneer, Everspin Technologies. The partnership has already delivered the world’s highest density ST-MRAM in August, 2016  – Everspin’s 256Mb DDR3 perpendicular magnetic tunnel junction (pMTJ) product, which is now successfully sampling and is being readied for mass production at GLOBALFOUNDRIES.

GLOBALFOUNDRIES’ 22FDX eMRAM is currently in development and is expected to be available for customer prototyping in 2017, with volume production in 2018. GLOBALFOUNDRIES’ eMRAM technology is scalable beyond 22nm and is expected to be available on both FinFET and future FDX platforms.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, announced worldwide sales of semiconductors reached $27.1 billion for the month of July 2016, an increase of 2.6 percent compared to the previous month’s total of $26.4 billion. July marked the global market’s largest month-to-month sales increase since September 2013, though sales were down 2.8 percent compared to the July 2015 total of $27.9 billion. Underscoring the welcome uptick, month-to-month sales increased in all regional markets for the first time since October 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The modest increase in global semiconductor sales in July was the global market’s largest month-to-month growth in nearly three years, an encouraging sign of potentially stronger sales during the remainder of 2016 and beyond,” said John Neuffer, president and CEO, Semiconductor Industry Association. “After months of lagging sales, the Americas region was a bright spot in July, posting 3.3 percent growth to lead all regional markets. Meanwhile, most major semiconductor product categories saw increased sales in July compared to the previous month, with DRAM leading the way with 7.1 percent growth.”

In addition to the month-to-month growth in the Americas, sales also increased in China (3.2 percent), Japan (3.1 percent), Asia Pacific/All Other (1.8 percent), and Europe (0.7 percent). Year-to-year sales increased in China (4.7 percent), but dropped in Japan (-1.1 percent), Europe (-4.9 percent), Asia Pacific/All Other (-6.8 percent), and the Americas (-7.5 percent).

“As Congress returns to Washington this week, we urge policymakers to work together to advance initiatives that promote growth and innovation in the semiconductor industry and throughout the U.S. economy,” Neuffer said. “One such measure is the Trans-Pacific Partnership (TPP), a landmark agreement that would tear down barriers to trade with Pacific-Rim countries. Congress should do what’s right for U.S. businesses, consumers, and our economy and approve the TPP.”

To find out how to purchase the WSTS Subscription Package, which includes comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, please visit http://www.semiconductors.org/industry_statistics/wsts_subscription_package/.

July 2016 GSR table and graph

SEMI today announced that twenty-one start-ups have been selected to pitch to investors and exhibit their products at SEMICON Europa‘s INNOVATION VILLAGE in Grenoble, France at the Alpexpo from 25-27 October, 2016. INNOVATION VILLAGE will showcase never-before-seen technologies, with early stage companies introducing their technologies on the exposition floor.

INNOVATION VILLAGE, an area of more than 400m² on the SEMICON Europa exhibition floor, is dedicated to the launch and promotion of technological innovation.  Twenty-one leading European start-ups will be featured, including:

• 3Dis Technologies • HPROB • ProNT GmbH
• Antaios • Irlynx • Silicon Radar
• Applied Nanolayers BV • Madci • Siltectra
• Bright Red Systems Gmbh • Mi2-factory GmbH • Smart Force Technologies
• Fastree3D • Miniswys SA • Smoltek
• FlexEnable • Noivion • Solayl
• FMC – The Ferroelectric Memory Company • Pollen Metrology • Terabee

Start-ups will be given the opportunity to “pitch” their products to potential investors including Applied Ventures LLC, Samsung Ventures, TEL Venture Capital, Robert Bosch Venture Capital GmbH, 3M New Ventures, Aliad-Air Liquide Corporate Venture Capital, Capital ASTER, CEA Investment, VTT Ventures, Capital-E, Siemens Technology Accelerator GmbH and more.

For the first time at the INNOVATION VILLAGE, a new technology transfer program, called the TechnoMarket, from partner Linksium, SATT Grenoble Alpes will be showcased on 26 October. “The national network, SATT, has chosen SEMICON Europa to promote the best technological projects derived from public research within France that can also benefit manufacturers. The new Techno Market event offers new opportunities for businesses,” says Gilles Talbotier, CEO, Linksium.  The TechnoMarket acts as a genuine market place for VCs and companies ready to invest in innovation.

Free admission code: Use the promotional code SCEU-TBN4U to gain free admission to the show floor (not including conferences or forums).  Register now – attend to connect.

For more information about SEMICON Europa, please visit http://www.semiconeuropa.org

Asia-Pacific’s grip as the dominant market for IC sales is forecast to strengthen in 2016 with the region expected to account for 61.0% of the $282.0 billion IC market this year, based on analysis published in IC Insights’ mid-year Update to the 2016 IC Market Drivers report.  The forecast calls for another small gain in total IC marketshare in 2016 after Asia-Pacific held 57.7% share in 2013, 58.4% in 2014, and 60.5% in 2015. The Asia-Pacific region is particularly dominant with regard to IC marketshare in the communications and computer categories, and to a lesser extent in the consumer and industrial categories (Figure 1).  In 2016, IC Insights expects the Asia-Pacific region to surpass Europe and become the largest region for automotive ICs for the first time, as China continues to account for a large and growing portion of new car shipments.  That will leave only the Government/Military end use segment where Asia-Pacific does not have top IC marketshare—a condition that is forecast to hold through 2019.

Figure 1

Figure 1

IC Insights’ Update to the IC Market Drivers 2016 report forecasts total IC usage by system type through the year 2019. Highlights from the forecast include the following items.

– The Asia-Pacific region is forecast to increase its share of the IC market to 62.3% in 2019, from 61.0% forecast for 2016. Over the same time, North American is also forecast to increase marketshare to 23.8%. Conversely, Europe and Japan are expected to lose IC marketshare through 2019. Japan’s IC marketshare is forecast to slip to 5.5% and Europe is forecast to slide to 8.3% in 2019.

– The two fastest growing end-use markets for ICs through 2019 are forecast to be the automotive and industrial/medical segments, having 2015-2019 CAGRs of 8.0% and 7.1%, respectively.  Though having the greatest CAGR through 2019, the automotive IC market is not expected to account for more than 8.0% of total IC sales any time through the forecast period.

– After slumping to only $10.6 billion in 2009, the automotive IC market is forecast to reach nearly 3x that amount ($28.0 billion) in 2019.

– The two largest end-use markets (computer and communications) are forecast to account for 73.7% of the total IC market in 2019, almost the same as the 73.9% share they are forecast to hold in 2016.

– In 2016, analog ICs are forecast to account for the greatest share of IC sales within the automotive (45%) and industrial (50%) segments; logic devices are expected to account for the greatest share of IC sales in communications (41%), consumer (41%), and government/military (32%) applications, and microprocessors are forecast to account for the greatest share (42%) of IC sales in the computer segment.

Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, presented its highest honors Sept. 12 to professors from University of California, Berkeley and University of Minnesota at SRC’s annual TECHCON conference in Austin, Texas.

Dr. Tsu-Jae King Liu, TSMC Distinguished Professor in Microelectronics in the Department of Electrical Engineering and Computer Sciences(EECS) at UC Berkeley, received this year’s SRC Aristotle Award for outstanding teaching and a deep commitment to the educational experience of his students. With SRC support, Liu’s team at UC Berkeley has made numerous research contributions to the industry in areas including nanometer-scale semiconductor devices and technology, novel non-volatile memory devices and technology and M/NEMS technology for ultra-low-power integrated circuits.

Additionally, Dr. Chris Kim, a Professor in the Department of Electrical and Computer Engineering at Minnesota, was awarded the SRC Technical Excellence Award for his respective SRC-supported research and contributions to the industry in VLSI circuit design.

Selected by SRC member companies and SRC staff, the award-winning faculty and research teams are being recognized for their exemplary impact on semiconductor productivity through cultivation of technology and talent.

“Advanced research has been instrumental in propelling the semiconductor industry forward, and we are recognizing these valuable researchers and their teams for the critical work they have performed in helping the industry achieve technological triumphs,” said Ken Hansen, SRC CEO and President.

UC Berkeley and Minnesota research helps drive technology innovation

Dr. Liu, a member of the Kavli Energy NanoSciences Institute and Associate Dean of the College of Engineering at UC Berkeley, earned B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. Prior to joining UC Berkeley, she worked as a researcher at the Xerox Palo Alto Research Center. Dr. Liu’s current research activities include nanometer-scale logic and memory devices for energy-efficient electronics, and she currently leads research on millivolt nanomechanical switches under the NSF Center for Energy Efficient Electronics Science.

“I am very fortunate to have been able to work with many outstanding students during my career at UC Berkeley, and am humbled to receive this prominent recognition for our joint achievements,” said Dr. Liu. “SRC’s support has made it possible for us to make impactful contributions to society, for which I am very grateful.”

Dr. Kim, a recipient of the National Science Foundation’s CAREER award, received his B.S and M.S. degrees from Seoul National University and a Ph.D. from Purdue University. Prior to joining the University of Minnesota, he worked at Intel Corporation that also recognized him with an Intel Ph.D. Fellowship. His current research focuses on digital, mixed-signal and memory circuit design in advanced-CMOS and beyond-CMOS technologies.

“This award recognizes our group’s invention of a new class of compact on-chip sensors called “silicon odometers” that can accurately and efficiently measure circuit aging effects,” said Dr. Kim. “Over the span of several SRC projects, our team has experimentally demonstrated more than a dozen different odometer designs in technologies ranging from 130 to 32 nanometers.”

TECHCON showcases academia’s brightest

TECHCON brings together the brightest minds in microelectronics research to exchange news about the progress of research ranging from materials to architectures created by SRC’s network of more than 100 of the top engineering universities. Students and industry leaders discuss basic research that is intended to accelerate advancements for both private and public entities.

The presentation of the Aristotle and Technical Excellence awards reflects the purpose of TECHCON, which is to enable future generations of chip technology. The Aristotle Award is given to SRC-funded university faculty that have profoundly and continuously impacted their students’ professional performances in a way that provides long-term benefit to the SRC member companies. The Technical Excellence Awards recognize researchers who have made key contributions to technologies that significantly enhance the productivity of the semiconductor industry.

More than 12,000 students have been prepared by SRC programs, professors and mentors for entry into the semiconductor business. These students provide a path for technology transfer and a source of relevantly educated technical talent for the industry.

Lomonosov MSU physicists found a way to “force” silicon nanoparticles to glow in response to radiation strongly enough to replace expensive semiconductors used in display business. According to Maxim Shcherbakov, researcher at the Department of Quantum Electronics of the Moscow State University and one of the authors of the study, the developed method considerably enhances the efficiency of nanoparticle photoluminescence.

The key term in the problem is photoluminescence — the process, when materials irradiated by visible or ultraviolet radiation start to respond with their own light, but in a different spectral range. In the study, the material glows red.

In some of the modern displays, semiconductor nanoparticles, or the so-called quantum dots, are used. In quantum dots, electrons behave completely unlike those in the bulk semiconductor, and it has long been known that quantum dots possess excellent luminescent properties. Today, for the purposes of quantum-dot based displays various semiconductors are used, i.e. CdSe, etc. These materials are toxic and expensive, and, therefore, researchers have long been scrutinizing the far cheaper and much more studied silicon. It is also suitable for such use in all respects except one — silicon nanoparticles vaguely respond to radiation, which is not appealing for optoelectronic industry.

Scientists all over the world were seeking to solve this problem since the beginning of the 1990’s, but until now no significant success has been achieved in this direction. The breakthrough idea about how to “tame” silicon originated in Sweden, at the Royal Institute of Technology, Kista. A post-doctoral researcher Sergey Dyakov (a graduate of the MSU Faculty of Physics and the first author of the paper) suggested placing an array of silicon nanoparticles in a matrix with a non-homogeneous dielectric medium and cover it with golden nanostripes.

‘The heterogeneity of the environment, as has been previously shown in other experiments, allows to increase the photoluminescence of silicon by several orders of magnitude due to the so-called quantum confinement,’ says Maxim Shcherbakov. ‘However, the efficiency of the light interaction with nanocrystals still remains insufficient. It has been proposed to enhance the efficiency by using plasmons (quasiparticle appearing from fluctuations of the electron gas in metals — ed). Plasmon lattice formed by golden nanostripes allow to “hold” light on the nanoscale, and allow a more effective interaction with nanoparticles located nearby, bringing its luminescence to an increase.’

The MSU experiments with samples of “gold-plated” matrix with silicon nanoparticles made in Sweden brilliantly confirmed the theoretical predictions – the UV irradiated silicon for the first time shone bright enough to be used it in practice.

The first author of the paper Sergey Dyakov will present the findings on The 10th International Congress on Advanced Electromagnetic Materials in Microwaves and Optics (September 17-22, Crete). The work was also published in the Physical Review B (“Optical properties of silicon nanocrystals covered by periodic array of gold nanowires”).

An overview of liquid-to-liquid cooling systems and their operating principles

BY MARKO NIEMANN, Regional Sales Director, Laird Engineered Thermal Systems, Cologne, Germany

Cooling and temperature control systems are used throughout semiconductor fabrication facilities. In fabrication facilities both large and small, hundreds to thousands of cooling systems are installed and operate continuously. The processes employed are usually setup as copy-exact, which means the process systems are developed and transferred from the OEM of the process tool. These crtitical production tools used in a semiconductor fabrication facilities are required to be reliable and easy to service to deliver minimum downtime. The same is required of the cooling systems that support them. Usually the cooling systems employed have a water- cooled evaporator instead of an air-cooled evaporator. A liquid-liquid unit is quieter than a liquid to air unit because a fan is not required. Even more important, the heat can be rejected by available general facility cooling water and the heat is not rejected into the air temperature conditioned environment. These cooling systems can be placed near the tool, hidden in a false floor or on the lower level in a sub-floor. Cooling systems are built to meet SEMI S2 or F47 standards. OEM customers vary in their demand according to their unique requirements, but compliance is mandatory and sometimes OEM customers ask to get certifications for SEMI S2 or F47, which includes for example seismic “protections.” In these fabrication facilities a variety of liquid cooling systems are used including: compressor and thermoelectric based recirculating chillers.

Cooling systems

Liquid cooling systems are required to:

  • Protect the tool process against chemical reaction by avoiding an unknown Wetted-Parts-Material-Mix
  • Achieve a stable temperature, independent from facility water temperatures that can change
  • Achieve a temperature below or above the facility water temperature
  • Solve different temperature or fluid requirements at one tool with a multi-loop liquid cooling system

In semiconductor fabrication facilities, the required temperature control range varies from -80°C to +150°C. For the majority of applications, only one stable temperature set point is required. In the final chip test environment however, temperatures are required to vary in order to stress the chip. Here different temperature set points need to be reached with a single thermal management system. Due to the high-precision processes, tool manufacturers demand a very stable temperature environment. Typical of these requirements are +/-0.1K stability (e.g. for etching) to ±0.001K (e.g. for lithography) while cooling capacities can be up to several kilowatts.

In semiconductor fabrication facilities, custom multi- stage compressor based chillers are used to support cooling for very low temperature requirements. Most standard chillers utilized need some form of modification to meet semiconductor process facility requirements and may even require a water-cooled condenser. Some of the installation base also uses thermoelectric (19” rack) cooling systems, i.e. for etch applications, instead of compressor-based systems.

The cooling capacity demands and the range over which the system operates varies from a couple of hundred Watts (thermoelectric chiller and compressor based systems) to hundreds of Kilowatts (liquid-to-liquid cooling systems). The majority of the installed base uses liquid-to-liquid cooling systems that operate close to ambient and are based on a fluid-to-fluid heat-exchange principle.

The cooling systems utilize facility water to prevent heat dissipation of the cooling unit from warming the cleanroom and destabilizing the process tool’s thermal management system. These liquid-to-liquid systems keep the air quality level high by avoiding dust up introduced from the airflow of an air-to-air thermal management system. This consideration is independent of the location of the thermal management system. Due to the cyclic nature of the market, product requirements change and time to market is crucial. The cooling system solution developed is usually a custom product with a unique approach and design specific to the OEM.

Technical requirements

Cooling systems are often placed in the sub-fab, which means they are located one or two floors below the tool they are connected to. For cooling systems that use water as coolant, the height between the tool and the cooling system cannot exceed 10 meters, otherwise the height difference can cause the water to boil as the pressure is lower than the vapor pressure of water.
If the cooling system is placed at a lower level, the coolant circuit can function as a closed loop to the atmosphere. In this case, the cooling unit needs to incorporate a closed pressurized reservoir (7 PSI pressure cap) to minimize over flow conditions. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap (FIGURE 1).

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

A standpipe reservoir introduces additional fluid to the liquid circuit as required, whereas a flow-through reservoir continuously exchange fluid. It is important to know that the pump simply needs to overcome the height and pressure difference one-time during start-up in a closed loop system, as the supply and return lines will equilibrate given that they have the same length and diameter.

Material compatibility

In the semiconductor process environment, copper and brass are materials with limited compatibility due to their susceptibility to galvanic corrosion. Wetted parts, which come in direct contact with the medium (liquid), are typically made of stainless steel. These parts range from the complete plumbing circuit of the cooling unit to the process loop. Stainless steel is usually used in the process loop due its resistance to galvanic corrosion or because a special fluid is used that is not compatible with PVC, copper, and brass etc. When stainless steel is required, the heat exchanger, valves and the pumps will require special consideration. Occasionally, stainless steel may require additional passivation or a limited subset of stainless steel materials may be used.

If copper or brass is used to accomodate cost considerations, the material needs to be insulated to minimize the thermal impact on the system from outside thermal sources. Special particle free insulation may be required in this instance.

Special fluids used in the semiconductor environment include: di-electric fluids (Galden, 3M Novec), which are non-conductive. Special hoses and sealings need to be used for these fluids and special attention to handling is also required. These coolants run in a closed loop as the fluid vapor pressure is relatively low compared to water.

The use of de-ionized water is common. Copper or brass can be run up to 3 MOhm-cm resistivity if the set point temperature does not exceed 30°C for extended periods of time. However to ensure long lifetimes and for higher resistivity demands, the cooling system should be equipped with a nickel brazed or complete passivated stainless steel evaporator/heat-exchanger. The pumps should be stainless steel and all component parts in contact with the fluid should be made of passivated stainless steel to prevent corrosion. This is referred to as high-purity plumbing. In addition, a DI cartridge can be equipped with an indicator light or regulated through the cooling system and the DI level will be constantly measured and monitored keeping to a preset resistivity. The DI cartridge filters the ions out of the fluid and needs to be replaced to ensure its effectiveness.

Valves

If the unit is placed below the fabrication floor, an anti- siphoning package can be used to avoid backflow of the fluid and prevent overflowing the unit in event the pump stops. The anti-siphoning package consists of a one-way check valve in the supply line and normally open solenoid valves triggered by the unit in the return line. The solenoid valve would close in case the pump stops and the one-way check valve allows for the flow in only one direction. Instead of a one-way check valve, another solenoid valve can be used, though this depends on the flow rate and size (FIGURE 2).

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

For a process facility, constant monitoring and control of the facility process water is required and modulating solenoid valves from Siemens or Bellimo need to be used. The valve diameter and actuating motor have to be sized correctly to achieve stable temperatures and trigger the correct switching cycles. Assuring this means the inclusion of a long- lasting actuator and facility water flowing through an acceptable pressure drop from the facility water supply and return. Sometimes three-way mixing valves are used. This allows for continuous flow into the facility water loop and adds cooling for the heat exchanger of the thermal management system when required. The constant flow back to the facility water loop avoids a water hammer in cases where it would close and reopen when cooling is required. Flow requirements can go be as high as hundreds of liters per minute.

Space consideration

Cleanroom costs can be up to $60,000 /m2, therefore the chiller footprint is important and can have a costly impact. Semiconductor cooling systems should be stackable (stacked high) and preferable narrow to maximize space and minimize their impact on costs. Therefore the design of a cooling system’s footprint needs to be closely examined. The system should also be located where it is easy to access from two sides. Routine maintenance on cooling systems is required to exchange components such as pumps, motors, valves and fans to maximize system uptime.

SEMI requirements

For a completed tool, OEMs require a SEMI S2 certification and sometimes a Semi F-47 certification in areas with high earthquake probability. As the SEMI S2 certification requires a high amount of documentation, subsystems like a cooling unit will finally be integrated into the tool. Most of the time it is sufficient to meet the intent of SEMI S2 and the OEM will do a full certification of the final tool with all sincorporated subsystems in their NRTL laboratory. Below are some items to consider when designing a cooling unit to meet SEMI S2 and F-47 standards.

SEMI S2:

  • Drip tray must be large enough to hold 110% of the volume of the largest container in the cooling product
  • EMO button and/or EMO connection
  • Seismic brackets, seismic tie downs for standalone units
  • A specific power connection setup depending on the power consumption

F-47:

  • Continue to run during a power drop for a given time and fixed reduction of power

These requirements vary from customer to customer, but to some extent the certification is known to the manufacturer of the system.

If the unit is not placed below the fabrication facility flooring, the cooling system will instead be placed in the cleanroom or a grey room. Again, requirements here can vary drastically from customer to customer. If the cooling system, sub-assembly or any component is required to be in the cleanroom, then the entire assembly including each component must be as clean as possible. This requires the entire manufacturing process to have a high level of attention to cleanliness. Debris, dust, burrs or chips occurring at every process step need to be examined and removed ideally after every fabrication step. The industry is quite sensitive to this.

After the final assembly, the cooling unit needs to go through a manual check with UV-light and wipe down for final cleaning with gloves. The unit is then double bagged and each bag needs to be labeled appropriately. There are suppliers who specialize in cleaning, to semicon- ductor standards, and this can be subcontracted. Since it contributes to the cost and lead-time, the level of detail used requires scrutiny.

Service

Selling a cooling unit into the semiconductor market requires long-term servicing agreements in the contract. If a product is qualified in one facility other facilities can take over the setup as a copy exact requirement and use the existing cooling solution. For this after-market service and support, full understanding of the end users demands is critical. Service and support needs to responsive. In the event a tool unexpectedly goes down, immediate support is required or the OEM can lose millions of dollars in revenue.

Once the tool is installed service needs to be done on-site on the same day of failure, as large cooling systems cannot be replaced easily or shipped back to manufacturer for repair. OEMs have moved away from purchasing redundant cooling systems as their processes are getting leaner and expenses are reviewed more closely. This puts the contractual emphasis on service and a global service infrastructure.

Ideally the manufacturer is aware of the service demands and support strategy of their customers. Systems today are designed to minimize the downtime and make use of hot swappable parts, such as pumps on rails or modular exchange of complete assemblies, including electrical control boxes.

Conclusion

A semiconductor fabrication facility’s unique environment makes designing and building a liquid based cooling system one of the most challenging environments. Careful consideration is required not only for component selection, but also on the overall liquid cooling system unit and its integration with a semiconductor tool. Challenges designers face include the type of heat transfer mechanism utilized on the control and heat dissipation sides, material compat- ibility, valve control, cleanliness, space optimization, semi compliance and serviceability. These are all areas in need of attention to detail to properly ensure an optimized total cost of ownership.

Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES today announced that Synopsys has joined the foundry’s FDXcelerator Partner Program, an ecosystem designed to facilitate 22FDX system-on-chip (SoC) designs. This program enables designers to deploy Synopsys’ comprehensive RTL-to-GSDII solution with superior power and performance metrics for FDX-based designs. The collaboration accelerates the development of innovative products in applications spanning systems for intelligent clients, 5G connectivity, augmented and virtual reality and automotive.

Through the FDXcelerator Partner Program, Synopsys and GLOBALFOUNDRIES offer easy access to a complete 22FDX Reference Flow based on the Synopsys Galaxy Design Platform. This includes validated 22FDX “plug & play” support for tools, including Design Compiler, IC Compiler II, IC Validator, PrimeTime, StarRC, Custom Compiler, HSPICE and CustomSim solutions. The collaboration enables Synopsys’ tools to enhance support for differentiating GLOBALFOUNDRIES FD-SOI design features, including support for the adaptive body bias that unlocks FDX SoC performance and ultra-low-power operation, while lowering barriers of migration from bulk nodes. This allows engineers to create optimized designs, while minimizing development costs.

“Synopsys’ close collaboration with GLOBALFOUNDRIES provides designers access to a trusted EDA solution with advanced technical capabilities to address the requirements for developing differentiated FD-SOI-based designs,” said Bijan Kiani, vice president of product marketing for Synopsys’ Design Group. “We are helping designers adopt GLOBALFOUNDRIES’ innovative FDX offering by delivering comprehensive tools and methodologies to take advantage of the power, performance and cost advantages of the FDX technologies.”

“We are thrilled that Synopsys is an initial FDXcelerator partner,” said Alain Mutricy, senior vice president of Product Management at GLOBALFOUNDRIES. “Through this collaboration, our mutual customers can now take full advantage of the FDX value proposition by leveraging the validated Synopsys-based reference flow. The FDX-enabled Galaxy Design Platform will offer seamless support of body bias and other critical FDX performance management capabilities. The program will also enable access to Synopsys FDX EDA experts available for proactive training and support of mutual 22FDX design customers.”

With the recent announcement of the company’s next-generation 12FDX technology, the FDXcelerator Partner Program builds upon GLOBALFOUNDRIES’ industry-first FD-SOI roadmap, a lower-cost migration path for designers desiring advanced node design. By participating in FDXcelerator and continuing to invest in expanding the feature set of its tools to further support FDX customers, Synopsys is well positioned to participate in the adoption and growth of the FDX market. Moreover, the FDXcelerator Partner Program broadens the qualification and quality assurance collaboration between the companies, including tighter interlock around quality testing and methodology.

Additional Synopsys tools and features will be enhanced for FDX, and more information will be shared with the FDX design community in the months to come. Customers and partners interested in learning more about FDXcelerator can visit www.globalfoundries.com/fdxcelerator