Category Archives: Device Architecture

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry’s first multi-node FD-SOI roadmap. Building on the success of its 22FDX offering, the company’s next-generation 12FDX platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

As the world becomes more and more integrated through billions of connected devices, many emerging applications demand a new approach to semiconductor innovation. The chips that make these applications possible are evolving into mini-systems, with increased integration of intelligent components including wireless connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption. GLOBALFOUNDRIES’ new 12FDX technology is specifically architected to deliver these unprecedented levels of system integration, design flexibility, and power scaling.

12FDX sets a new standard for system integration, providing an optimized platform for combining radio frequency (RF), analog, embedded memory, and advanced logic onto a single chip. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate energy efficiency.

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

GLOBALFOUNDRIES’ new 12FDX technology is built on a 12nm fully-depleted silicon-on-insulator (FD-SOI) platform, enabling the performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET. The platform offers a full node of scaling benefit, delivering a 15 percent performance boost over today’s FinFET technologies and as much as 50 percent lower power consumption.

“Chip manufacturing is no longer one-shrink-fits-all. While FinFET is the technology of choice for the highest-performance products, the industry roadmap is less clear for many cost-sensitive mobile and IoT products, which require the lowest possible power while still delivering adequate clock speeds,” said Linley Gwennap, founder and principal analyst of the Linley Group. “GLOBALFOUNDRIES’ 22FDX and 12FDX technologies are well positioned to fill this gap by offering an alternative migration path for advanced node designs, particularly those seeking to reduce power without increasing die cost. Today, GLOBALFOUNDRIES is the only purveyor of FD-SOI at 22nm and below, giving it a clear differentiation.”

“When 22FDX first came out from GLOBALFOUNDRIES, I saw some game-changing features. The real-time tradeoffs in power and performance could not be ignored by those needing to differentiate their designs,” said G. Dan Hutcheson, chairman and CEO of VLSI Research. “Now with its new 12FDX offering, GLOBALFOUNDRIES is showing a clear commitment to delivering a roadmap for this technology — especially for IoT and Automotive, which are the most disruptive forces in the market today. GLOBALFOUNDRIES’ FD-SOI technologies will be a critical enabler of this disruption.”

“FD-SOI technology can provide real-time trade-offs in power, performance and cost for those needing to differentiate their designs,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ new 12FDX offering delivers the industry’s first FD-SOI roadmap that brings the lowest cost migration path for advanced node design, enabling tomorrow’s connected systems for Intelligent Clients, 5G, AR/VR, Automotive markets.”

GLOBALFOUNDRIES Fab 1 in Dresden, Germany is currently putting the conditions in place to enable the site’s 12FDX development activities and subsequent manufacturing. Customer product tape-outs are expected to begin in the first half of 2019.

“We are excited about the GLOBALFOUNDRIES 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

“NXP’s next generation of i.MX multimedia applications processors are leveraging the benefits of FD-SOI to achieve both leadership in power efficiency and scaling performance-on-demand for automotive, industrial and consumer applications,” said Ron Martino, vice president, i.MX applications processor product line at NXP Semiconductors. “GLOBALFOUNDRIES’ 12FDX technology is a great addition to the industry because it provides a next generation node for FD-SOI that will further extend planar device capability to deliver lower risk, wider dynamic range, and compelling cost-performance for smart, connected and secure systems of tomorrow.”

“As one of the first movers of design for FD-SOI, VeriSilicon leverages its Silicon Platform as a Service (SiPaaS) together with experience in delivering best-in-class IPs and design services for SoCs,” said Wayne Dai, president and CEO of VeriSilicon. “The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments. We look forward to extending our collaboration with GLOBALFOUNDRIES on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market.”

“12FDX development will deliver another breakthrough in power, performance, and intelligent scaling as 12nm is best for double patterning and delivers best system performance and power at the lowest process complexity,” said Marie Semeria, CEO of Leti, an institute of CEA Tech. “We are pleased to see the results of the collaboration between the Leti teams and GLOBALFOUNDRIES in the U.S. and Germany extending the roadmap for FD-SOI technology, which will become the best platform for full system on chip integration of connected devices.”

“We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering. Now this new 12FDX offering will further expand FD-SOI market adoption,” said Paul Boudre, Soitec CEO. “At Soitec, we are fully prepared to support GLOBALFOUNDRIES with high volumes, high quality FD-SOI substrates from 22nm to 12nm. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

The global high-tech engineering and construction company M+W Group has presented current and future trends, as well as state of the art solutions, for an integrated approach to waste reduction in order to improve the sustainability of semiconductor fabs. The presentation was held at the High-Tech Facility International Forum 2016 in Taipei on 8th September in conjunction with the Semicon Taiwan trade show.

Having successfully contributed to the forum’s widely recognized meetings over the past two years M+W Group was also invited to this year’s expert meeting on high- tech facilities. There, M+W Group leading experts presented the company’s solutions for an Integrated Waste Reduction Program for Semiconductor Facilities. It was emphasized that minimization of waste produced in semiconductor wafer fabs and other high-tech facilities begins during the buildings’ design and must focus on both the construction as well as the operational phases.

Drawing on its globally recognized experience, M+W Group outlined how sustainability in a semiconductor wafer fab can best be evaluated, monitored and optimized through the application of a holistic Life Cycle Assessment (LCA) tool that provides systematic evaluation of all environmental aspects of a wafer fab during their construction, operational lifetime and decommissioning.
Herbert Blaschitz, CEO of M+W Group’s Global Business Unit Advanced Technology Facilities, said “There is an ever-increasing interest in the industry to implement fully sustainable semiconductor wafer fab solutions. We at M+W Group have broad and successful experience in this field and are proud to be at the forefront of this development.”

About the High-Tech Facility International Forum: As part of SEMICON Taiwan the High- Tech Facility International Forum 2016 focuses on cost-efficient waste reduction for sustainable facilities. The forum builds a platform for major players in the high tech facility community to discuss latest trends, challenges and outstanding solutions for the Taiwanese high-tech industry. Other members besides M+W Group include TSMC, UMC (wafer fab foundries for Integrated Circuits (IC)), Macronix, Inotera (IC memory manufacturers), AUO, Chimei Innolux (flat panel display manufacturers), ASE, SPIL (IC assembly), Epistar (LED Manufacturer) and Motech (PV module manufacturer).

GLOBALFOUNDRIES today announced a new partner program, called FDXcelerator, an ecosystem designed to facilitate 22FDX system-on-chip (SoC) design and reduce time-to-market for its customers.

With the recent announcement of the company’s next-generation 12FDX™ technology, the FDXcelerator Partner Program builds upon GLOBALFOUNDRIES industry-first FD-SOI roadmap, a lower cost migration path for customers desiring advanced node design.

Together with GLOBALFOUNDRIES and FDXcelerator Partner solutions, customers will be able to build innovative 22FDX SoC solutions as well as ease migration to FD-SOI from bulk nodes such as 40nm and 28nm. Initial FDXcelerator Partners have committed a set of key offerings to the program, including:

  •  tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features,
  •  a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements,
  • platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX,
  • reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market,
  • resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology, and;
  • product packaging and test (OSAT) solutions.

“22FDX is increasingly gaining momentum as the platform of choice to build differentiated, highly-integrated system solutions,” said Alain Mutricy, senior vice president of Product Management at GLOBALFOUNDRIES.  “Now is the time to step up industry collaboration to enable our customers to accelerate adoption of 22FDX. FDXcelerator will extend the reach of the FD-SOI ecosystem by creating a market place for truly innovative FDX-tailored solutions and services.”

The FDXcelerator Partner Program creates an open framework to allow selected Partners to integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.

FD-SOI technology has been gaining ground as designers leverage the process as an alternative to Fin-FET-based technologies for chips that require performance on demand and energy efficiency at the lowest solution cost. According to a recent Linley Group Microprocessor Report, FD-SOI Offers Alternative to FinFET, GLOBALFOUNDRIES’ FDX technologies provide an alternative path for applications that cannot accept the cost and complexity of FinFETs.

Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semiconductor (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services. Additional FDXcelerator members will be announced in the following months.

SEMI today presented its industry leadership award for sustainable manufacturing to Po Wen Yen, CEO of United Microelectronics Corporation (UMC). Yen received theSEMI Sustainable Manufacturing Leadership Award – Inspired by Akira Inoue, at the Leadership Gala Dinner at SEMICON Taiwan 2016, the largest annual electronics manufacturing industry event in Taiwan.

“Yen exemplifies outstanding leadership and commitment to sustainable manufacturing issues. He approaches environmental protection in a holistic way, thinking broadly and then setting up the infrastructure to institutionalize the change while staying involved each step of the way,” said Denny McGuirk, president and CEO of SEMI. “This SEMI award for significant sustainable manufacturing achievement recognizes his status among a distinguished group of electronics industry executives.”

As CEO of UMC, Yen drove UMC to become a global leader in sustainable semiconductor manufacturing, emphasizing to his staff, customers, and suppliers, that “sustainable development is not only UMC’s vision but is also our core philosophy.” Yen also created a corporate structure where all sustainability-related goals and activities are overseen by a committee that he chairs, and then he reports these developments directly to the UMC Board of Directors.  Yen’s commitment has led to significant positive impacts on sustainable manufacturing at UMC. Yen’s specific accomplishments noted by the SEMI Award committee include:

Environmental Protection

  • Global Warming –To reduce energy use at UMC, Yen created and chairs an Energy Saving Committee, which reduced electrical power usage by 29,469 Mwh in 2014, which is the equivalent of removing 15,353 tons of CO2 from the atmosphere, and reduced natural gas usage by 11,979 Mwh, the equivalent to reducing 2,159 tons of CO2 emissions from being released into the atmosphere.
  • Water Resources – UMC maximizes water efficiency and promotes the importance of water resources and conservation. Total water recovery and reuse reached more than 180 percent of water intake for the calendar year 2015.
  • Green Manufacturing – UMC innovated corporate programs to manage hazardous substances and reduce pollution and waste during semiconductor manufacturing. UMC has a robust Hazardous Substance Process Management (HSPM) system in place that is certified by the International Electro-Technical Commission Quality Assessment System.
  • Green Buildings – UMC’s Fab 12A in the Tainan Science Park obtained both Taiwan’s Gold Certification for Green Buildings and LEED Gold Certification.
  • Green Products –To better evaluate the environmental impacts of products, UMC collaborated with the Industrial Technology Research Institute (ITRI) to implement a Life Cycle Assessment for each fab, improving its management processes and reducing resource consumption.


Community Service

  • Social Welfare – UMC encourages a culture of community volunteering with many programs. One example, “Spreading the Seeds of Hope,” has assisted over 6,000 children from disadvantaged families.
  • UMC Fire Brigade – Still the only corporation in Taiwan’s electronics industry to have its own fire department, UMC established its high-tech fire brigade more than 20 years ago. The fire brigade consists of 106 members, including 13 full-time employees and 93 voluntary firefighters.

The Sustainable Manufacturing Leadership Awardis sponsored by SEMI. The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of sustainable manufacturing in the semiconductor industry. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry who have made significant leadership contributions to reduce the environmental and social impacts of semiconductor manufacturing. Past Award recipients include: Mark Durcan (CEO, Micron), TY Chiu (CEO, SMIC), Ajit Manocha (CEO, GLOBALFOUNDRIES), and Morris Chang (CEO, TSMC).

SEMICON Taiwan will be held from September 7 to 9 at Taipei Nangang Exhibition Center, Hall 1. Upbeat about the growth prospects of Taiwan’s semiconductor sector, SEMICON Taiwan 2016 features 600 exhibitors covering over 1,600 booths,and is expected to attract more than 43,000 visitors in three days.

For the sixth consecutive year, Taiwan has been the largest consumer of semiconductor equipment due to its large foundry and advanced packaging capacity, totaling $9 billion in 2016 and expecting to grow to $10 billion in 2017, accounting for a quarter of the global market. According to the latest report from IEK, the total production value of Taiwan semiconductor industry is expected to reach $2.4 trillion, performing better than the global market with a growth rate of 7.2 percent.

SEMICON Taiwan 2016 adds new pavilions including Okinawa (Japan), Philippines, Singapore, and World of IoT, in addition to pavilions on Cross-Strait, Kyushu (Japan), German, Holland High Tech and Korea, plus theme pavilions of AOI, CMP, High-Tech Facility, Materials, Precision Machinery, Secondary Market, Smart Manufacturing and Taiwan Localization. The total of nine theme pavilions and the eight country/region pavilions will offer visitors the most up-to-date options of greatest diversity.

The ascending trends of the Internet of Things and the need for smaller and more powerful mobile devices and wearables have created limitless new opportunities for semiconductor industry. In response to these trends, SEMICON Taiwan 2016 features the World of IoT pavilion showing off the latest application products, but also includes 21 forums, inviting speakers from the industry and academia, including TSMC, UMC, ASE, SPIL, Amkor, Lam Research, TEL and more, to share their exclusive perspectives on topics including memory, advanced packaging, semiconductor materials, high-tech facility, IC design, MEMS, 2.5D/3D IC technology, embedded and wafer level technology, and sustainable supply chain management. The three-day program is expected to attract over 4,000 attendances, providing an ideal platform for information exchange.

Covering the hottest topics like smart manufacturing, high-tech facility, and materials, more than 50 presentations will be given on TechXPOT stages, providing not only the latest technology updates but also great opportunities to meet potential partners.  To connect the right people and facilitate collaboration, SEMICON Taiwan organizes a series of networking events, like the Materials, High-Tech Facility, and Smart Manufacturing Get Togethers and the Supplier Search Program, creating business opportunities.

Diverse show activities and services include:

  • Live Broadcasting: HD live streaming provides first-hand highlights of forums and events from each corner on big screen and Facebook.
  • SEMICON Taiwan App: Providing the most updated exhibition information along with personal assistance functions, the SEMICON Taiwan App allows a smarter and more convenient visiting experience.
  • Jing Jing Lucky Draw: One of the most anticipated show activities will give away Ninebot One E+, Kodak Pixpro SP360, HTC Vive, Irobot Roomba, and new-years-eve hotel coupon.

Terry Tsao, SEMI Taiwan president states, “For years, SEMICON Taiwan not only has successfully connected Taiwan with the global markets, but also has bridged healthy communication between the government and the industry. Through increasing diversity, we expect to see SEMICON Taiwan continue to play an important role in facilitating collaboration and integration, helping the Taiwan semiconductor industry remain in a leading position.”

For more information, visit www.semicontaiwan.org/en

Technavio analysts forecast the global radio frequency (RF) IC market to grow at a CAGR of nearly 12% during the forecast period, according to their latest report.

The research study covers the present scenario and growth prospects of the global RF IC market for 2016-2020. To calculate the market size, the report considers revenue generated from the shipment of RF ICs globally.

Asia-Pacific (APAC) is expected to be the major demand generating region and is expected to be the major contributor to the market during the forecast period. This is because of the growing demand for RF IC’s in the consumer electronics segment and increasing need for logic and multipoint control units (MCUs) in the automotive segment in the region. The presence of major buyers such as Samsung Electronics, LG Electronics, and Toyota Motor led to the increasing consumption of RF ICs in this region.

Increased demand for electronics from countries such as China and India drives the market in APAC. China’s massive demand for electronics exceeds the production levels in the country. Despite the phenomenal growth, only a small share of semiconductors’ demand in China is actually produced domestically.

Technavio hardware and semiconductor analysts highlight the following four factors that are contributing to the growth of the global RF IC market:

  • Deployment of next-generation LTE wireless networks
  • Advent of carrier aggregation
  • Use of new materials for manufacture of RF devices
  • Growing traction of RF technology for remotes

Deployment of next-generation LTE wireless networks

The increase in data consumption has resulted in the adoption of next-generation LTE networks such as 3G and 4G. The growing consumption has resulted in the growth of commercial networks, making LTE the fastest developing mobile technology. Though specific bands have been designated for LTE, they vary from carrier to carrier.

Sunil Kumar Singh, one of the lead embedded systems research analysts at Technavio, says, “LTE-based computing devices allow consumers to upload and download music and photographs, play games online with minimum signal interference, and watch online TV shows uninterrupted. This has created an opportunity for manufacturers of transceiver chips to offer solutions that address the consumer needs for faster and smoother access to mobile data.”

Advent of carrier aggregation

Carrier aggregation results in an increase in RF content in smartphones and tablets. Carrier aggregation combines a wide range of the available spectrum at the same time to increase download and upload speeds. Though carrier aggregation is not a widespread concept currently, it has already been implemented in South Korea.

“The RF signals are transmitted and received using transceiver chips, which are integrated into RF modules as a component. The advent of carrier aggregation will compel transceiver chip manufacturers to improve and upgrade their offerings according to the requirements of the OEMs,” adds Sunil.

Use of new materials for manufacture of RF devices

The manufacture of RF devices such as power amplifiers incurs huge costs for vendors because of the high cost of raw materials. This has resulted in vendors searching for new materials that can reduce the expenditure incurred in the manufacturing process of RF devices. The development of new materials such as GaAs and indium phosphide (InP) will ramp up the production of RF power amplifiers. GaAs-RF power amplifiers use high saturated electron velocity and electron mobility to function, especially at high frequencies.

The new materials display a superior level of integration with other electronic components such as switches being fabricated in silicon on sapphire or other silicon on insulator processes. While, SAW filters and duplexers are being fabricated with piezo-effective materials such as lithium tantalate and lithium niobate. Therefore, companies such as Murata and TriQuint are trying to use cost-effective and superior-performing materials to manufacture RF power amplifiers.

Growing traction of RF technology for remotes

RF remotes accounted for 13% of the global remote market in 2015 and are expected to witness increased adoption during the forecast period, accounting for a little more than 20% by 2020. One of the major factors contributing to it is the decrease in the development cost of RF technology-based products. Moreover, RF remotes are expected to gain traction in the market because of advantages compared with IR remotes. RF remotes have lower power consumption, longer range, and do not need line-of-sight to control the device.

The RF remotes segment will witness high demand considering the demand for advanced TVs such as 3D smart TVs and 4k UHD smart TVs. Consumers demand visually aesthetic TVs that deliver a unique experience in terms of picture quality, viewing angle, and internet connectivity. With such advanced features, remote manufacturers are also manufacturing advanced and sophisticated RF remotes. RF has benefits such as out-of-line and sight communication and control, two-way communication, incorporation of gesture recognition and voice controls, and enhanced bandwidth compared to IR.

The key vendors are:

  • Infineon Technologies
  • Qualcomm
  • Avago Technologies
  • Qorvo
  • Skywork Solutions
  • NXP Semiconductors
  • STMicroelectronics
  • Renesas Electronics

Last March, the artificial intelligence (AI) program AlphaGo beat Korean Go champion LEE Se-Dol at the Asian board game.

“The game was quite tight, but AlphaGo used 1200 CPUs and 56,000 watts per hour, while Lee used only 20 watts. If a hardware that mimics the human brain structure is developed, we can operate artificial intelligence with less power,” points out Professor YU Woo Jong.

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In the junctions (synapses) between neurons, signals are transmitted from one neuron to the next. TRAM is made by a stack of different layers: A semiconductor molybdenum disulfide (MoS2) layer with two electrodes (drain and source), an insulating hexagonal boron nitride (h-BN) layer and graphene layer. This two-terminal architecture simulates the two neurons that made up to the synaptic structure. When the difference in the voltage of the drain and the source is sufficiently high, electrons from the drain electrode tunnel through the insulating h-BN and reach the graphene layer. Memory is written when electrons are stored in the graphene layer, and it is erased by the introduction of positive charges in the graphene layer. CREDIT: IBS

In collaboration with Sungkyunkwan University, researchers from the Center for Integrated Nanostructure Physics within the Institute for Basic Science (IBS), have devised a new memory device inspired by the neuron connections of the human brain. The research, published in Nature Communications, highlights the devise’s highly reliable performance, long retention time and endurance. Moreover, its stretchability and flexibility makes it a promising tool for the next-generation soft electronics attached to clothes or body.

The brain is able to learn and memorize thanks to a huge number of connections between neurons. The information you memorize is transmitted through synapses from one neuron to the next as an electro-chemical signal. Inspired by these connections, IBS scientists constructed a memory called two-terminal tunnelling random access memory (TRAM), where two electrodes, referred to as drain and source, resemble the two communicating neurons of the synapse. While mainstream mobile electronics, like digital cameras and mobile phones use the so-called three-terminal flash memory, the advantage of two-terminal memories like TRAM is that two-terminal memories do not need a thick and rigid oxide layer. “Flash memory is still more reliable and has better performance, but TRAM is more flexible and can be scalable,” explains Professor Yu.

TRAM is made up of a stack of one-atom-thick or a few atom-thick 2D crystal layers: One layer of the semiconductor molybdenum disulfide (MoS2) with two electrodes (drain and source), an insulating layer of hexagonal boron nitride (h-BN) and a graphene layer. In simple terms, memory is created (logical-0), read and erased (logical-1) by the flowing of charges through these layers. TRAM stores data by keeping electrons on its graphene layer. By applying different voltages between the electrodes, electrons flow from the drain to the graphene layer tunnelling through the insulating h-BN layer. The graphene layer becomes negatively charged and memory is written and stored and vice versa, when positive charges are introduced in the graphene layer, memory is erased.

IBS scientists carefully selected the thickness of the insulating h-BN layer as they found that a thickness of 7.5 nanometers allows the electrons to tunnel from the drain electrode to the graphene layer without leakages and without losing flexibility.

Flexibility and stretchability are indeed two key features of TRAM. When TRAM was fabricated on flexible plastic (PET) and stretachable silicone materials (PDMS), it could be strained up to 0.5% and 20%, respectively. In the future, TRAM can be useful to save data from flexible or wearable smartphones, eye cameras, smart surgical gloves, and body-attachable biomedical devices.

Last but not least, TRAM has better performance than other types of two-terminal memories known as phase-change random-access memory (PRAM) and resistive random-access memory (RRAM).

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced more than a dozen semiconductor industry icons, leaders, and founders will come together at the annual SIA Award Dinner on Thursday, Nov. 10 in San Jose to celebrate the 25th anniversary of the Robert N. Noyce Award, the industry’s highest honor. Former Noyce Award recipients who will attend the event include Dr. Craig Barrett, Dr. Morris Chang, John Daane, Federico Faggin, Ted Hoff, Dr. John E. Kelly III, Stanley Mazor, Jim Morgan, Jerry Sanders, George Scalise, Mike Splinter, Ray Stata, Rich Templeton, and Pat Weber. The evening’s program will include a conversation with former Noyce recipients about the industry’s storied past and its tremendous promise for the future.

SIA previously announced Martin van den Brink, president and chief technology officer at ASML Holding and renowned pioneer in semiconductor manufacturing technology, will receive the 2016 Noyce Award. SIA presents the Noyce Award annually in recognition of a leader who has made outstanding contributions to the semiconductor industry in technology or public policy.

“Recipients of the Noyce Award represent the finest our industry has to offer, individuals who have shaped the trajectory of semiconductor technology and spurred groundbreaking innovations,” said John Neuffer, president and CEO, Semiconductor Industry Association. “This year we are privileged to present the 2016 Noyce Award to Martin van den Brink, a man whose career accomplishments have fundamentally transformed semiconductor manufacturing, and to do so with many former Noyce winners on hand. We look forward to this unique opportunity to celebrate the semiconductor industry alongside these legends in our industry and true trailblazers of modern technology.”

For information about the SIA Award Dinner, including tickets and sponsorship opportunities, please visit www.semiconductors.org.

By Paul Trio, SEMI

Growing Demands, Constraints Continue

For many years, the ATE industry has been challenged with controlling the cost of both production and development test by implementing innovative approaches and employing clever strategies (e.g., multi-site test implementation, DFT, etc.) to make “ends” meet, so to speak.  This predicament has been a perpetual struggle, but the industry manages to soldier on. However, the demands for next-generation technology continues to introduce new challenges to the ATE realm. For example, shorter production ramp-up and higher yields result in the increasing demand for test data and information in real-time. Not only is there a need for more data quickly, but also for better test data quality. Adding to the complexity is that existing formats are typically slow/limited or even proprietary. As a result, the equipment manufacturers are burdened with supporting multiple proprietary data transport and communications systems.  This requires the use of valuable engineering resources to develop and maintain these multiple proprietary systems, whereas a single standard system would open up resources to develop new ATE features and products.

ATE Industry Alliance

These ATE industry problems are being addressed by CAST – Collaborative Alliance for Semiconductor Test – a SEMI Special Interest Group (SIG). SEMI SIGs provide a forum that fosters discussion and aligns stakeholders on industry-critical issues. CAST was formed in 2008 by semiconductor device makers and test industry suppliers to engage in and resolve common industry issues related to higher test equipment utilization, lower costs, and greater return on investment. In 2009, CAST became a SEMI Special Interest Group. Its charter includes fostering pre-competitive collaboration as well as developing and promoting standards that enable industry productivity improvements.

Figure 1 CAST Industry Stakeholders

Figure 1 CAST Industry Stakeholders

CAST members include a range of semiconductor industry leaders, ranging from automated test equipment (ATE) companies to integrated device manufacturers (IDMs) to fabless manufacturers to outsourced semiconductor assembly and test (OSAT) companies. Companies participating in CAST include: Advantest, ASE, Galaxy Semiconductor, GLOBALFOUNDRIES, Infineon, Maxim, Nvidia, Optimal+, PDF Solutions, Qualcomm, Roos Instruments, STMicroelectronics, Teradyne, Tesec, Texas Instruments, Xcerra.

CAST Structure

The CAST organization is primarily comprised of a steering committee and two working groups. The CAST Steering Committee meets quarterly to review progress on programs and identify new solutions needed by the industry. The Steering Committee is comprised of decision-makers and strategic thinkers of the participating companies mentioned above.

The current CAST working groups that are addressing data transport and control are the Rich Interactive Test Database (RITdb) WG and the Tester Event Messaging for Semiconductor (TEMS) WG.

Figure 2 SEMI CAST Working Group Focus Areas

Figure 2 SEMI CAST Working Group Focus Areas

Enabling Adaptive Test through Next Generation Standard Test Data Format

While Standard Test Data Format (STDF) is widely used in the semiconductor industry today, its current specification does not directly support the new use models in today’s test environment, such as real time or pseudo real time queries, adaptive test and streaming access. The STDF V4 record format is not extendible and the specification itself can be imprecise, such that it tends to result in many interpretations. These limitations become apparent when there is a need for more efficient and flexible format to manage “big test data.”

The RITdb group has been working on the next generation format following STDF with more flexibility in data types as well as allowing support for adaptive test. The WG aims to provide a standards-driven data environment for semiconductor test including simple standards-based data capture, transport and relationship model for eTest, probe, and final test data. Their work also aims to support equipment configuration management and operational performance data. RITdb is a SQLite database with one table, independent from an operating system. Key value store optimized for test data.

Figure 3 STDF to RITdb: PTR

Figure 3 STDF to RITdb: PTR

To date, the group has defined the mapping from STDF v4 to RITdb. A translator developed by the RITdb is also available. The overall schema has already been defined and many file translations have already been tested. Work by the RITdb group will ultimately be developed into SEMI Standards. Therefore, the group has been working on the (SEMI Standard) spec which will be in MS Word, while the database itself will be in a different format. There will be a spec editor that will help ensure the spec is used correctly. The group also plans to expand the spec beyond probe and final test. Meanwhile, the group is working on experiments related to streaming RITdb as well as work on using different extensions (e.g., tester log, streaming). Additional work will be needed on probe maps as well as on doing test cases (i.e., be able to run verifiers to validate the spec).

Improving Test Yield through Common ATE Data Communication Interface

Semiconductor test operations involved in ATE today continues to see a surging demand for data for real-time data analysis and real-time ATE input and control of the test flow to improve test yield, throughput, efficiency, and product quality.  At the same time, test equipment and test operations around the world utilize a diverse range of data formats, specifications, and interface requirements that create significant customer service and application engineering costs for ATE vendors, OSAT companies, IDM test operations, software providers, and handler equipment. A common ATE hardware and software communications interface would help reduce the cost, time and complexity of integrating ATE equipment into data-intensive test operations.

The TEMS WG was chartered to develop a standardized ATE data messaging system based on industry standard internet communication protocols between a Test Cell host and a server.  The standard will be limited to ATE data messaging, using RITdb entity types, where applicable, as well as the standard data format, and control requirements. It will have no impact on other test communication interfaces such as those involving handlers, probers, test instrumentation, and other systems covered by existing standards (e.g., SEMI E30, E4, E5, STDF, etc.).

The group will essentially develop a set of standards to define a vendor neutral way to collect test cell data. The primary spec defines the Model while a subordinate spec defines the Transport layer to maintain consistency with prior standards.

Figure 4 TEMS Focus Area

Figure 4 TEMS Focus Area

Similar to the RITdb activity, the TEMS group plans to transition its two working documents to the SEMI Standards space. As the group continues to fine-tune these documents while maintaining alignment with the RITdb WG, the preliminary SEMI Standards work (e.g., authorize formation of corresponding task force) is expected to occur by the end of the year.

Other ATE Challenges Looming

System Level Test (SLT) is an approach used to guarantee the performance of a product for a particular customer application. However, the term “System Level Test” (SLT) is frequently applied to both the testing of full systems as well as to the testing of chips to ensure their ultimate performance in target systems. This often leads to confusion.

For its 2016 workshop to be held in early November, CAST will address the topic of “Component SLT”, which is the set of application-specific functional tests that are performed prior to I.C. shipment to guarantee a chip’s quality and performance when it will be ultimately used in the final system.  It may also encompass incoming inspection of I.C. components by customers prior to assembly into systems.  Currently, component SLT tends to be implemented primarily on complex SoC devices using custom hardware and software.

Component SLT considerations:

  • Normally component SLT would be applied using a card or board based on the target system’s functional card or board — but with a socket where the IC component is temporarily placed while SLT tests are applied.
  • Component SLT is used by some chip vendors as an IC component test after conventional Final Test on ATE.
  • Potentially, component SLT could also be applied using a custom card within the ATE system that mimics system application tests.
  • Any level of standardization will ease the capital burden and operational flexibility at OSATs.
  • It will be a key requirement to be able to generate data from component SLT that can be shared backwards and forwards along the semiconductor supply chain for yield optimization and quality/reliability management.

Those looking to share their perspectives on component SLT and their vision for its future direction are invited to present at the CAST workshop. The community is particularly interested in opportunities to improve the Component SLT ​infrastructure or methods — that is, identify potential opportunities for CAST to drive improvements through pre-competitive collaboration.

Participating in SEMI CAST Special Interest Group

The SEMI CAST Special Interest Group is open to all SEMI Members. For more information or to join CAST, please contact Paul Trio at SEMI ([email protected]).

SEMI announced today that the deadline for presenters to submit an abstract for the annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is October 17.  ASMC, which takes place May 15-18, 2017 in Saratoga Springs, New York, will feature technical presentations of more than 90+ peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, as well as educational tutorials.

ASMC, in its 28th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.  Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. In addition to publication in the ASMC proceedings, select papers will be invited to participate in a special section of ASMC 2017 to be featured in IEEE Transactions on Semiconductor Manufacturing. Technical abstracts are due October 17, 2016. 

This year SEMI (www.semi.org) is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:

  • Packaging and Through Silicon Via (3D/TSV)
  • Fabless Experience (FE)
  • Advanced Equipment Processes and Materials (AEPM)
  • Advanced Metrology
  • Advanced Patterning / Design for Manufacturability (AP/DFM)
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Defect Inspection and Reduction (DI)
  • Data Management and Data Mining Tools (DM)
  • Discrete Power Devices (DP)
  • Equipment Reliability and Productivity Enhancements (ER)
  • Enabling Technologies and Innovative Devices (ET/ID)
  • Factory Automation (FA)
  • Green Factory (GF)
  • Industrial Engineering (IE)
  • Lean Manufacturing (LM)
  • MOL and Junction Interfaces (MJ)
  • Smart Manufacturing (SM)
  • Yield Methodologies (YM)

Complete descriptions of each topic and author kit can be accessed at http://www.semi.org/en/node/38316.  If you would like to learn more about the conference and the selection process, please contact Margaret Kindling at [email protected] or call 1.202.393.5552.

Papers co-authored between device manufacturers, equipment or materials suppliers, and/or academic institutions that demonstrate innovative, practical solutions for advancing semiconductor manufacturing are highly encouraged.  To submit an abstract, click here.

Technical abstracts are due October 17, 2016.  To learn more about the SEMI Advanced Semiconductor Manufacturing Conference, visit http://www.semi.org/en/asmc2017.