Category Archives: Device Architecture

Microsemi Corporation (NASDAQ:  MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the production release of its Flashtec NVM Express (NVMe)2032 and NVMe2016 controllers, enabling the world’s leading enterprises and data centers to realize the highest performance solid state drives (SSDs) utilizing next-generation NAND technologies. Providing the highest capacity, performance and reliability to store critical data, the devices are the industry’s first SSD controllers to integrate DDR4 DRAM, alleviating bottlenecks and maximizing throughput.

“Microsemi is pleased to announce the production release of our second-generation Flashtec NVMe controllers, tuned for enterprise storage, server and data center workloads,” said Derek Dicker, vice president and business unit manager, performance storage, at Microsemi. “These controllers deliver world class performance, advanced low-density parity-check (LDPC) error correction suitable for managing next-generation 3D NAND, and a programmable architecture upon which SSD builders can develop custom firmware, providing developers the ultimate means of product differentiation.”

Microsemi’s second-generation Flashtec NVMe2032 and NVMe2016 controllers support the standard NVMe host interface and are optimized for high-performance 4KB random read/write operations, performing all flash management operations on-chip and consuming negligible host processing and memory resources. In addition, the controllers can achieve up to 1 million random read input/output operations per second (IOPS).

“We congratulate Microsemi on the production release of its second-generation NVMe 2032/2016 enterprise NVMe controller with a high-performance, flexible low-density parity-check engine,” said Eric Endebrock, vice president of Storage Marketing Micron. “These types of enabling technologies align to Micron’s 3D NAND needs which are focused on mission-critical and high performance workloads.”

Hyperscale and enterprise data centers continue adopting NVMe due to the high speed and low latency connection between SSDs and host processors, providing significant performance advantages over SAS and SATA. According to market research firm IDC’s report titled, “Worldwide Solid State Drive Forecast, 2015–2019,” the number of high-performance PCIe-based SSD units has an estimated compound annual growth rate of 44 percent from 2014-2019. As part of Microsemi’s broad Flashtec controller family, the NVMe2032 and NVMe2016 controllers cater to this growing demand for robust NVMe-based solutions, with the devices optimized for power efficiency while providing customers the highest levels of performance, data integrity and reliability.

In addition to the monthly Updates, IC Insights’ subscription to The McClean Report includes three “subscriber only” webcasts.  The first of these webcasts was presented on August 3, 2016 and discussed semiconductor industry capital spending trends, the worldwide economic outlook, the semiconductor industry forecast through 2020, as well as China’s failures and successes on its path to increasing its presence in the IC industry.

In total, IC Insights forecasts that semiconductor industry capital spending will increase by only 3% this year after declining by 2% in 2015.  However, driven by the top three spenders—Samsung, TSMC, and Intel—capital spending in 2016 is expected to be heavily skewed toward the second half of this year. Figure 1 shows that the combined 2016 outlays for the top three semiconductor industry spenders are forecast to be 90% higher in the second half of this year as compared to the first half.

Figure 1

Figure 1

Combined, the “Big 3” spenders are forecast to represent 45% of the total semiconductor industry outlays this year.  An overview of each company’s actual 1H16 spending and their 2H16 spending outlook is shown below.

Samsung — The company spent only about $3.4 billion in capital expenditures in 1H16, just 31% of its forecasted $11.0 billion full-year 2016 budget.

TSMC — Its outlays in the first half of 2016 were only $3.4 billion, leaving $6.6 billion to be spent in the second half of this year in order to reach its full-year $10.0 billion budget.  This would represent a 2H16/1H16 spending increase of 92%.

Intel — Spent just $3.6 billion in 1H16.  The company needs to spend $5.9 billion in the second half of this year to reach its current $9.5 billion spending budget, which would be a 2H16/1H16 increase of 61%.

In contrast to the “Big 3” spenders, capital outlays by the rest of the semiconductor suppliers are forecast to shrink by 16% in the second half of this year as compared to the first half.  In total, 2H16 semiconductor industry capital spending is expected to be up 20% over 1H16 outlays, setting up a busy period for the semiconductor equipment suppliers through the end of this year.

Further trends and analysis relating to semiconductor capital spending through 2020 are covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.

Mouser Electronics, Inc., the global authorized distributor with the newest semiconductors and electronic components, today announced the appointment of Sam Katsuta as Vice President of Mouser Electronics-Japan.

“Japan is a key global market as well as one of the world’s leading markets for electronic design, and is therefore of great interest to us,” said Mark Burr-Lonnon, Mouser’s Senior Vice President of APAC and EMEA Business. “With this in mind, we are establishing a Japanese company which Sam Katsuta will run within our global operation. The nuances of the Japan market call for a special model.”

Katsuta will assume full control of Mouser’s customer service, marketing and finance within Japan. He will work closely with Mouser’s manufacturer partners in Japan and will report directly to Burr-Lonnon.

Katsuta has had a long, exceptional career at TDK, where he most recently served as General Manager of Global Distribution for both high service and volume distribution. He earned a degree in Economics at Keio University in Japan before taking his first role with Mitsubishi Chemical Industries. He joined TDK in 1984.

“I have long been impressed with Mouser’s business model, and I am pleased now to be a part of the Mouser team as we launch this exciting new phase of Mouser’s Japan operation,” Katsuta said.

Mouser has seen solid customer growth in Japan — where it opened a customer service center last year in Tokyo — with customers purchasing online through its website, Mouser.com. The global distributor stocks semiconductors and electronic components authorized by more than 600 manufacturers, including the leading Japanese manufacturers Murata, Panasonic, Toshiba, Taiyo Yuden, TDK, ROHM, Hirose, Nichicon, and OMRON.

“We see Japan as a strong market for innovative technologies, and the significant growth of design engineers and small- to medium-sized production business fits perfectly with our business model,” Burr-Lonnon said. “We are prepared to strengthen our brand and presence in this key market and believe the expanded Japan operation will allow us to uniquely establish closer cooperation with Japanese manufacturers to penetrate their products into more designs globally via our platform.”

Mouser caters to design engineers and buyers by delivering What’s Next in advanced technologies. Mouser offers customers 22 global support locations and stocks the world’s widest selection of the latest semiconductors and electronic components for the newest design projects.

GLOBALFOUNDRIES announced that Wallace Pai has been appointed as vice president and general manager of China. Pai will be responsible for driving the company’s strategic direction in China as it expands its presence and customer base in the region.

Pai has more than two decades of experience in the semiconductor industry, with expertise in strategic planning, corporate development, marketing and ecosystem growth. Throughout his career as a senior executive at Motorola, Qualcomm, Samsung and Synaptics, he has shaped strategy and led numerous strategic initiatives and investments in China. He is fluent in Mandarin and Cantonese, and has extensive access to business networks throughout the Greater China region. Pai will be based primarily in Shanghai and will report to Mike Cadigan, senior vice president of global sales and business development.

“Greater China represents a multi-billion dollar market opportunity, with significant growth potential for GLOBALFOUNDRIES,” Cadigan said. “Wallace has the ideal background and expertise to help drive our strategy, working closely with our extensive sales and design resources in the region. As we build on this base with a planned manufacturing presence, we will be well positioned to serve customers in Greater China and beyond.”

Wallace joins GLOBALFOUNDRIES from Synaptics, where he was vice president and general manager for the touch and display business where he spent most of the time in Greater China, Korea and Japan. Prior to Synaptics, Pai served as vice president of corporate business development at Samsung, where he led strategic initiatives and investments for the mobile and semiconductor business. He came to Samsung from Motorola Mobility, where as corporate vice president he led corporate development and managed Motorola’s corporate venture fund, driving a number of strategic acquisitions and divestitures key to establishing the foundation and trajectory for the company. Before Motorola, Pai worked at Qualcomm in a number of leadership roles in global business development, product management and strategic planning.

Pai holds an MBA from Harvard Business School and an MSEE from the University of Michigan, Ann Arbor. Early in his career, Wallace was a consultant for McKinsey & Company and a microprocessor design engineer at Intel.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $79.1 billion during the second quarter of 2016, an increase of 1.0 percent over the previous quarter and a decrease of 5.8 percent compared to the second quarter of 2015. Global sales for the month of June 2016 reached $26.4 billion, an uptick of 1.1 percent over last month’s total of $26.1 billion, but down 5.8 percent from the June 2015 total of $28.0 billion. Cumulatively, year-to-date sales during the first half of 2016 were 5.8 percent lower than they were at the same point in 2015. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales increased slightly from Q1 to Q2 but remain behind the pace from last year, due largely to global economic uncertainty and sluggish demand,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales into Japan and China have been a bright spot midway through 2016, and a modest rebound in sales is projected during the second half of the year.”

Regionally, sales increased compared to June 2015 in China (1.7 percent), but fell in Asia Pacific/All Other (-11.0 percent), the Americas (-10.8 percent), Europe (-5.5 percent), and Japan (-1.3 percent). Sales were up slightly compared to last month in the Americas (3.0 percent), China (2.2 percent) and Europe (1.7 percent), but down somewhat in Japan (-1.0 percent) and Asia Pacific/All Other (-0.6 percent).

sales graph sales table

It is now feasible to make a prized material for spintronic devices and semiconductors — monolayer graphene nanoribbons with zigzag edges.

Miniscule ribbons of graphene are highly sought-after building blocks for semiconductor devices because of their predicted electronic properties. But making these nanostructures has remained a challenge. Now, a team of researchers from China and Japan have devised a new method to make the structures in the lab. Their findings appear in the current issue of Applied Physics Letters, from AIP Publishing.

“Many studies have predicted the properties of graphene nanoribbons with zigzag edges,” said Guangyu Zhang, senior author on the study. “But in experiments it’s very hard to actually make this material.”

Previously, researchers have tried to make graphene nanoribbons by placing sheets of graphene over a layer of silica and using atomic hydrogen to etch strips with zigzag edges, a process known as anisotropic etching. These edges are crucial to modulate the nanoribbon’s properties.

But this method only worked well to make ribbons that had two or more graphene layers. Irregularities in silica created by electronic peaks and valleys roughen its surface, so creating precise zigzag edges on graphene monolayers was a challenge. Zhang and his colleagues from the Chinese Academy of Sciences, Beijing Key Laboratory for Nanomaterials and Nanodevices, and the Collaborative Innovation Center of Quantum Matter teamed up with Japanese collaborators from the National Institute for Materials Science to solve the problem.

They replaced the underlying silica with boron nitride, a crystalline material that’s chemically sluggish and has a smooth surface devoid of electronic bumps and pits. By using this substrate and the anisotropic etching technique, the group successfully made graphene nanoribbons that were only one-layer thick, and had well-defined zigzag edges.

“This is the first time we have ever seen that graphene on a boron nitride surface can be fabricated in such a controllable way,” Zhang explained.

The zigzag-edged nanoribbons showed high electron mobility in the range of 2000 cm2/Vs even at widths of less than 10nm — the highest value ever reported for these structures — and created clean, narrow energy band gaps, which makes them promising materials for spintronic and nano-electronic devices.

“When you decrease the width of the nanoribbons, the mobility decreases drastically because of edge defects,” said Zhang. “Using standard lithography fabrication techniques, studies have seen mobility of 100 cm2/Vs or even lower, but our material still exceeds 2000 cm2/Vs even at the sub-10 nanometer scale, demonstrating that these nanoribbons are of very high quality.”

In future studies, extending this method to other kinds of substrates could enable the quick large scale processing of monolayers of graphene to make high-quality nanoribbons with zigzag edges.

Researchers from Moscow Institute of Physics and Technology (MIPT), Skolkovo Institute of Science and Technology (Skoltech), the Technological Institute for Superhard and Novel Carbon Materials (TISNCM), the National University of Science and Technology MISiS (Russia), and Rice University (USA) used computer simulations to find how thin a slab of salt has to be in order for it to break up into graphene-like layers. Based on the computer simulation, they derived the equation for the number of layers in a crystal that will produce ultrathin films with applications in nanoelectronics. Their findings were in The Journal of Physical Chemistry Letters (which has an impact factor of 8.54).

Transition from a cubic arrangement into several hexagonal layers. Credit: Authors of the study

Transition from a cubic arrangement into several hexagonal layers. Credit:
Authors of the study

From 3D to 2D

Unique monoatomic thickness of graphene makes it an attractive and useful material. Its crystal lattice resembles a honeycombs, as the bonds between the constituent atoms form regular hexagons. Graphene is a single layer of a three-dimensional graphite crystal and its properties (as well as properties of any 2D crystal) are radically different from its 3D counterpart. Since the discovery of graphene, a large amount of research has been directed at new two-dimensional materials with intriguing properties. Ultrathin films have unusual properties that might be useful for applications such as nano- and microelectronics.

Previous theoretical studies suggested that films with a cubic structure and ionic bonding could spontaneously convert to a layered hexagonal graphitic structure in what is known as graphitisation. For some substances, this conversion has been experimentally observed. It was predicted that rock salt NaCl can be one of the compounds with graphitisation tendencies. Graphitisation of cubic compounds could produce new and promising structures for applications in nanoelectronics. However, no theory has been developed that would account for this process in the case of an arbitrary cubic compound and make predictions about its conversion into graphene-like salt layers.

For graphitisation to occur, the crystal layers need to be reduced along the main diagonal of the cubic structure. This will result in one crystal surface being made of sodium ions Na? and the other of chloride ions Cl?. It is important to note that positive and negative ions (i.e. Na? and Cl?)–and not neutral atoms–occupy the lattice points of the structure. This generates charges of opposite signs on the two surfaces. As long as the surfaces are remote from each other, all charges cancel out, and the salt slab shows a preference for a cubic structure. However, if the film is made sufficiently thin, this gives rise to a large dipole moment due to the opposite charges of the two crystal surfaces. The structure seeks to get rid of the dipole moment, which increases the energy of the system. To make the surfaces charge-neutral, the crystal undergoes a rearrangement of atoms.

Experiment vs model

To study how graphitisation tendencies vary depending on the compound, the researchers examined 16 binary compounds with the general formula AB, where A stands for one of the four alkali metals lithium Li, sodium Na, potassium K, and rubidium Rb. These are highly reactive elements found in Group 1 of the periodic table. The B in the formula stands for any of the four halogens fluorine F, chlorine Cl, bromine Br, and iodine I. These elements are in Group 17 of the periodic table and readily react with alkali metals.

All compounds in this study come in a number of different structures, also known as crystal lattices or phases. If atmospheric pressure is increased to 300,000 times its normal value, an another phase (B2) of NaCl (represented by the yellow portion of the diagram) becomes more stable, effecting a change in the crystal lattice. To test their choice of methods and parameters, the researchers simulated two crystal lattices and calculated the pressure that corresponds to the phase transition between them. Their predictions agree with experimental data.

Just how thin should it be?

The compounds within the scope of this study can all have a hexagonal, “graphitic”, G phase (the red in the diagram) that is unstable in 3D bulk but becomes the most stable structure for ultrathin (2D or quasi-2D) films. The researchers identified the relationship between the surface energy of a film and the number of layers in it for both cubic and hexagonal structures. They graphed this relationship by plotting two lines with different slopes for each of the compounds studied. Each pair of lines associated with one compound has a common point that corresponds to the critical slab thickness that makes conversion from a cubic to a hexagonal structure energetically favourable. For example, the critical number of layers was found to be close to 11 for all sodium salts and between 19 and 27 for lithium salts.

Based on this data, the researchers established a relationship between the critical number of layers and two parameters that determine the strength of the ionic bonds in various compounds. The first parameter indicates the size of an ion of a given metal–its ionic radius. The second parameter is called electronegativity and is a measure of the ? atom’s ability to attract the electrons of element B. Higher electronegativity means more powerful attraction of electrons by the atom, a more pronounced ionic nature of the bond, a larger surface dipole, and a lower critical slab thickness.

And there’s more

Pavel Sorokin, Dr. habil., is head of the Laboratory of New Materials Simulation at TISNCM. He explains the importance of the study, ‘This work has already attracted our colleagues from Israel and Japan. If they confirm our findings experimentally, this phenomenon [of graphitisation] will provide a viable route to the synthesis of ultrathin films with potential applications in nanoelectronics.’

The scientists intend to broaden the scope of their studies by examining other compounds. They believe that ultrathin films of different composition might also undergo spontaneous graphitisation, yielding new layered structures with properties that are even more intriguing.

By Yoichiro Ando, SEMI Japan

The 2016 global semiconductor market is forecast to decrease by 2.4 percent from the previous year according to the World Semiconductor Trade Statistics (WSTS). SEMI forecasts that the global semiconductor manufacturing equipment market will be effectively flat this year. However, SEMI also forecasts double-digit growth in 2017 with significant new fab construction starts in 2016 and 2017 that will drive later equipment. The forecast foresees the Japan market will shrink through 2017. This article provides insight behind those forecast numbers.

Overview

Large-scale investments in 300mm wafer lines in Japan are primarily made by three companies: Toshiba (NAND Flash), Sony (image sensors) and Micron Memory Japan (DRAM). The logic players’ investments are largely for upgrading and expanding existing capacity; the companies producing power, surface acoustic wave (SAW), and automotive semiconductor devices are actively adding capacity by constructing new fabs and expanding existing fabs. These activities are planned on 200mm or smaller wafers, so the investments are smaller in terms of dollar values. However, they are important to Japan’s semiconductor industry in the coming Internet of Things (IoT) age.

Toshiba plans a new mega fab

Toshiba continues to expanding its 300 mm NAND fabs in Yokkaichi in 2015 and 2016 ─ including the second phase construction of Fab 5, new Fab 2 for 3D NAND flash memory production, and plan for a new fab (Fab 6).

Toshiba New Fab 2

Toshiba’s new Fab 2 cleanroom (Source: Toshiba)

The new Fab 6 will be dedicated to 3D NAND flash memory production, and is planned to be built in an adjacent area of the current Yokkaichi factory site. Detailed plans of the construction (such as construction period, production capacity, and investment to manufacturing instrument used) will be decided in FY 2016 based on market trends. Fab 6 is expected to be built in FY 2017. Production capacity of the fab is projected to be more than 200,000 wafers per month (300mm wafers) at full capacity.

Toshiba and Western Digital announced a plan in July 2016 to invest a total of 1.5 trillion JPY for the next three years in Yokkaichi operations. This investment will be for the construction of the new fab as well as for updating equipment for existing fabs such as new Fab 2 and Fab 5.

Sony expands 300mm capacity

Sony is also actively expanding its 300mm wafer fabs for increased production of complementary metal-oxide-semiconductor (CMOS) image sensors. Sony plans to expand production capacity not only with its existing lines but also to acquire fabs from other companies. Specifically, Sony acquired Tsuruoka factory in Yamagata prefecture in 2014 from Renesas Electronics Corporation, and it is now operated as Yamagata Technology Center (TEC) of Sony Semiconductor Manufacturing Corporation, which is a semiconductor production subsidiary of Sony Corporation. In 2015, Sony acquired the 300mm line of the Toshiba Oita factory, for production of CMOS image sensors.

Sony plans to invest 70 billion JPY in FY 2016, and expand image sensor production capacity ─ now 70,000 wafers per month as of first quarter of 2016. The restoration of Kumamoto TEC damaged by the Kumamoto earthquake would make investment in other TECs decrease.

Micron and TowerJazz

Micron Technology operates a 300mm fab in Hiroshima (Micron Memory Japan Fab 15). The fab manufactures DRAM with 12nm process technology. Micron invested US$750 million in 2015 and $500 million in 2016 for the technology upgrades. The capacity has been flat in these two years.

Panasonic TowerJazz Semiconductor, a Panasonic and TowerJazz joint venture, operates a 300mm foundry fab in Uozu. The company invested $10 million in 2015 and plans to invest the same amount in 2016 to improve the productivity.

Investments in 200mm and smaller wafer lines

Other major semiconductor manufacturers primarily invest in existing fabs and lines for maintenances and productivity improvements. Therefore, investment amount is modest. However, these fabs will be the major source for semiconductor devices of the Internet of Things applications.

  • Renesas Electronics Corporation plans upkeep of production capacity of Kumamoto fab (200mm wafer fab) and Naka fab (300mm wafer fab).
  • Fujitsu enhances Fab B2 of Mie Fujitsu Semiconductor Limited, which provides foundry services with 300mm wafer lines. Taiwan’s major foundry UMC participated in capital of Mie Fujitsu Semiconductor Limited, and assists with 40nm process technology.
  • Rohm Co., Ltd. plans to invest more than 10 billion JPY in enhancement of 200mm lines of fab and others in the headquarters.
  • Fuji Electric Co., Ltd. continues enhancement of its 200mm wafer lines for IGBT of Yamanashi plant in FY 2016. Fuji Electric further expands its SiC power device production capacity by enhancing 200mm wafer lines at Matsumoto fab.
  • Mitsubishi Electric Corporation manufactures power devices at 200mm wafer line of Kumamoto fab. Mitsubishi Electric continues enhancement of power device production capacity.
  • Shindengen Electric Manufacturing Co., Ltd. is enhancing its power semiconductor module production by adding a new line each for Akita Shindengen Co., Ltd. and Higashine Shindengen Co., Ltd. from FY 2015.

Electronic Parts and Optoelectronic Devices

The electronic parts companies are emerging as new fab owners in Japan. Their recent activities are summarized below:

  • New Japan Radio Co., Ltd. continues enhancement of production capacity of SAW devices and GaAs ICs at its Kawagoe fab in 2016.
  • Hamamatsu Photonics K.K. continues enhancement of MEMS fabrication facility (Fab 13) which started operation in March 2014.
  • Upkeep of new clean room of Toyota Motor Corporation, which started operation in 2014, is now underway. Currently, this line is used for research and development, and trial production of SiC devices.
  • Murata Manufacturing Company, Ltd. is building a new fab for SAW filter production at its headquarter factory in Toyama. The new fab construction will be completed in September 2016. Total investment to the facility is planned to be 12 billion JPY. Then it will be equipped with 200 mm (mostly secondary) equipment.
  • Taiyo Yuden Co., Ltd. continues its enhancement plan of Oume fab in FY 2016, which was acquired from Hitachi in 2013 for SAW device production.
  • TDK agreed to acquire 125mm wafer lines in Tsuruoka Factory from Renesas Electronics Corporation in November 2015. TDK plans to enhance its production capacity of super miniature electronic components at this plant. Production will start in FY 2016 after replacement of manufacturing equipment to conform to products to be manufactured. Investment will continue in FY 2016 as well for startup of the mass production and maintenance at this plant.

SEMI World Fab Forecast

To obtain line-by-line investment and capacity trends in Japan and other regions in the world, SEMI Fab Forecast is a powerful and affordable tool. The report is in easy to use, with Excel spreadsheet format that covers six quarters of actual data and six quarters of forecast on over 1,000 fab/lines. For further information, please see www.semi.org/en/MarketInfo/FabDatabase.

Connect with Japan Semiconductor Industry at SEMICON Japan
SEMICON Japan (December 14-16, Tokyo) offers excellent opportunities to interact and connect with the Japan semiconductor industry. To join the exhibition, please see www.semiconjapan.org/en/exhibit.

Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production (Figure 1).  It has oftentimes been quoted over the last couple of years that China’s imports of semiconductors exceeds that of oil.

In its upcoming Mid-Year Update to The McClean Report 2016 (released at the end of this week), IC Insights examines the “Three-Phase” history of China’s attempt at strengthening its position in the IC industry that started in earnest in the late 1990s (Figure 2).

Figure 1

Figure 1

Figure 2

Figure 2

In the late 1990s, China began to contemplate ways to grow its indigenous IC industry and assisted in creating Hua Hong NEC, which was founded in 1997 as a joint venture between Shanghai Hua Hong and Japan-based NEC (it merged with Grace in 2011).  Then, as part of the country’s 10th Five Year Plan (2000-2005), establishing a strong China-based IC foundry industry became a priority.  As a result, pure play foundries SMIC and Grace (now Hua Hong Semiconductor) were both founded in 2000 and XMC was founded in 2006.  This effort is categorized by IC Insights as Phase 1 of China’s IC industry strategy.

In the early 2000s, to help boost the sales of its indigenous foundries, as well as ride the strong wave of fabless IC supplier growth, the Chinese government began attempts to foster a positive environment for the creation of Chinese fabless companies. It should be noted that eight of the current top 10 Chinese fabless IC suppliers were started between 2001 and 2004 and seven of them were in the top 50 worldwide ranking of fabless IC companies last year. This stage of China’s IC industry strategy is labeled by IC Insights as Phase 2.

IC Insights believes that Phase 3 of China’s attempt at creating a strong China-based IC industry began in 2014, just before the start of its 13th Five Year Plan which runs from 2015 through 2020.  As discussed in detail in the Mid-Year Update, this Phase is being supported by a huge “war chest” of cash that is intended to be used to purchase IC companies and their associated intellectual property, provide additional funding to China’s existing IC producers (e.g., SMIC, Grace, XMC, etc.), and to help establish new IC producers (e.g., Sino King Technology, Fujian Jin Hua, etc.).

In 1Q16, the U.S. Department of Commerce slapped an export ban on U.S. IC suppliers’ shipments of ICs to China-based telecom giant ZTE in response to the company allegedly shipping telecommunications equipment to Iran while it was under trade sanctions by the U.S. This ban, if fully enacted, would have a devastating effect on ZTE’s telecom equipment sales (including mobile phones). Thus far, the export ban has been postponed until August 30, 2016 pending further investigation by the U.S. Department of Commerce.

The situation regarding ZTE and the abrupt announcement earlier this year of export controls on the company by the U.S. government sent shock waves throughout the Chinese government as well as China’s electronic system manufacturers.  At this point in time, such potentially drastic measures taken by the U.S. government against such a large Chinese electronics company has bolstered the Chinese government’s resolve to make China more self-sufficient regarding IC component production, spurring increased emphasis on “Phase Three.”

Smaller and faster has been the trend for electronic devices since the inception of the computer chip, but flat transistors have gotten about as small as physically possible. For researchers pushing for even faster speeds and higher performance, the only way to go is up.

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

University of Illinois researchers have developed a way to etch very tall, narrow finFETs, a type of transistor that forms a tall semiconductor “fin” for the current to travel over. The etching technique addresses many problems in trying to create 3-D devices, typically done now by stacking layers or carving out structures from a thicker semiconductor wafer.

“We are exploring the electronic device roadmap beyond silicon,” said Xiuling Li, a U. of I. professor of electrical and computer engineering and the leader of the study. “With this technology, we are pushing the limit of the vertical space, so we can put more transistors on a chip and get faster speeds. We are making the structures very tall and smooth, with aspect ratios that are impossible for other existing methods to reach, and using a material with better performance than silicon.”

The team published the results in the journal Electron Device Letters.

Typically, finFETs are made by bombarding a semiconductor wafer with beams of high-energy ions. This technique has a number of challenges, Li said. For one, the sides of the fins are sloped instead of straight up and down, making them look more like tiny mountain ranges than fins. This shape means that only the tops of the fins can perform reliably. But an even bigger problem for high-performance applications is how the ion beam damages the surface of the semiconductor, which can lead to current leakage.

The Illinois technique, called metal-assisted chemical etching or MacEtch, is a liquid-based method, which is simpler and lower-cost than using ion beams, Li said. A metal template is applied to the surface, then a chemical bath etches away the areas around the template, leaving the sides of the fins vertical and smooth.

“We use a MacEtch technique that gives a much higher aspect ratio, and the sidewalls are nearly 90 degrees, so we can use the whole volume as the conducting channel,” said graduate student Yi Song, the first author of the paper. “One very tall fin channel can achieve the same conduction as several short fin channels, so we save a lot of area by improving the aspect ratio.”

The smoothness of the sides is important, since the semiconductor fins must be overlaid with insulators and metals that touch the tiny wires that interconnect the transistors on a chip. To have consistently high performance, the interface between the semiconductor and the insulator needs to be smooth and even, Song said.

Right now, the researchers use the compound semiconductor indium phosphide with gold as the metal template. However, they are working to develop a MacEtch method that does not use gold, which is incompatible with silicon.

“Compound semiconductors are the future beyond silicon, but silicon is still the industry standard. So it is important to make it compatible with silicon and existing manufacturing processes,” Li said.

The researchers said the MacEtch technique could apply to many types of devices or applications that use 3-D semiconductor structures, such as computing memory, batteries, solar cells and LEDs.