Category Archives: Device Architecture

Semiconductor Manufacturing International Corporation, one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, announces that the Snapdragon 425 processor and MDM9x07 has passed customer qualification and begun mass production in Beijing, after the successful technology transfer from SMIC’s Shanghai 12-inch fab to SMIC’s majority owned joint venture fab in Beijing. The successful production of 28nm Snapdragon products in Beijing represents an important step for SMIC’s 28nm technology.

This achievement is a result of close collaboration between Qualcomm and SMIC’s Beijing and Shanghai teams. SMIC’s successful 28nm production demonstrates its continued leadership in Mainland China and enhanced global competitiveness in advanced node technology.

The Qualcomm Snapdragon 425 processor is redefining the entry-point of mid-tier processors. With 802.11ac Wi-Fi, a 64-bit CPU, and a 16 megapixel dual image sensor processor, the Snapdragon 425 is making cutting-edge experiences more accessible with advanced computing, smooth graphics and remarkable camera quality. SMIC’s Beijing fab is located in the Beijing Economic Development Zone and is capable of manufacturing 28nm and above process technology nodes.

“The successful mass production of Snapdragon 28nm in the Beijing fab represents a major achievement for SMIC in expanding our production at 28nm,” said Dr. Haijun Zhao, Chief Operating Officer and Executive Vice President of SMIC. “Through parallel production of 28nm at both Shanghai and Beijing fabs, SMIC is able to expand our 28nm services to Qualcomm and global customers and to continue our progress in advanced node technology production.”

Mentor Graphics Corp. today announced that MagnaChip Semiconductor Corp., a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products for high-volume consumer applications, has selected the Mentor Analog FastSPICE (AFS) Platform for circuit verification and device noise analysis of their analog and mixed-signal designs including display drivers, power management ICs, and PLLs.

“We needed to reduce our long circuit simulation time and include device noise analysis in our analog and mixed-signal circuit verification flow,” said Dr. Kihyun Kim, senior manager, Design Technology at MagnaChip. “We selected the AFS Platform because it demonstrated SPICE accurate results 2.5x-4x faster than our existing parallel SPICE simulator in multiple analog circuits.”

The AFS Platform provides the world’s fastest circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. Foundry certified by the world’s leading foundries and IDMs, the AFS Platform delivers nanometer SPICE accuracy 5x-10x faster than traditional SPICE and 2x-6x faster than parallel SPICE simulators. For large circuits the AFS Platform delivers greater than 20M element capacity and the fastest mixed-signal simulation. For memory and other array-based circuits, AFS Mega delivers silicon-accurate simulation with greater than 100M element capacity. For silicon-accurate characterization it includes the industry’s only comprehensive full-spectrum device noise analysis and a high-productivity Analog Characterization Environment product —both of which deliver 5x-10x speedup over alternative approaches.

“We are very pleased that MagnaChip Semiconductor Corporation has selected the Analog FastSPICE Platform for circuit verification and device noise analysis of their analog and mixed-signal designs,” said Ravi Subramanian, general manager of AMS products in the DSM division, Mentor Graphics. “MagnaChip offers one of the broadest and deepest analog and mixed-signal semiconductor technology platforms in the industry and we are delighted to be one of their essential partners.”

POET Technologies Inc., a developer of opto-electronics fabrication processes for the semiconductor industry, today announced the completion of its previously announced acquisition of all of the shares of BB Photonics Inc. (“BB Photonics”), a private designer of integrated photonic solutions for the data communications market. POET completes the transaction owning 100% of BB Photonics and its assets, including intellectual property and technologies.  BB Photonics had no liabilities at Closing.

BB Photonics, a pre-revenue, New Jersey-based privately held company develops photonic integrated components for the datacenter market utilizing embedded dielectric technology that is intended to enable on-chip athermal wavelength control and lower the total solution cost of datacenter photonic integrated circuits. This strategic acquisition is designed to provide POET with additional differentiated intellectual property and know-how for product development, enable POET to better service its first identified commercialization market – the end-to-end data communications market – and augment its sensing roadmap.

“The addition of BB Photonics significantly enhances our integrated photonic solution set and advances our commercialization initiative,” said Dr. Suresh Venkatesan, POET’s Chief Executive Officer. “By internal development and acquisition, we are accelerating our drive from technology leadership to market entry in differentiated photonics.”

The POET platform and process technology continue to be the focal point of the Company’s commercialization strategy.  To this end, the POET team continues to make progress toward its previously announced goal of demonstrating an integrated product prototype by the end of 2016 using the POET platform.  POET’s recent acquisitions and organic development are meant to serve as a logical continuum of the roadmap by enabling immediate market entrance into its first identified commercialization market – data communications. The acquisitions also allow the Company to engage prospective customers with an extensive suite of integrated photonics products, thereby enabling multiple differentiated product sales and enhancing potential revenue.

POET acquired 100% of the shares of BB Photonics in consideration of the issuance of 1,996,090 common shares from POET’s treasury for a total deemed purchase price of US $1,550,000 in this stock only transaction, based on a price of the US equivalent of $1.00 per share.

Power transistors—the $12 billion growth engine in the $21 billion discrete semiconductor market—have faced a choppy uphill climb since surging in the 2010 recovery from the 2008 2009 economic recession. Worldwide revenues for power transistors continue to increase by a compound annual growth rate (CAGR) of about 4%, but sales in the largest discretes product category have fallen in three out of the last five years because of ongoing economic uncertainty and quick cancellation of purchase orders by systems makers whenever they see signs of demand weakening for end-use electronic products, says IC Insights’ 2016 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes.

After dropping 7% in 2015 to $12.3 billion, power transistor sales are expected to stabilize and begin a modest recovery in 2016, growing by a little over 1% to $12.4 billion, according to the latest edition of IC Insights’ annual O-S-D Report, which contains a detailed five-year forecast of sales, unit shipments, and average selling prices (ASPs) for more than 30 individual product types and device categories in optoelectronics, sensors/actuators, and discretes. The 360-page report shows power transistor sales slowly regaining strength in the next few years, rising 3% in 2017 to $12.8 billion followed by 5% growth in 2018 to about $13.5 billion, which will match the current annual peak set in 2011 (Figure 1).

Between 2015 and 2020, power transistor sales are projected to grow by a CAGR of 3.9% to $14.8 billion in the final year of the 2016 O-S-D Report’s forecast.  The annual growth rate in the second half of this decade essentially matches the CAGR of 4.0% recorded in the last 10 years (2005-2015), but IC Insights anticipates much less volatility in the power transistor market because worldwide demand will continue to climb for greater energy efficiency in data center computers, industrial systems, home appliances, battery-operated portable electronics, automobiles, and the explosion of connections to the Internet of Things (IoT).  Worldwide shipments of power transistors are now forecast to rise by a CAGR of 6.5%, reaching 71.1 billion units in 2020 compared to about 52.0 billion in 2015.

power transistors

Among the power transistor product categories, sales growth is expected to be the strongest in high voltage field-effect transistors (FETs) and insulated-gate bipolar transistor (IGBT) modules during the second half of this decade. The 2016 O-S-D Report shows sales of high-voltage (over 200V) FETs growing by a CAGR of 4.7% to $2.4 billion in 2020 while IGBT modules are expected to increase by an annual rate of 4.0% to $3.2 billion in five years.  Other projected 2015-2020 CAGR growth rates for power transistor product categories are: 3.7% for low-voltage FETs (under 200V) to $5.6 billion; 3.8% for discrete IGBT transistors to $1.1 billion; and 3.1% for bipolar junction transistors to $886 million in 2020.

Despite slower growth for the automotive industry and exchange rate fluctuations, the automotive semiconductor market grew at a modest 0.2 percent year over year, reaching $29 billion in 2015, according to IHS (NYSE: IHS), a global source of critical information and insight.

A flurry of mergers and acquisitions last year caused the competitive landscape to shift, including the merger of NXP and Freescale, which created the largest automotive semiconductor supplier in 2015 with a market share of 14.3 percent, IHS said. The acquisition of International Rectifier (IR) helped Infineon overtake Renesas to secure the second-ranked position, with a market share of 9.8 percent. Renesas slipped to third-ranked position in 2015, with a market share of 9.1 percent, followed by STMicroelectronics and Texas Instruments.

“The acquisition of Freescale by NXP created a powerhouse for the automotive market. NXP increased its strength in automotive infotainment systems, thanks to the robust double-digit growth of its i.MX processors,” said Ahad Buksh, automotive semiconductor analyst for IHS Technology. “NXP’s analog integrated circuits also grew by double digits, thanks to the increased penetration rate of keyless-entry systems and in-vehicle networking technologies.”

NXP will now target the machine vision and sensor fusion markets with the S32V family of processors for autonomous functions, according to the IHS Automotive Semiconductor Intelligence Service Even on the radar front, NXP now has a broad portfolio of long- and mid-range silicon-germanium (SiGe) radar chips, as well as short-range complementary metal-oxide semiconductor (CMOS) radar chips under development. “The fusion of magnetic sensors from NXP, with pressure and inertial sensors from Freescale, has created a significant sensor supplier,” Buksh said.

The inclusion of IR, and a strong presence in advanced driver assistance systems (ADAS), hybrid electric vehicles and other growing applications helped Infineon grow 5.5 percent in 2015. Infineon’s 77 gigahertz (GHz) radar system integrated circuit (RASIC) chip family strengthened its position in ADAS. Its 32-bit microcontroller (MCU) solutions, based on TriCore architectures, reinforced the company’s position in the powertrain and chassis and safety domains.

The dollar-to-yen exchange rate worked against the revenue ranking for Renesas for the third consecutive year. A major share of Renesas business is with Japanese customers, which is primarily conducted in yen. Even though Renesas’ automotive semiconductor revenue fell 12 percent, when measured in dollars, the revenue actually grew by about 1 percent in yen. Renesas’ strength continues to be its MCU solutions, where the company is still the leading supplier globally.

STMicroelectronics’ automotive revenue declined 2 percent year over year; however, a larger part of the decline can be attributed to the lower exchange rate of the Euro against the U.S. dollar in 2015, which dropped 20 percent last year. STMicroelectronics’ broad- based portfolio and its presence in every growing automotive domain of the market helped the company maintain its revenue as well as it did. Apart from securing multiple design wins with American and European automotive manufacturers, the company is also strengthening its relationships with Chinese auto manufacturers. Radio and navigation solutions from STMicroelectronics were installed in numerous new vehicle models in 2015.

Texas Instruments has thrived in the automotive semiconductor market for the fourth consecutive year. Year-over-year revenue increased by 16.6 percent in 2015. The company’s success story is not based on any one particular vehicle domain. In fact, while all domains have enjoyed double-digit increases, infotainment, ADAS and hybrid-electric vehicles were the primary drivers of growth.

IHS_Auto_Semis_Ranking_2015

Other suppliers making inroads in automotive

After the acquisition of CSR, Qualcomm rose from its 42nd ranking in year 2014, to become the 20th largest supplier of automotive semiconductors in 2015. Qualcomm has a strong presence in cellular baseband solutions, with its Snapdragon and Gobi processors; while CSR’s strength lies in wireless application ICs — especially for Bluetooth and Wi-Fi. Qualcomm is now the sixth largest supplier of semiconductors in the infotainment domain.

Moving from 83rd position in 2011 to 37th in 2015, nVidia has used its experience, and its valuable partnership with Audi, to gain momentum in the automotive market. The non-safety critical status of the infotainment domain was a logical stepping stone to carve out a position in the automotive market, but now the company is also moving toward ADAS and other safety applications. The company has had particular success with its Tegra processors.

Due to the consolidation of Freescale, Osram entered the top-10 ranking of automotive suppliers for the first time in 2015. Osram is the global leader in automotive lighting and has enjoyed double-digit growth over the past three years, thanks to the increasing penetration of light-emitting diodes (LEDs) in new vehicles.

Ultratech, Inc., a supplier of lithography, laser-processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HB-LEDs), as well as atomic layer deposition (ALD) systems, today announced a follow-on order from a major foundry in Asia for its LSA101 laser spike anneal system. Equipped with the dual-beam option, the system provides a second low-power laser that adds flexibility for annealing at low substrate temperatures. This capability is required for advanced applica­tions, such as gate stack formation, silicide or post-silicide anneal. The LSA101 tool will be used to support the foundry’s 28nm and 40nm production efforts, and Ultratech expects to ship the system in the third quarter of 2016.

Scott Zafiropoulo, General Manager of LSA and Senior Vice President of Marketing at Ultratech, said, “This follow-on order for our LSA101 system reinforces the growing opportunities that we are experiencing for advanced planar logic devices. Customers around the world are increasing their 28-nm capacity to take advantage of the optimal performance-to-cost ratio at this node. We will continue working closely with our global customers as we strive to continue to provide advanced annealing systems that deliver the most flexible, extendable and cost-effective performance.”

Ultratech LSA 101 Dual Beam Laser Spike Anneal System

Built on the customizable Unity Platform, LSA101 with the dual-beam option expands the process space by adding a second low-power laser beam that adds process flexibility and enables millisecond annealing with a low substrate temperature. Inserting a millisecond anneal step post-junction formation, such as gate stack formation, silicide or post-silicide anneal, has been shown to improve leakage and device reliability, while reducing contact resistance and improving both performance and yield. Compared to compet­ing millisecond annealing technologies, LSA with dual beam is designed to offer the lowest thermal budget millisecond anneal process along with superior within-die uniformity for different layouts. The LSA101 delivers high flexibility and extendibility for advanced annealing applications and is currently in high-volume production for advanced planar and FinFET devices.

Do you really know how good your UHP pressure transducers are based on the manufacturer-provided datasheet as end users?

BY YANLI CHEN and MATTHEW MILBURN, UCT, Hayward, CA

As a widely-used components in the semiconductor industry, the performance of UHP pressure trans- ducers are very important for process control and process monitoring. Selecting a proper UHP pressure transducer with good performance for specific application is challenging, because different UHP pressure transducers manufacturers have different parameters listed in their datasheet/specification. For example, FIGURE 1, 2 and 3 are displaying the published speci- fication of UHP pressure transducers from three major manufacturers. Manufacturer A states “BFSL” (Best-fit straight line) method in its accuracy. However, manufacturer C uses “BFSL” in its non-linearity. Except accuracy, manufacturer B and C list non-linearity and hysteresis in their datasheet as well, but those parameters are not shown in manufacturer A’s datasheet. Behinds the datasheet/ specification, it was found that they have different test procedure and data processing methods to determine performance characteristics, such as non-linearity, hysteresis, non-repeatability, and accuracy. So, for neither the specifier nor the end users is it possible to compare the performance of different brands of pressure transducers without standardized test methods. To date, the industry has not recognized the full scope of the specification problem nor developed a standardized testing and reporting program.

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Technical data and their definition

Before conducting any test, it is necessary to understand the definition of technical data. The common used parameters in the datasheet, such as non-repeatability, non-linearity, hysteresis, and accuracyRSS are explained in the following sections.

Non-repeatability error is defined as the largest deviation between the highest and lowest measurements of the same pressure taken under identical conditions. Non-repeatability characterizes the extent to which the output signals for successive measurements of the same pressure vary, and it is an important parameter to judge the design and manufacturing quality of the instrument. High repeatability (i.e., a small non-repeatability error) is a basic requirement of every dependable sensor system. Sometimes, it is expressed as repeatability in percent of full scale.

Non-linearity is defined as the largest deviation (positive or negative) between the actual-characteristic curve and a reference straight line. There are several ways to determine the reference straight line. The two most common are the terminal straight line (TSL) and the best-fit straight line (BFSL) as shown in FIGURE 4. In the TSL method, the zero error and span error are ignored and an ideal line connecting the zero and full-scale test is drawn and used as the reference straight line (red line in Figure 4). In the BFSL method, the reference straight line is positioned in relation to the measured characteristic curve in such a way that the sum of squares of the deviations is minimal (green line in Fig. 4). There is no requirement for this line to be parallel or in any other way related to the ideal line of the TSL method. The BFSL method is the standard data fitting method used by the major pressure trans- ducer manufacturers in the United States. Sometimes, non-linearity is expressed by linearity in percent of full scale.

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Hysteresis is defined as the maximum deviation between the increasing and decreasing characteristic curves as shown in FIGURE 5, which is caused by the applied pressure. Due to the nature of hysteresis, the output readings during rising pressure typically lower than the readings on the return path to zero.

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AccuracyRSS, UncertaintyRSS and Inaccuracy Historically, most major manufacturers are using a traditional root sum squares (RSS), defined as the square root of the sum of the squares of non-linearity/linearity, non-repeatability/repeatability and hysteresis, as a method to quantify the accuracy of a pressure transducer. In reality, the RSS method cannot truly reflect the accuracy/inaccuracy behavior of a pressure transducer which can be proved by the test results in the following sections.

A new term, inaccuracy, is introduced. It is defined as the worst case performance or absolute value of the maximum deviation at any measured value from the ideal value across the full pressure range of a transducer. Inaccuracy is much more representative of a device’s performance.

In order to be able to compare the test results with the manufacturers’ published specification, a new term, “uncertaintyRSS”, is introduced based on the “uncertainty” definition from SEMI International Standards: Compilation of Terms. Actually, it is the same as the historical accuracyRSS listed in most manufacturers’ published specification.

Experimental

Three UHP pressure transducer manufacturers (MFG A, MFG B and MFG C) participated in this comprehensive performance evaluation project by providing their products as test samples. FIGURE 6 shows the detailed information of devices under tests (DUTs). Twelve DUTs were installed in a test fixture designed by UCT for running simultaneous tests. The schematic of the test fixture is shown in FIGURE 7. The benefit of this design is to save significant amounts of time for assembly, disassembly, and testing, and eliminate potential setup errors occurring in the sequential tests.

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The tests were conducted in a temperature controlled environment (20 ± 20C). FIGURE 8 shows the DUTs in the environmental chamber. The tests were completed by running total ten ascending (from 0%FS to 100%FS in 10%FS steps with a rate of change setpoint every 200 seconds) and descending (from 100%FS to 0%FS in 10%FS steps with a rate of change setpoint every 200 seconds) cycles.

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Test results and discussion

The test results are summarized in FIGURE 9. In each sample group, the highest test value is highlighted in red and the lowest test value is highlighted in green. For each testing parameter, the best case is not always the same DUT in each sample group; the worst case is not always the same DUT in each sample group, either. For better comparison, the test results are graphically shown in FIGURE 10. As shown in Fig. 10, repeatability and hysteresis of the twelve DUTs do not have obvious fluctuations and all of the twelve DUTs have similar values for hysteresis and repeatability.

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However, linearity, uncertaintyRSS and inaccuracy of the twelve DUTs have dramatic fluctuations, especially inaccuracy. Four DUTs from manufacturer C shows higher inaccuracy than the rest of other DUTs. Specifically, DUT 10 is showing extremely high inaccuracy (2.420%FS), which is about thirty-three times worse than the best case (0.074%FS). Four DUTs from manufacturer C also shows poorer linearity than the rest of other DUTs. For the uncertaintyRSS values, three DUTs from manufacturer C have much higher values than the rest of DUTs. Devices from manufacturer B have the best repeatability (0.039%FS), linearity (0.069%FS), inaccuracy (0.238%FS), and uncertaintyRSS (0.090%FS). A device from manufacturer C has the best hysteresis (0.038%FS). Devices from manufacturer A have the worst repeatability (0.050%FS) and hysteresis (0.057%FS) values. Devices from manufacture C have the worst linearity (0.372%FS), uncertaintyRSS (0.376%FS), and inaccuracy (2.420%FS) values. It can be concluded that the devices from manufacturer B have the best overall performance compared to devices from manufacturer A and C.

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In order to conduct the side by side comparison of each manufacturer’s product, the worst case of each manufacturer’s sample for repeatability, linearity, hysteresis, uncertaintyRSS, and inaccuracy is summarized in FIGURE 11 and graphically shown in FIGURE 12.

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The worst case value is reported as the representative values of that brand’s pressure trans- ducer. For each testing parameter, the highest value is highlighted in red and the lowest value is highlighted in green. As shown in Fig. 11, MFG A has the highest repeatability (0.050%FS) and MFG B has the lowest repeat- ability (0.039%FS); MFG C has the highest linearity (0.372%FS) and MFG B has the lowest linearity (0.069%FS); MFG A has the highest hysteresis (0.057%FS) and MFG C has the lowest hysteresis (0.038%FS); MFG C has the highest uncertaintyRSS (0.376%FS) and MFG B has the lowest uncertaintyRSS (0.090%FS); MFG C has the highest inaccuracy (2.420%FS) and MFG B has the lowest inaccuracy (0.238%FS).

When compared with the manufacturers’ published specification, the DUTs of MFG B meet the published specification of repeatability, linearity, hysteresis and uncertaintyRSS; the DUTs of MFG C meet their hysteresis specification, but do not meet their published linearity and uncertaintyRSS specification except that DUT 10 meet the uncertaintyRSS specification. However, DUT 10 has the highest inaccuracy value among the twelve DUTs, which totally supports our findings that uncertaintyRSS or accuracyRSS cannot reflect the true accuracy/inaccuracy behavior.

Conclusions

The results of this study prove that the performance indicator “accuracyRSS” used by most the pressure transducer manufacturers cannot truly reflect the performance. Based on this study, transducers marketed as comparable to each other display dramatically difference performance levels which could lead to process reproducibility challenges. It also demonstrates that the manufacturers’ published specification needs to be improved in order to truly reflect the performance of a UHP pressure transducer. Also, and of critical value, a proper test procedure and data processing method needs to be adopted in the industry. The pressure measurement task force of SEMI North America Gases and Facilities Committee is developing a new pressure transducer measurement standard based on this study.

References

1. Gassmann, Eugen. “Pressure-sensor fundamentals: inter- preting accuracy and error.” Chemical Engineering Progress, June (2014). http://www.aiche.org/sites/default/files/ cep/20140328.pdf
2. Gassmann, Eugen. “Introduction to pressure measurement.” Chemical Engineering Progress, March (2014). http://www. aiche.org/sites/default/files/cep/20140328.pdf
3. SEMI E56-0314, Test method for determining accuracy, linearity, repeatability, short-term reproducibility, hysteresis, and dead band of thermal mass flow controllers
4. SEMI International Standards: Compilation of Terms (Updated 0915) http://www.semi.org/en/sites/semi.org/files/data15/ docs/CompilationTerms0915.pdf
5. IEC 61298-2, Process measurement and control devices- General methods and procedures for evaluating performance- Part 2: Tests under reference conditions

MATTHEW MILBURN is a principal engineer at UCT, Hayward, CA. UCT provides OEMs manufacturers with an array of services including design, engineering, system assembly, testing, and global supply chain management. The company does not manufacture pressure transducers.

Papers that address the theme “Inflections for a Smart Society” are highlighted.

The 2016 Symposium on VLSI Technology is part of a premiere international conference that defines the pace, progress and evolution of micro-electronics, scheduled from June 13-16, 2016 in Honolulu, Hawaii and held in conjunction with the Symposium on VLSI Circuits (June 14-17, 2016). The Symposia’s overall theme “Inflections for a Smart Society,” reflects the industry’s transition point as “smart” system level applications help to transform the industry.

Samsung Electronics will present a 10nm logic technology developed using 3rd generation Si FinFETs for low power, high performance applications, demonstrating a speed improvement of 27% with a 40% reduction in power compared to 14nm process, achieved with multi-threshold voltage devices and reduced contact resistance (FIGURE 1). Overcoming process challenges such as multiple patterning, high aspect ratio etching, niche gate replace- ments, and advanced isolation, the authors demonstrated yield analysis of a 0.04μm2 SRAM with 128Mb cell size and observed a static noise margin of 190mV at 0.75V.

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TSMC will demonstrate a fully functional 32Mb 6-T high density SRAM with smallest reported size of sub-0.03μm2 using bulk CMOS FinFETs scaled beyond the 10nm node (FIGURE 2). This presentation also reports improved transistor performance and electrostatic control through process and CET optimization of scaled FinFETs with competitive performance: DIBL of <45mV/V, sub-threshold swing of <65mV/decade, and static noise margin of ~90mV for the high density SRAM operated at 0.45V.

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IBM and GLOBALFOUNDRIES developed the fundamental and disruptive enhancement of transistor mobility needed to continue expected power and performance scaling at 10nm and beyond, with the introduction of high mobility SiGe channel (20%Ge) into the PFETs to achieve 35% hole mobility increase, and thus ~17% PFET Ieff enhancement. The presentation will demonstrate for the first time10nm FinFET CMOS technology featuring SiGe channel PFETs with superior NBTi reliability and defect control.

TSMC will present a systematic study of the material properties, dimension effects and device characteristics of its In0.53Ga0.47As FinFETs, manufactured on 300mm Si substrates that demonstrate high performance with good uniformity across the wafer. High electron mobility III-V semiconductors are one potential path for continuing Moore’s Law to meet the high performance and low power requirements of future logic applications. Creating high quality hetero-epitaxial of III-V material on large scale Si platforms with good HK/III-V interfaces are critical hurdles to overcome for fabricating HP devices capable of replacing Si FF as scaling continues beyond 7nm.

Significantly, the devices fabricated on 300mm Si show similar characteristics in SS and Ion when benchmarked with equivalent devices fabricated on lattice-matched InP substrates. The current drive of the III-V FinFETs is Ion=44.1uA per fin for a fin-height of 70nm and a fin-width of 25nm. These results are among the highest values reported for In0.53Ga0.47As FinFETs.

Researchers at IBM will demonstrate for the first time high Ge content (HGC) SiGe FinFETs in a replacement mode high-k and metal gate (RMG) process flow with an aggressive equivalent oxide thickness (EOT) scaling down to 0.7nm. IBM’s first of its kind HGC SiGe pMOS FinFETs exhibits high mobility, record-low RMG long channel SS=66mV/dec and good short channel behavior down to Lg=21nm.

The devices are characterized down to 4nm fin widths with excellent mobility (μeff=220cm2/V-s) and reliability at 0.7nm. A 10-year lifetime target is achieved for sub-10nm FinFET widths.
This work demonstrates best mobility values compared to state-of-the-art FinFETs, ultra thin body Si or Ge alternatives, as well as to strained SiGe quantum well options, showing that high performance SiGe FinFETs are feasibile at these aggressive dimensions, with results that outperform all previously reported data.

A team from imec reports on vertically stacked gate- all-around (GAA) n- and p-MOSFETs of 8nm diameter with nanowire stacking and replacement metal gate (RMG) processing, which is relevant for continuing scaling beyond sub-10nm technology (FIGURE 3). Stacking nanowire GAA devices is a promising path to maximize current drive per footprint. Fabricated by adapting a RMG FinFET process, these devices represent an evolutionary approach to extend the learning achieved with FinFET manufacturing. The nanowires exhibit excellent short channel characteristics (SS=65mV/dec, DIBL=42mV/V for Lg=24nm) at performance levels comparable to FinFET devices. The parasitic channel below the nanowires is suppressed by a groundplane doping technique prior to nanowire specific processing.

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Intel’s corporate research group shows performance, area, and energy efficiency are improved by novel tunnel FET (TFET) library circuits, redesign of logic at low-VDD and CMOS/TFET heterogeneous logic. The TFET/CMOS logic with low-overhead level-shifters improves performance 50% while reducing energy 42% for non-critical perfor- mance logic. Performance and power are benchmarked by design synthesis using industry test cases, libraries and interconnect.

TDK Headway Technologies returns to the VLSI Symposium to present advances in writing speed of their perpendicular spin-transfer torque magnetic memory (pSTT-MRAM), which can be reduced to a pulse width of 750ps without compromising functionality and data retention. The switching of the full 8MB array with 80nm devices can be achieved with 3ns pulses without use of error-correcting code (ECC), with the array level data retention showing a 10-year lifetime at 1ppm at 125oC.

They demonstrate sub-ns switching of pSTT-MRAM over a large temperature range after optimization of the magnetic tunnel junction (MTJ) stack, with single devices switched reliably using write pulse length down to 750ps while preserving functionality and data retention @125oC.
This pSTT-MRAM with improved writing speed is a viable candidate for replacement of LCC cache for advanced technology nodes, as well as a possible replacement for non-volatile memory.
A novel perpendicular magnetic tunnel junction (MTJ) is demonstrated by Toshiba with a high speed cache memory operation around 1ns, low power switching less than sub-100μA and size scalability of write current down to 16nm diameter MTJ. This novel MTJ is suited for embedded NVRAM solutions for sub-20nm high-perfor- mance CMOS SoC technology.

Macronix and IBM investigate methods of reducing programming power in phase change memories (PCM) for new storage class memory (SCM) applications. The researchers demonstrate a new low power phase change memory using inter-granular switching (IGS), a novel 3D network of crystallites with phase change confined to grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalco- genide glass is amorphized or crystallized to achieve high or low resistance, they propose a multi-grained structure where the phase change occurs only in the inter-grain regions. By localizing the phase- change to the inter-grain area, the reset power is substantially reduced to 20μA, as well as the thermal disturbance to the neighboring bits, with set speed and cycling endurance also enhanced.

CEA Leti and STMicroelectronics demonstrate for the first time a full 3D VLSI CMOS-over- CMOS integration, CoolCubeTM, on 300mm wafers, with the top level CMOS devices fabricated using low temperature (less than 650°C) processes. A functional 3D inverter with either PMOS over NMOS or NMOS over PMOS is demonstrated to achieve compatible performance with state-of-the- art high performance FDSOI devices. Furthermore, the Leti/STM work demonstrates the integration feasibility of CoolCubeTM by transferring a high quality Si layer over the 28nm devices with W-M1 and then returning to the front end of the line for processing the top CMOS devices.

For the first time, researchers at Stanford and National Nano Device Laboratories have developed a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, integrated with FinFET selector (FIGURE 4). The four-layer 3D RRAM is a versatile computing unit for (a) brain- inspired computing and (b) in-memory computing. Uniform memory performance across four layers is obtained (±0.8V switching, 106 endurance, 104s @125°C). The 3D architecture with dense and balanced neuron-synapse connections provides 55% energy delay product (EDP) savings and 74% VDD reduction (enhanced robustness) as compared with conventional 2D architecture.

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Dialog Semiconductor plc (FWB:DLG), a provider of highly integrated power management, AC/DC power conversion, solid state lighting (SSL) and Bluetooth low energy technology, today announced the appointment of Nick Jeffery to the company’s Board of Directors, effective July 1, 2016. Mr Jeffery has been CEO, Vodafone Global Enterprise since 2006.

“Nick will bring to Dialog a wealth of relevant international business experience, having operated for many years at the highest level of some of Europe’s largest mobile communications companies,” said Rich Beyer, Dialog Chairman of the Board. “During the course of his career, he has launched and scaled new enterprise focused business units and successfully led multiple acquisition and integration projects, and we are very pleased he is joining our board as a non-executive director,” added Beyer.

Joining Vodafone Group plc in 2004, Mr. Jeffery has held a position on the Executive Committee since April 2013 and undertaken numerous roles including that of CEO of the Group’s acquired Cable and Wireless Worldwide operations, from 2012 to 2013. In his most recent role, Mr. Jeffery has proven his ability to grow the business through the launch and successful scaling up of new service lines, both organically and in-organically, including M2M, Cloud, Security and Group Carrier Services. Having begun his career at Cable & Wireless plc (Mercury Communications) in 1991, where he rose to lead the company’s UK and international markets business units, Mr. Jeffery then founded and led Microfone Limited in 2001, whilst serving as Head of Worldwide Sales and Europe Managing Director at Ciena Inc. from 2002 until 2004.

Mr. Jeffery has also served as a non-executive Director at FairFX Group plc since August 2014. He is also a member of the Chartered Institute of Marketing and gained a BSc in Economics from the University of Warwick.

In collaboration with the National Institute of Information and Communications Technology (NICT), Associate Professor Hiroyuki Ito and Professor Kazuya Masu, et al., of the Tokyo Institute of Technology, developed a new algorithm and circuit technology allowing high-frequency piezoelectric resonators to be used for phase locked loops (PLL). It was confirmed that these operate with low noise and have an excellent Figure of Merit (FoM) compared to conventional PLLs.

This technology allows high-frequency piezoelectric resonators to be used in place of crystal oscillators which was a problem for realizing compact and low-cost radio modules. This greatly contributes to the creation of compact, low-cost, high-speed radio communication systems for the IoT age. High-frequency piezoelectric resonators are compact, can be integrated, have an excellent Q value, and oscillators that use these have excellent jitter performance. High-frequency piezoelectric resonators had greater issues with resonance frequency variance and temperature dependability compared to crystal resonators. However, these issues were resolved by the development of a PLL that uses a channel adjustment technique, which is a new algorithm.

A prototype was fabricated by a silicon CMOS process with a minimum line width of 65 nm, and a maximum frequency output of approximately 9 GHz was achieved with a phase fluctuation of only 180 femtoseconds. Power consumption was 12.7 mW. This performance is equivalent to a PLL Figure of Merit (FoM) of -244 dB, and it has the world’s top-class performance as a fractional-N PLL. This can contribute to the realization of compact, low-cost, high-speed radio communication systems.

The study results will be announced in local time June 17 in “The 2016 Symposium on VLSI Circuits” to be held in Hawaii from June 14.