Category Archives: Device Architecture

Leti, an institute of CEA Tech, said today its teams have demonstrated how Fully Depleted Silicon on Insulator (FDSOI) technology can be scaled downwards and how the experience in thin-film engineering built on FDSOI development can be harnessed for innovative architectures and computing paradigms.

At the recent 2016 Symposia on VLSI Technology and Circuits, Leti reported how performance boosters can be successfully implemented on a short time scale to increase performance of next-generation FDSOI devices using material engineering and design/technology co-optimization. With its current performance and flexibility, the FDSOI platform can be extended to the 10nm node. Looking further ahead, thin-film management expertise will be leveraged to design high-performance stacked nanowires.

Based on its expertise in CMOS technologies and thin-film integration, Leti also shared its latest results on CoolCube high-density 3D integration. For the first time, 3D-via density above 10 million/mm² has been demonstrated and high CMOS FDSOI performance has been achieved within a low-temperature integration. CoolCube, which powerfully leverages the benefits of the third dimension, provides designers with a wide range of design opportunities.

Through extreme device scaling, Leti and Inac, a fundamental research division of CEA, are exploring the emerging quantum computing era with an extended use of FDSOI technology for chip design and fabrication.

“These results, which highlight the technology depth of the Grenoble ecosystem, stem from more than a decade of research on ways to use FDSOI-nanowire silicon technologies to design devices with an accurate control of single charge,” said Maud Vinet, Leti’s advanced CMOS manager. “We are currently leveraging this R&D activity, which relies primarily on extensive research in low-temperature physics of ultra-scaled MOS FET properties developed by Leti and Inac, to investigate the potential that silicon FDSOI technology has for quantum computing.”

Leti and its long-time research partner Inac have been investigating a silicon-on-insulator technology for quantum computing applications that could rely on the scalability originally developed for CMOS VLSI circuits. Applying Inac’s expertise in cryogenic electrical measurements and Leti’s SOI nanowire FET technology, the teams also demonstrated the co-integration of quantum devices with conventional CMOS control electronics (ring oscillators) on 300mm SOI substrates.

Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented gate-all-around (GAA) n- and p-MOSFET devices made of vertically stacked horizontal silicon (Si) nanowires (NWs) with a diameter of only 8nm. The devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices.

GAA devices architectures offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. In addition, horizontal NWs are a natural extension of RMG finFETs, in contrast to vertical NWs which require more disruptive technology changes. Furthermore, stacking of NWs maximizes the drive current per footprint. Imec successfully combined these three aspects, and, for the first time, demonstrated vertically stacked horizontal Si NWs at scaled dimensions: 8-nm-diameter wires, 45-nm lateral pitch, and 20-nm vertical separation.

Compared to the conventional bulk FinFET flow, imec implemented two major differences in the process flow. First, shallow trench isolation (STI) densification at 750°C resulted to preserve sharp silicon-germanium (SiGe)/Si interfaces, which is essential for well-controlled Si NW release. Second, a low-complexity ground plane doping scheme was applied, suppressing the bottom parasitic channel.

“By demonstrating stacked nanowires with solid electrostatic control, at scaled dimensions, and using an industry-relevant RMG process on bulk silicon substrates, imec has achieved breakthrough results that can pave the way to realizing sub-10nm technology nodes,” stated Dan Mocuta, Director Logic Device and Integration at imec. “The upcoming research phase will focus on achieving even denser pitches and on leveraging this knowledge to develop gate-all-around lateral nanowire CMOS devices.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs

TEM images of an NMOS GAASiNWFET(LG=70nm):(a)overview of the SiNW array; (b)detailed view of two stacked SiNWs

Today, at the 2016 Symposia on VLSI Technology & Circuits, nano-electronics research center imec presented junction-less gate-all-around (GAA) nanowire (NW) FETs built in lateral and vertical configurations. With their simplified processing, improved reliability, reduced low frequency noise and lower IOFF values, they are an attractive option for advanced logic, low power circuits and analog/RF applications. Moreover, they enable a simpler path for considerable SRAM scaling via the stacking of vertical devices.

GAA-NWFETs -with the gate fully wrapped around the device body for optimum electrostatics control- are considered one of the most promising candidates for enabling (sub-)5nm CMOS scaling. Moreover, junction-less devices offer great process simplicity as they do not require junctions.

Previously, at the 2015 VLSI and IEDM conferences, imec demonstrated the superior reliability behavior of these devices and their potential for low power circuits. At today’s VLSI symposium, imec thoroughly evaluated key control knobs for junction-less devices operation, namely controlling the NW doping vs. NW size to achieve optimum performance. The feasibility of these devices for analog/RF applications was also studied, concluding them to be a viable option with reported similar speeds and voltage gains as compared to inversion-mode NWFETs.

Imec also addressed the variability of junction-less GAA-NWFETs, showing that whereas the VT mismatch increased with increasing nanowire doping for NMOS devices, less impact was observed for PMOS devices and at smaller nanowire dimensions.

Additionally, the junction-less concept was demonstrated in vertical devices integrated on the same 300mm Si platform, also used for lateral devices. Low IOFF and IGvalues and good electrostatics were achieved over a wide range of vertical nanowire arrays.

Lastly, taking advantage of the junction-less devices process simplicity, Imec further explored their potential by proposing a novel SRAM cell design with two vertically stacked junction-less vertical NWFETs with the same channel doping, thus enabling reduction of the SRAM area per bit by 39%.

“Imec’s work has contributed to an increased and more in-depth understanding of junction-less GAA-NWFETs,” stated Dan Mocuta, Director Logic Device and Integration at imec. “Our thorough evaluation highlighted the excellent performance of junction-less lateral and vertical nanowire devices for beyond 5nm logic devices. Moreover, junction-less devices appeared as a viable option for analog/RF applications, whereas stacked junction-less vertical nanowire FETs could significantly reduce SRAM area.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

Gartner, Inc. said global smartphone sales will continue to slow and will no longer grow in double digits. Worldwide smartphone sales are expected to grow 7 percent in 2016 to reach 1.5 billion units. This is down from 14.4 percent growth in 2015. In 2020, smartphone sales are on pace to total 1.9 billion units.

“The smartphone market will no longer grow at the levels it has reached over the last seven years,” said Roberta Cozza, research director at Gartner. “Smartphone sales recorded their highest growth in 2010, reaching 73 percent.”

Slowing replacement of phones

Today, the smartphone market has reached 90 percent penetration in the mature markets of North America, Western Europe, Japan and Mature Asia/Pacific, slowing future growth. Furthermore, users in these regions are not replacing or upgrading their smartphone as often as in previous years.

“In the mature markets, premium phone users are extending life cycles to 2.5 years, which is not going to change drastically over the next five years,” said Ms. Cozza.

Communications service providers (CSPs) have moved away from subsidies providing a “free” smartphone every two years, which has led to more varied upgrade cycles. On the other hand, CSPs have introduced financing programs and vendors such as Apple now offer upgrade programs that provides users with new hardware after only 12 months. “These programs are not for everyone, as most users are happy to hold onto their phone for two years or longer than before. They do so especially as the technology updates have become incremental rather than exponential,” added Ms. Cozza.

In emerging markets, the average lifetime of premium phones is between 2.2 and 2.5 years, while basic phones have an average lifetime of three years and more. “2015 was the year when sales of smartphones overtook those of feature phones for the first time in Sub-Saharan Africa. This region represents an attractive market for vendors that can persuade users to migrate to their first smartphone,” said Ms. Cozza.

India is the main focus for growth opportunity

Since mature markets are saturated, the focus for many vendors is on India and China. “India has the highest growth potential,” said Annette Zimmermann, research director at Gartner. “Sales of feature phones totaled 167 million units in 2015, 61 percent of total mobile phone sales in India.”

Smartphones are expensive for users in India, but with the average selling prices (ASPs) of low-end models falling, Gartner estimates that 139 million smartphones will be sold in India in 2016, growing 29.5 percent year over year. ASPs of mobile phones in India remain under $70, and smartphones under $120 will continue to contribute around 50 percent of overall smartphone sales in 2016.

After recording growth of 16 percent in 2014, sales of smartphones in China were flat in 2015. “In this saturated yet highly competitive smartphone market, there is little growth expected in China in the next five years,” said Ms. Zimmermann. Sales of smartphones in China represented 95 percent of total mobile phone sales in 2015. Similar to India, falling ASPs for smartphones will make them more affordable for users.”

“The worldwide smartphone market remains complex and competitive for all mobile phone vendors, and we are not expecting the vendor landscape to get smaller,” said Ms. Zimmermann. “In such a fluid vendor landscape, some will exit the market while newcomers, including mobile manufacturers or internet service providers from China and India, could make their debut.”

Gartner forecasts that by 2018, at least one nontraditional phone maker will be among the top five smartphone brands in China. “Chinese internet companies are increasingly investing in mobile device hardware development, platforms and distribution as they aim to grow their user bases and increase user loyalty and engagement,” concluded Ms. Zimmermann.

By Paula Doe, SEMI

The changing market for ICs means the end of business as usual for the greater semiconductor supply chain. Smarter use of data analytics looks like a key strategy to get new products more quickly into high yield production at improved margins.

Emerging IoT market drives change in manufacturing

The emerging IoT market for pervasive intelligence everywhere may be a volume driver for the industry, but it will also put tremendous pressure on prices that drive change in manufacturing. Pressure to keep ASPs of multichip connected devices below $1 to $5 for many IoT low-to-mid end applications, will drive more integration of the value chain, and more varied elements on the die. “The value chain must evolve to be more effective and efficient to meet the price and cost pressures for such IoT products and applications,” suggests Rajeev Rajan, VP of IoT, GLOBALFOUNDRIES, who will speak on the issue in a day-long forum on the future of smart manufacturing in the semiconductor supply chain at SEMICON West 2016 on July 14.

“It also means tighter and more complete integration of features on the die that enable differentiating capabilities at the semiconductor level, and also fewer, smaller devices that reduce the overall Bill of Materials (BOM), and result in more die per wafer.” He notes that at 22nm GLOBALFOUNDRIES is looking to enable an integrated connectivity solution instead of a separate die or external chip. Additional requirements for IoT are considerations for integrating security at the lower semiconductor/hardware layers, along with the typical higher layer middleware and software layers.

This drive for integration will also mean demand for new advanced packaging solutions that deliver smaller, thinner, and simpler form factors. The cost pressure also means than the next nodes will have to offer tangible power/performance/area/cost (PPAC) value, without being too disruptive a transition from the current reference flow. “Getting to volume yields faster will involve getting yield numbers earlier in the process, with increasing proof-points and planning iterations up front with customers, at times tied to specific use-cases and IoT market sub-segments,” he notes.

Rapid development of affordable data tools from other industries may help

Luckily, the wide deployment of affordable sensors and data analysis tools in other industries in other industries is developing solutions that may help the IC sector as well.  “A key trend is the “democratization” – enabling users to do very meaningful learning on data, using statistical techniques, without requiring a Ph.D. in statistics or mathematics,” notes Bill Jacobs, director, Advanced Analytics Product Management, Microsoft Corporation, another speaker in the program. “Rapid growth of statistics-oriented languages like R across industries is making it easier for manufacturers and equipment suppliers to capture, visualize and learn from data, and then build those learnings into dashboards for rapid deployment, or build them directly into automated applications and in some cases, machines themselves.”

Intel has reported using commercially available systems such as Cloudera, Aquafold, and Revolution Analytics (now part of Microsoft) to combine, store, analyze and display results from a wide variety of structured and unstructured manufacturing data. The system has been put to work to determine ball grid placement accuracy from machine learning from automatic comparison of thousands of images to select the any that deviate from the known-good pattern,  far more efficiently than human inspectors, and also to analyze tester parametrics to predict 90% of potential failures of the test interface unit before they happen.

“The IC industry may be ahead in the masses of data it gathers, but other industries are driving the methodology for easy management of the data,” he contends. “There’s a lot that can be leveraged from other industries to improve product quality, supply chain operations, and line up-time in the semiconductor industry.”

Demands for faster development of more complex devices require new approaches

As the cost of developing faster, smaller, lower power components gets ever higher, the dual sourcing strategies of automotive and other big IC users puts even more pressure on device makers to get the product right the first time. “There’s no longer time to learn with iterations to gradually improve the yield over time, now we need to figure out how to do this faster, as well as how to counter higher R&D costs on lower margins,” notes Sia Langrudi, Siemens VP Worldwide Strategy and Business Development,   who will also speak in the program.

The first steps are to recognize the poor visibility and traceability from design to manufacturing, and to put organizational discipline into place to remove barriers between silos. Then a company needs good baseline data, to be able to see improvement when it happens. “It’s rather like being an alcoholic, the first step is to recognize you have a problem,” says Langrudi. “People tell me they already have a quality management system, but they don’t. They have lots of different information systems, and unless they are capturing the information all in one place, the opportunity to use it is not there.”

Other speakers discussing these issues in the Smart Manufacturing Forum at SEMICON West July 14 include Amkor SVP Package Products Robert Lanzone, Applied Materials VP New Markets & Services Chris Moran, Intel VP IoT/GM Industrial Anthony Neal Graves, NextNine US Sales Manager Don Harroll, Optimal+ VP WW Marketing David Park, Qualcomm SVP Engineering Michael Campbell, Rudolph Technologies VP/GM Software Thomas Sonderman, and Samsung Sr Director, Engineering Development, Austin, Ben Eynon.

Learn more about the speakers at the SEMICON West 2016 session “Smart Manufacturing: The Key Opportunities and Challenges of the Next Generation of Manufacturing for the Electronics Value Chain.” To see all sessions in the Extended Supply Chain Forum, click here.

The Semiconductor Industry Association (SIA) this week announced worldwide sales of semiconductors reached $25.8 billion for the month of April 2016, a decrease of 1.0 percent from last month’s total of $26.1 billion and 6.2 percent lower than the April 2015 total of $27.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects decreased annual semiconductor sales in 2016, followed by slight market growth in 2017 and 2018.

“Global semiconductor sales decreased marginally in April, continuing a recent trend of market sluggishness driven by soft demand and a range of macroeconomic headwinds,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Despite a cumulative decrease across all product categories, year-to-year sales of microprocessors and analog products increased modestly, perhaps foreshadowing stronger sales ahead. The latest industry forecast suggests global sales may indeed rebound somewhat in the second half of 2016, but still fall short of last year’s total. The global market is projected to grow slightly in 2017 and 2018.”

Regionally, year-to-year sales increased in Japan (2.2 percent) and China (0.3 percent), but decreased in Asia Pacific/All Other (-8.2 percent), Europe (-8.6 percent), and the Americas (-14.8 percent). Compared with last month, sales were up slightly Japan(0.2 percent) and Asia Pacific/All Other (0.1 percent), but down in Europe (-0.8 percent), China (-1.8 percent), and the Americas (-2.2 percent).

Additionally, SIA today endorsed the WSTS Spring 2016 global semiconductor sales forecast, which projects the industry’s worldwide sales will be $327.2 billion in 2016, a 2.4 percent decrease from the 2015 sales total. WSTS projects year-to-year decreases across all regional markets for 2016: Europe (-0.1 percent), Asia Pacific (-1.2 percent), Japan (-1.7 percent), and the Americas (-7.3 percent). On the positive side, WSTS predicts growth in 2016 for several semiconductor product categories, including discretes, analog, and MCU products.

Beyond 2016, the semiconductor market is expected to grow at a modest pace across all regions. WSTS forecasts 2.0 percent growth globally for 2017 ($333.7 billion in total sales) and 2.2 percent growth for 2018 ($340.9 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

April 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

4.89

4.78

-2.2%

Europe

2.66

2.64

-0.8%

Japan

2.59

2.60

0.2%

China

7.93

7.79

-1.8%

Asia Pacific/All Other

8.02

8.03

0.1%

Total

26.09

25.84

-1.0%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.61

4.78

-14.8%

Europe

2.89

2.64

-8.6%

Japan

2.54

2.60

2.2%

China

7.77

7.79

0.3%

Asia Pacific/All Other

8.74

8.03

-8.2%

Total

27.56

25.84

-6.2%

Three-Month-Moving Average Sales

Market

Nov/Dec/Jan

Feb/Mar/Apr

% Change

Americas

5.41

4.78

-11.7%

Europe

2.70

2.64

-2.4%

Japan

2.49

2.60

4.3%

China

8.42

7.79

-7.4%

Asia Pacific/All Other

7.87

8.03

2.0%

Total

26.89

25.84

-3.9%

Media Contact 

By Debra Vogler, SEMI

A forum of industry experts at SEMICON West 2016 will discuss the challenges associated with getting from node 10 — which seems set for HVM — to nodes 7 and 5. Confirmed speakers at the “Node 10 to Node 5 ─ Dealing with the Slower Pace of Traditional Scaling (Track 2)” session on Tuesday, July 12, 2:00pm-4:00pm, are Lode Lauwers (imec), Guy Blalock (IM Flash), Kelvin Low (Samsung), Mike Chudzik (Applied Materials), Kevin Heidrich (Nanometrics), and David Dutton (Silvaco). SEMI interviewed Lauwers and Chudzik to see what challenges they see ahead as the industry progresses from node 7 to node 5.

According to Mike Chudzik, senior director, Cross-Business Unit Modules Team at Applied Materials, “The top tw or three process development challenges facing the industry at node 7 are RC reduction, RC reduction, and RC reduction,” Chudzik told SEMI. “At the 7nm node, parasitic resistance and parasitic capacitance delays are predicted to be greater than the inherent transistor delay.” Among the solutions he cites are new materials such as cobalt for the contact fill, lower-k spacers, and integration solutions, such as air-gap and replacement contact schemes. “While FinFETs are expected to scale to the 7nm node, their days are numbered. If you want to scale to the true historical 0.7X 7nm node, it’s a challenge for FinFETs because continuing to scale the gate length requires scaling the fin width.” He also explained that the variability in patterned fins will cause serious device performance challenges at near 5nm fin width on account of quantum confinement. “Something new like gate-all-around (GAA) devices are needed to fuel the next-generation of device scaling.”

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Figure 1: At the 7nm node (CD of 13nm), the resistance of the TiN/W fill materials for the contact plug is expected to become higher than the interfacial contact resistance. SOURCE: Applied Materials

Among the materials challenges in getting to nodes 7 and 5 are cobalt implementation for the contact, and Si/SiGe superlattices for the 5nm node, explained Chudzik. “The former challenge concerns replacing tungsten in the contact plug, and the latter is needed to form horizontal GAA structures.” Figure 1 shows that at the 7nm node (CD of 13nm) the resistance of the TiN/W fill material for the contact plug is expected to become higher than the interfacial contact resistance. “A TiN/Co solution provides relief.”

In addition to improving the performance of the interconnect, Lode Lauwers, VP, business development for CMOS technology at imec, told SEMI that getting to node 7 will require very advanced fin technology combined with a patterning solution. Looking ahead to node 5, he said it is expected that the fin will still be the reference technology, along with the introduction of new materials such as SiGe, and a high concentration of Ge in the channel as a mobility improvement, and possibly even the consideration of III-V materials (particularly at N5) (see Figures 2 and 3).

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 2: Performance and energy efficiency roadmap: devices architectures. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

Figure 3: Performance and energy efficiency roadmap: transistor features that are driving the logic roadmap. SOURCE: imec

In looking out towards the horizon, Lauwers pointed out that the industry has to consider alternatives to the fin because there is an engineering limit to how small the fin dimensions can be made. “There is the possibility that at node 5 the industry will consider alternatives to the traditional fin, said Lauwers. “For example, the GAA structure (also referred to as a lateral or horizontal nanowire, HGAA) is superior in terms of gate control and will have better leakage control. That means you will be able to have better performance over a lower supply voltage with a lower threshold voltage.”

Beyond HGAA structures, Lauwers observed that the industry could move to a vertical nanowire structure (VGAA). But there are several contenders (see Figure 2). “It’s not up to imec to choose and it’s too early to say what will be the right option,” Lauwers told SEMI. “Maybe for certain applications or a certain technology positioning, a device maker might make a different compromise.”

In addition to imec and Applied Materials, speakers from IM Flash, Nanometrics, Samsung, and Silvaco will present at the “Scaling: Node 10 to Node 5” session of the three-day Advanced Manufacturing Forum (see Schedule-at-a-Glance) at SEMICON West 2016 which takes place July 12-14 in San Francisco, Calif.

Today, SEMI announced that 19 new fabs and lines are forecasted to begin construction in 2016 and 2017, according to the latest update of the SEMI World Fab Forecast report. While semiconductor fab equipment spending is off to a slow start in 2016, it is expected to gain momentum through the end of the year. For 2016, 1.5 percent growth over 2015 is expected while 13 percent growth is forecast in 2017.

Fab equipment spending ─ including new, secondary, and in-house ─ was down 2 percent in 2015. However, activity in the 3D NAND, 10nm Logic, and Foundry segments is expected to push equipment spending up to US$36 billion in 2016, 1.5 percent over 2015, and to $40.7 billion in 2017, up 13 percent. Equipment will be purchased for existing fabs, lines that are being converted to leading-edge technology, as well as equipment going into new fabs and lines that began construction in the prior year.

Table 1 shows the regions where new fabs and lines are expected to be built in 2016 and 2017. These projects have a probability of 60 percent or higher, according to SEMI’s data. While some projects are already underway, others may be subject to delays or pushed into the following year. The SEMI World Fab Forecast report, published May 31, 2016, provides more details about the construction boom.

new fab lines

Breaking down the 19 projects by wafer size, 12 of the fabs and lines are for 300mm (12-inch), four for 200mm, and three LED fabs (150mm, 100mm, and 50mm). Not including LEDs, the potential installed capacity of all these fabs and lines is estimated at almost 210,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2016 and 330,000 wafer starts per month (in 300mm equivalents) for fabs beginning construction in 2017.

In addition to announced and planned new fabs and lines, SEMI’s World Fab Forecast provides information about existing fabs and lines with associated construction spending, e.g. when a cleanroom is converted to a larger wafer size or a different product type.

In addition, the transition to leading-edge technologies (as we can see in planar technologies, but also in 3D technologies) creates a reduction in installed capacity within an existing fab. To compensate for this reduction, more conversions of older fabs may take place, but also additional new fabs and lines may begin construction.

For insight into semiconductor manufacturing in 2016 and 2017 with details about capex for construction projects, fab equipping, technology levels, and products, visit the SEMI Fab Database webpage and order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 60 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.

The market is expected to grow from USD 10.57 Billion in 2015 to USD 31.26 Billion by 2022, at a CAGR of 15.4% between 2016 and 2022, according to the new report “RF Power Semiconductor Market by Product (Power Amplifiers, Passives, Switches, and Duplexers), Material (Silicon, Gallium Nitride, and Gallium Arsenide), Frequency, Application (Consumer, and Aerospace & Defense), and Geography – Global Forecast to 2022,” published by MarketsandMarkets.

Early buyers will receive 10% customization on this report.

The use of power amplifiers for long-term evolution (LTE) has increased with the growing demand for LTE. The transition to LTE would require a significant investment in the market as the core networks would also need to change for the upgradation of the wireless standard. This would also drive the demand for RF power devices, which would boost the growth of the RF power semiconductor market. The increased use of smartphones is another major factor driving the growth of the RF power semiconductor market.

RF power amplifiers to play a key role in the RF power semiconductor market

The RF power amplifiers are expected to hold the largest market share and dominate the RF power semiconductor market between 2016 and 2022 owing to the increasing adoption of power amplifiers across the globe. The growing preference for wireless connectivity has driven the use of RF power devices in wireless connectivity. The RF power amplifiers have applications in sectors such as aerospace & defense, automotive, medical, telecommunication and data communication, and consumer among others.

Consumer application held the largest market share in 2015

The consumer application is expected to hold the largest market share and dominate the RF Power Semiconductor Market between 2016 and 2022. The growing use of smartphones and demand for faster data rates are the major drivers for the RF power semiconductor market in the consumer sector. The growth of LTE is also one of the major drivers for the growth of the RF power semiconductor market.

APAC expected to hold the largest market share and grow at the highest rate

APAC is expected to hold the largest market share and dominate the RF power semiconductor market between 2016 and 2022. The established electronics industry and adoption of innovative technologies are the reasons for the high growth rate in the region. The RF power semiconductor market in Asia-Pacific is expected to grow at a high rate in consumer, telecommunication and data communication, and medical sectors among others. The increasing number of players in the region is further expected to drive the growth of the APAC RF power semiconductor market.

The key players in RF power semiconductor market include Infineon Technologies AG (Germany), M/A-COM Technology Solutions Holdings, Inc. (U.S.), NXP Semiconductors N.V. (Netherlands), Qorvo, Inc. (U.S.), Broadcom Limited (U.S.), Toshiba Corporation (Japan), Qualcomm Inc. (U.S.), Skyworks Solutions, Inc. (U.S.), Mitsubishi Electric Corporation (Japan), and Murata Manufacturing (Japan).