Category Archives: Device Architecture

A team of scientists from Arizona State University’s School of Molecular Sciences and Germany have published in Science Advances online today an explanation of how a particular phase-change memory (PCM) material can work one thousand times faster than current flash computer memory, while being significantly more durable with respect to the number of daily read-writes.

PCMs are a form of computer random-access memory (RAM) that store data by altering the state of the matter of the “bits”, (millions of which make up the device) between liquid, glass and crystal states. PCM technology has the potential to provide inexpensive, high-speed, high-density, high-volume, nonvolatile storage on an unprecedented scale.

The basic idea and material were invented by Stanford Ovshinsky, long ago, in1975, but applications have lingered due to lack of clarity about how the material can execute the phase changes on such short time scales and technical problems related to controlling the changes with necessary precision. Now high tech companies like Samsung, IBM and Intel are racing to perfect it.

The semi-metallic material under current study is an alloy of germanium, antimony and tellurium in the ratio of 1:2:4. In this work the team probes the microscopic dynamics in the liquid state of this PCM using quasi-elastic neutron scattering (QENS) for clues as to what might make the phase changes so sharp and reproducible.

On command, the structure of each microscopic bit of this PCM material can be made to change from glass to crystal or from crystal back to glass (through the liquid intermediate) on the time scale of a thousandth of a millionth of a second just by a controlled heat or light pulse, the former now being preferred. In the amorphous or disordered phase, the material has high electrical resistance, the “off” state; in the crystalline or ordered phase, its resistance is reduced 1000 fold or more to give the “on” state.

These elements are arranged in two dimensional layers between activating electrodes, which can be stacked to give a three dimension array with particularly high active site density making it possible for the PCM device to function many times faster than conventional flash memory, while using less power.

“The amorphous phases of this kind of material can be regarded as “semi-metallic glasses”,” explains Shuai Wei, who at the time was conducting postdoctoral research in SMS Regents’ Professor Austen Angell’s lab, as a Humboldt Foundation Fellowship recipient.

“Contrary to the strategy in the research field of “metallic glasses”, where people have made efforts for decades to slow down the crystallization in order to obtain the bulk glass, here we want those semi-metallic glasses to crystallize as fast as possible in the liquid, but to stay as stable as possible when in the glass state. I think now we have a promising new understanding of how this is achieved in the PCMs under study.”

A Deviation from the expected

Over a century ago, Einstein wrote in his Ph.D. thesis that the diffusion of particles undergoing Brownian motion could be understood if the frictional force retarding the motion of a particle was that derived by Stokes for a round ball falling through a jar of honey. The simple equation: D (diffusivity) = kBT/6??r where T is the temperature, ? is the viscosity and r is the particle radius, implies that the product D?/T should be constant as T changes, and the surprising thing is that this seems to be true not only for Brownian motion, but also for simple molecular liquids whose molecular motion is known to be anything but that of a ball falling through honey!

“We don’t have any good explanation of why it works so well, even in the highly viscous supercooled state of molecular liquids until approaching the glass transition temperature, but we do know that there are a few interesting liquids in which it fails badly even above the melting point,” observes Angell.

“One of them is liquid tellurium, a key element of the PCM materials. Another is water which is famous for its anomalies, and a third is germanium, a second of the three elements of the GST type of PCM. Now we are adding a fourth, the GST liquid itself..!!! thanks to the neutron scattering studies proposed and executed by Shuai Wei and his German colleagues, Zach Evenson (Technical University of Munich, Germany) and Moritz Stolpe (Saarland University, Germany) on samples prepared by Shuai with the help of Pierre Lucas (University of Arizona).”

Another feature in common for this small group of liquids is the existence of a maximum in liquid density which is famous for the case of water. A density maximum closely followed, during cooling, by a metal-to semiconductor transition is also seen in the stable liquid state of arsenic telluride, (As2Te3), which is first cousin to the antimony telluride (Sb2Te3 ) component of the PCMs all of which lie on the “Ovshinsky” line connecting antimony telluride (Sb2Te3 ) to germanium telluride (GeTe) in the three component phase diagram. Can it be that the underlying physics of these liquids has a common basis?

It is the suggestion of Wei and coauthors that when germanium, antimony and tellurium are mixed together in the ratio of 1:2:4, (or others along Ovshinsky’s “magic” line) both the density maxima and the associated metal to non-metal transitions are pushed below the melting point and, concomitantly, the transition becomes much sharper than in other chalcogenide mixtures.

Then, as in the much-studied case of supercooled water, the fluctuations associated with the response function extrema should give rise to extremely rapid crystallization kinetics. In all cases, the high temperature state (now the metallic state), is the denser.

“This would explain a lot,” enthuses Angell “Above the transition the liquid is very fluid and crystallization is extremely rapid, while below the transition the liquid stiffens up quickly and retains the amorphous, low-conductivity state down to room temperature. In nanoscopic “bits”, it then remains indefinitely stable until instructed by a computer-programmed heat pulse to rise instantly to a temperature where, on a nano-second time scale, it flash crystallizes to the conducting state, the “on” state.

Lindsay Greer at Cambridge University has made the same argument couched in terms of a “fragile-to-strong” liquid transition”.

A second slightly larger heat pulse can take the “bit” instantaneously above its melting point and then, with no further heat input and close contact with a cold substrate, it quenches at a rate sufficient to avoid crystallization and is trapped in the semi-conducting state, the “off” state.

“The high resolution of the neutron time of flight-spectrometer from the Technical University of Munich was necessary to see the details of the atomic movements. Neutron scattering at the Heinz Maier-Leibnitz Zentrum in Garching is the ideal method to make these movements visible,” states Zach Evenson.

SEMI, the global industry association representing the electronics manufacturing supply chain, today applauded the United States and China for agreeing to take first steps to reduce trade tensions. The U.S. plans to delay tariff increases on $200 billion worth of Chinese imports, China has vowed to increase U.S. market access, and both parties are planning talks over the course of 90 days to address current frictions.

“Everyone, businesses and consumers alike, relies on devices powered by semiconductors,” said Ajit Manocha, president and CEO of SEMI. “Tariffs on products threaten jobs, stifle innovation, curb growth, and compromise U.S. competitiveness.”

With intellectual property critical to the semiconductor industry, SEMI strongly supports efforts to better protect valuable IP. SEMI believes, however, that U.S. tariff increases will ultimately do nothing to change China’s trade practices. SEMI has long supported efforts to reduce and end trade tensions between the U.S. and China.

“While this is a first step, it is encouraging to see presidents Trump and Xi committed to working together,” Manocha said. “We look forward to continued negotiations that produce an agreement that not only removes tariffs altogether, but also satisfactorily addresses bilateral economic concerns.”

The semiconductor industry relies heavily on international trade. Since the tariffs have been in force, companies have faced higher costs, greater uncertainty, and difficulty selling products abroad.

Since action against China was announced in March, SEMI has engaged heavily with the Trump administration, submitting written comments and offering testimony on the importance of the free trade to the industry as well as the damaging effects of tariffs on Chinese goods. SEMI estimates that tariffs would have cost semiconductor companies more than $700 million annually.

Last month, SEMI issued “10 Principles for the Global Semiconductor Supply Chain in Modern Trade Agreements,” calling for their adoption in existing and new trade deals, including frameworks for a U.S.-China agreement.

In the face of the microelectronics industry’s unprecedented challenges and opportunities with artificial intelligence (AI) and new markets outside the historic semiconductor audiences, SEMI announces the Technology Leadership Series of the Americas. The seven-part sequence of related strategy and technical conferences comprises the world’s largest and most comprehensive approach for examining and fabricating future innovations that can fuel a higher quality of life for the planet.

As the era begins with the volume of the world’s data doubling every 12-18 months, a global brain trust of hundreds of industry experts has provided inputs for a coherent, step-by-step process that will position the microelectronics industry to navigate the future.

With an objective to reduce learning curves and shorten product times to market, key interest groups have rallied with SEMI in the past 24 months to multiply interactions with the supply chain. In turn, these exchanges are calculated to increase the members’ respective technical ROIs. Technology communities include the Fab Owners Alliance (FOA), FlexTech, MEMS & Sensors Industry Group (MSIG), Electronic System Design Alliance, as well as global partner associations such as IEEE and SAE International, which leads technical learning for the mobility industry.

As a result, more than 2,100 global market-related businesses have teamed with SEMI to help structure content for the Technology Leadership Series of the Americas.

Aligned from coast to coast, across a 12-month span, the series is designed to foster the most critical discussions for connecting both the short-term and long-term influences impacting the $2 trillion worth of emerging markets. The series further aims to remove guesswork about which of the world’s rapidly rising number of conferences provides the highest ROI for the senior executive, engineer-scientist and sales manager.

“There’s been lots of talk around AI, its potential enhancements for nearly all markets, and which priorities should be next for maximizing those. To facilitate measurable industry progress, the approach for this series is to fit together the most critical puzzle pieces – strategy, design, new materials and manufacturing technologies – that will deliver the most impactful roadmap for the coming decades,” said David Anderson, president of SEMI Americas and series co-author. “The experts have concluded that focal points identified for these topic-exclusive conferences will each serve as a stepping stone – or enabler – for the roadmap’s most important areas. As with previous industry efforts, what hasn’t changed is that the path to success hinges on collaboration by partners from across the supply chain.”

Target topics will address the leading edges of industry knowledge and practices, including up-to-the-minute market forecasts and deep dives into game-changing issues and advancements. Six strategy and technical conferences will culminate in an unmatched integration of technologies and partners at SEMICON West, July 9-11, 2019, in San Francisco.

The Series’ special conferences are:

  • Industry Strategy Symposium (ISS) Jan. 6-9 – will kick off the new year with analysis of new and emerging demand drivers for new architectures, new logic and memory, new streams of investment and how to advance their arrivals and ensure longevities that enable the next industrial revolution.
  • Flexible & Printed Electronics and MEMS & Sensors Technical Congress (FLEX/MSTC) Feb. 18-21 – the co-located events will provide the most comprehensive technical conference as FLEX focuses on the design and manufacture of flexible electronics, including sensors, IC integration and substrates, while MSTC focuses on the technology behind the trends in MEMS and sensors for autonomous mobility in mobile devices, IOT, drones, and autonomous transportations.
  • Advanced Semiconductor Manufacturing Conference (ASMC) May 6-9 – will improve the industry’s advanced manufacturing strategies and methodologies through a combined sharing of highlights and insights by device makers, equipment and materials suppliers and academics. Women in Semiconductors will hold their third annual workshop.
  • Strategic Materials Conference (SMC) Sept. 2019 – will share the latest developments from around the world in strategic materials that will be vital for new markets, system creation, heterogeneous integration and packaging.
  • MEMS & Sensors Executive Congress (MSEC) Oct. 2019 – will present how the next generations of MEMS and sensors will be designed and produced to meet on-going growth for emerging markets beyond the historic microelectronics customer base.
  • International Technology Partners Conference (ITPC) Nov. 3-6 – will advance productive trans-pacific relationships to help avoid threatened supply chain prosperity, leveraging thought-leadership and relationship-building programs for executive-level engagement.

At the peak of the collaborative series, SEMICON West 2019 will provide renowned global presenters and hands-on demos, at both strategic and technical levels, for up-to-minute predictions and breakthroughs on upcoming trends and enablers. Based on direction from SEMI’s members, the five vertical application areas of AI and Data, Smart Transportation, MedTech, Smart Manufacturing and Industrial Automation, plus workforce development, will be featured at the semiconductor industry’s flagship event.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced the addition of Silicon Labs (NASDAQ: SLAB) as an SIA member. Silicon Labs President and CEO Tyson Tuttle was elected to the SIA board of directors at the association’s board meeting on Nov. 29. Silicon Labs joins several other companies that have become SIA members within the last year: Cree, NVIDIA, Xilinx, Arm, SK Hynix, and KLA-Tencor.

“Silicon Labs is a major player and leading voice in our industry, and we’re thrilled to have them in the SIA tent,” said John Neuffer, SIA President and CEO. “SIA has a 40-year history of advancing the semiconductor industry’s interests in Washington and capitals around the world. Our work to advance policies that will promote growth and innovation in our industry will be greatly strengthened by the addition of Silicon Labs as a member, and we are excited to welcome Tyson Tuttle to the SIA board.”

Tyson Tuttle has been instrumental in shaping Silicon Labs’ strategic and technological direction for more than 20 years. After becoming CEO in 2012, Tyson laid the foundation for a cultural shift to serve broad-based markets with a greater emphasis on software and tools, enabling customers to simplify IoT system design. As CEO, Tyson has transformed Silicon Labs into a leading provider of IoT connectivity solutions, with more than half of the company’s revenue stemming from the IoT. He has more than 25 years of semiconductor experience and holds more than 70 patents in RF and mixed-signal IC design. Tyson received a B.S. degree in Electrical Engineering in 1989 from Johns Hopkins University and an M.S. degree in Electrical Engineering in 1992 from UCLA.

“Smart government policy is critical to the continued strength of the semiconductor industry, the tech sector, and the broader economy,” said Tuttle. “It is a true pleasure to represent Silicon Labs on the SIA board and to work alongside my colleagues to make meaningful progress on issues of great importance to us all.”

Researchers from Intel Corp. and the University of California, Berkeley, are looking beyond current transistor technology and preparing the way for a new type of memory and logic circuit that could someday be in every computer on the planet.

In a paper appearing online Dec. 3 in advance of publication in the journal Nature, the researchers propose a way to turn relatively new types of materials, multiferroics and topological materials, into logic and memory devices that will be 10 to 100 times more energy-efficient than foreseeable improvements to current microprocessors, which are based on CMOS (complementary metal-oxide-semiconductor).

Single crystals of the multiferroic material bismuth-iron-oxide. The bismuth atoms (blue) form a cubic lattice with oxygen atoms (yellow) at each face of the cube and an iron atom (gray) near the center. The somewhat off-center iron interacts with the oxygen to form an electric dipole (P), which is coupled to the magnetic spins of the atoms (M) so that flipping the dipole with an electric field (E) also flips the magnetic moment. The collective magnetic spins of the atoms in the material encode the binary bits 0 and 1, and allow for information storage and logic operations. Credit: Ramamoorthy Ramesh lab, UC Berkeley

The magneto-electric spin-orbit or MESO devices will also pack five times more logic operations into the same space than CMOS, continuing the trend toward more computations per unit area, a central tenet of Moore’s Law.

The new devices will boost technologies that require intense computing power with low energy use, specifically highly automated, self-driving cars and drones, both of which require ever increasing numbers of computer operations per second.

“As CMOS develops into its maturity, we will basically have very powerful technology options that see us through. In some ways, this could continue computing improvements for another whole generation of people,” said lead author Sasikanth Manipatruni, who leads hardware development for the MESO project at Intel’s Components Research group in Hillsboro, Oregon. MESO was invented by Intel scientists, and Manipatruni designed the first MESO device.

Transistor technology, invented 70 years ago, is used today in everything from cellphones and appliances to cars and supercomputers. Transistors shuffle electrons around inside a semiconductor and store them as binary bits 0 and 1.

In the new MESO devices, the binary bits are the up-and-down magnetic spin states in a multiferroic, a material first created in 2001 by Ramamoorthy Ramesh, a UC Berkeley professor of materials science and engineering and of physics and a senior author of the paper.

“The discovery was that there are materials where you can apply a voltage and change the magnetic order of the multiferroic,” said Ramesh, who is also a faculty scientist at Lawrence Berkeley National Laboratory. “But to me, ‘What would we do with these multiferroics?’ was always a big question. MESO bridges that gap and provides one pathway for computing to evolve”

In the Nature paper, the researchers report that they have reduced the voltage needed for multiferroic magneto-electric switching from 3 volts to 500 millivolts, and predict that it should be possible to reduce this to 100 millivolts: one-fifth to one-tenth that required by CMOS transistors in use today. Lower voltage means lower energy use: the total energy to switch a bit from 1 to 0 would be one-tenth to one-thirtieth of the energy required by CMOS.

“A number of critical techniques need to be developed to allow these new types of computing devices and architectures,” said Manipatruni, who combined the functions of magneto-electrics and spin-orbit materials to propose MESO. “We are trying to trigger a wave of innovation in industry and academia on what the next transistor-like option should look like.”

Internet of things and AI

The need for more energy-efficient computers is urgent. The Department of Energy projects that, with the computer chip industry expected to expand to several trillion dollars in the next few decades, energy use by computers could skyrocket from 3 percent of all U.S. energy consumption today to 20 percent, nearly as much as today’s transportation sector. Without more energy-efficient transistors, the incorporation of computers into everything – the so-called internet of things – would be hampered. And without new science and technology, Ramesh said, America’s lead in making computer chips could be upstaged by semiconductor manufacturers in other countries.

“Because of machine learning, artificial intelligence and IOT, the future home, the future car, the future manufacturing capability is going to look very different,” said Ramesh, who until recently was the associate director for Energy Technologies at Berkeley Lab. “If we use existing technologies and make no more discoveries, the energy consumption is going to be large. We need new science-based breakthroughs.”

Paper co-author Ian Young, a UC Berkeley Ph.D., started a group at Intel eight years ago, along with Manipatruni and Dmitri Nikonov, to investigate alternatives to transistors, and five years ago they began focusing on multiferroics and spin-orbit materials, so-called “topological” materials with unique quantum properties.

“Our analysis brought us to this type of material, magneto-electrics, and all roads led to Ramesh,” said Manipatruni.

Multiferroics and spin-orbit materials

Multiferroics are materials whose atoms exhibit more than one “collective state.” In ferromagnets, for example, the magnetic moments of all the iron atoms in the material are aligned to generate a permanent magnet. In ferroelectric materials, on the other hand, the positive and negative charges of atoms are offset, creating electric dipoles that align throughout the material and create a permanent electric moment.

MESO is based on a multiferroic material consisting of bismuth, iron and oxygen (BiFeO3) that is both magnetic and ferroelectric. Its key advantage, Ramesh said, is that these two states – magnetic and ferroelectric – are linked or coupled, so that changing one affects the other. By manipulating the electric field, you can change the magnetic state, which is critical to MESO.

The key breakthrough came with the rapid development of topological materials with spin-orbit effect, which allow for the state of the multiferroic to be read out efficiently. In MESO devices, an electric field alters or flips the dipole electric field throughout the material, which alters or flips the electron spins that generate the magnetic field. This capability comes from spin-orbit coupling, a quantum effect in materials, which produces a current determined by electron spin direction.

In another paper that appeared earlier this month in Science Advances, UC Berkeley and Intel experimentally demonstrated voltage-controlled magnetic switching using the magneto-electric material bismuth-iron-oxide (BiFeO3), a key requirement for MESO.

“We are looking for revolutionary and not evolutionary approaches for computing in the beyond-CMOS era,” Young said. “MESO is built around low-voltage interconnects and low-voltage magneto-electrics, and brings innovation in quantum materials to computing.”

Leti, a research institute of CEA-Tech, and Silvaco Inc., a global provider of software, IP and services for designing chips and electronic systems for semiconductor companies, today announced during the IEDM 2018 conference a project to create innovative and unified SPICE compact models for the design of advanced circuits using nanowire and nanosheet technologies.

The new predictive and physical compact model under development, Leti-NSP, builds on Leti’s 15 years of model development, including the popular Leti-UTSOI model for FD-SOI technology. The Leti-NSP compact model uses a novel methodology for the calculation of the surface potential, including quantum confinement. The model is able to handle arbitrary cross-section shapes of stacked planar and vertical GAA MOSFETs (circular, square, rectangular). It provides an excellent tool for design exploration of nanowire and nanosheet device architectures.

This three-year collaboration will make the new device models available to designers through SmartSpiceTM, Silvaco’s high-performance parallel SPICE simulator for use by circuit designers. The corresponding model-parameters extraction flow will be implemented in Utmost IVTM, Silvaco’s database-driven environment for characterizing semiconductor devices, to ensure an accurate fit between simulated and measured device characteristics.

Accuracy of analysis at the nanometer scale is essential for co-optimization of silicon process technology and circuit performance. Besides accurate device characterization and simulation, a complete solution includes TCAD simulation, and 3D parasitic extraction. Silvaco’s partnership with leading research institutions for atomistic TCAD, and its proven in-house extraction solver technology, will provide the most accurate Design Technology Co-Optimization (DTCO) solution for nanometer technologies.

“Over two decades, CEA-Leti and Silvaco have collaborated on design-technology co-optimization, ranging from innovative TCAD simulation to the design of advanced nanoelectronics, and thus expanded and strengthened Silvaco’s suite of tools for designers,” said Emmanuel Sabonnadière, CEA-Leti CEO. “This project continues that partnership, andwhen these physics-based compact models are made available to designers worldwide, they will be able to evaluate the potential of advanced nanowire-based CMOS technologies under development at CEA-Leti.”

“DTCO, including circuit simulation, is fundamental to the development of electronic devices, and shrinking silicon geometries are placing an even greater premium on accuracy to capture and evaluate all the new physical effects in nanometer design,” said Eric Guichard, vice president of Silvaco’s TCAD Division. “Building on past successes of Leti and Silvaco’s collaboration, this project will provide circuit designers and technologists with powerful, advanced design flows that combine CEA-Leti’s physical, predictive, and easy-to-use models with Silvaco’s high-accuracy EDA tools.”

SEMI, the global industry association representing the electronics manufacturing supply chain, today reported that third quarter 2018 worldwide semiconductor manufacturing equipment billings dropped 5 percent from the previous quarter to US$15.8 billion but are 11 percent higher than the same quarter a year ago.

The data are gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

 
3Q2018
2Q2018
3Q2017
3Q18/2Q18
(Qtr-over-Qtr)
3Q18/3Q17
(Year-over-Year)
China
3.98
3.79
1.93
5%
106%
Korea
3.45
4.86
4.99
-29%
-31%
Taiwan
2.90
2.19
2.37
33%
23%
Japan
2.41
2.28
1.73
6%
40%
North America
1.27
1.47
1.50
-14%
-15%
Rest of World
0.98
0.96
0.74
2%
32%
Europe
0.85
1.18
1.06
-29%
-20%
Total
15.84
16.74
14.33
-5%
11%

Source: SEMI (www.semi.org) and SEAJ, December 2018

 

The Equipment Market Data Subscription (EMDS) from SEMI provides comprehensive market data for the global semiconductor equipment market.

Sanjay Mehrotra, President and CEO, Micron Technology, 2019 SIA Chair

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced the SIA Board of Directors has elected Sanjay Mehrotra, President and CEO of Micron Technology, Inc. (NASDAQ: MU), as its 2019 Chair and Keith Jackson, President, CEO, and Director of ON Semiconductor (NASDAQ: ON), as its 2019 Vice Chair.

“It is a great pleasure to welcome Sanjay Mehrotra as SIA’s 2019 Chair and Keith Jackson as SIA’s Vice Chair,” said John Neuffer, SIA President and CEO. “A design engineer by trade, Sanjay is a highly accomplished industry veteran and a leading voice on semiconductor technology. With more than 30 years of experience, Keith is a mainstay in our industry and a devoted champion for semiconductor priorities. Their combined skills and experience will be a tremendous asset to SIA as we pursue our industry’s interests in Washington and around the world.”

A 39-year veteran of the semiconductor industry, Mehrotra joined Micron in May 2017 after a long and distinguished career at SanDisk Corporation, where he led the company from a start-up in 1988 until its eventual sale in 2016. In addition to being a SanDisk co-founder, Mehrotra served as its President and CEO from 2011 to 2016, overseeing its growth to an industry-leading Fortune 500 company.

Prior to SanDisk, Mehrotra held design engineering positions at Integrated Device Technology, Inc., SEEQ Technology, and Intel Corporation. Mehrotra earned both bachelor’s and master’s degrees in electrical engineering and computer science from the University of California, Berkeley. He holds more than 70 patents and has published articles in the areas of non-volatile memory design and flash memory systems.

“The semiconductor industry is leading the greatest period of technological advancement in human history, making the seemingly impossible possible and opening up tremendous opportunities for economic growth,” said Mehrotra. “Driving innovation requires our industry to speak with one voice and promote policies that support our industry vision, and I look forward to helping lead that effort as 2019 SIA Chair.”

Jackson began serving as President, CEO, and Director of ON Semiconductor in November 2002. Before joining ON Semiconductor, he was with Fairchild, serving as Executive Vice President and General Manager, Analog, Mixed Signal, and Configurable Products Groups, and was head of its Integrated Circuits Group.

Previously, Jackson served as President and a Member of the Board of Directors of Tritech Microelectronics in Singapore and worked for National Semiconductor Corporation, most recently as Vice President and General Manager of the Analog and Mixed Signal division. He also held various positions at Texas Instruments Incorporated, including engineering and management positions, from 1973 to 1986. Mr. Jackson earned his bachelor’s and master’s degrees from Southern Methodist University.

“It is an honor to serve as 2019 SIA Vice Chair,” Jackson said. “Many issues of great importance to the semiconductor industry are being debated in Washington and around the world. We look forward to promoting policies that advance semiconductor technology and move our industry forward.”

 

IC Insights revised its outlook for total semiconductor industry capital spending and presented its forecast of semiconductor capex spending for individual companies in its November Update to The McClean Report 2018, which was released earlier this month.

Samsung is expected to have the largest capex budget of any IC supplier again in 2018.  After spending $24.2 billion for semiconductor capex in 2017, IC Insights forecasts that Samsung’s spending will edge slightly downward, but remain at a very strong level of $22.6 billion in 2018 (Figure 1).  If it comes in at this amount, Samsung’s two-year semiconductor capital spending will be an astounding $46.8 billion.

Figure 1

As seen in Figure 1, Samsung’s semiconductor capital outlays from 2010, the first year the company spent more than $10 billion in semiconductor capex, through 2016 averaged $12.0 billion per year. However, after spending $11.3 billion in 2016, the company more than doubled its 2017 capex budget. The fact that Samsung’s continued its strong capex spending in 2018 is just as impressive.

IC Insights believes that Samsung’s massive spending outlays in 2017 and 2018 will have repercussions far into the future.  One effect that has already begun is a period of overcapacity in the 3D NAND flash market.  This overcapacity situation is due not only to Samsung’s huge spending for 3D NAND flash, but also from spending by competitors (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) that attempt to keep pace in this market segment.

With the DRAM and NAND flash memory markets showing strong growth through the first three quarters of 2018, SK Hynix ramped up its capital spending this year.  In 1Q18, SK Hynix said that it intended to increase its capex spending by “at least 30%” this year. In the November Update, IC Insights forecasts that SK Hynix will see a 58% surge in its semi capex spending.  The increased spending by SK Hynix this year is focused primarily on bringing new capacity online at two of its large memory fabs—M15, a 3D NAND flash fab in Cheongju, South Korea, and the expansion of its huge DRAM fab in Wuxi, China. The Cheongju fab is being pushed to open before the end of this year.  The Wuxi fab is also targeted to open by the end of this year, a few months earlier than its original start date of early 2019.

Overall, IC Insights’ now forecasts total semiconductor industry capital spending will climb 15% to $107.1 billion this year, the first time that annual industry capex is expected to top $100.0 billion. Following the industry-wide growth this year, semiconductor capex is expected to decline 12% in 2019 (Figure 2).

Figure 2

Given that the current softness in the memory market is expected to extend into at least the first half of next year, the combined capital spending by the three largest memory suppliers—Samsung, SK Hynix, and Micron—is forecast to drop from $45.4 billion in 2018 to $37.5 billion in 2019, a decline of 17%.

In total, the top five spenders, which are expected to represent 66% of total outlays this year, are forecast to cut their capital spending by 14% in 2019 with the remaining semiconductor industry companies registering a 7% decline.

GLOBALFOUNDRIES today announced its advanced silicon germanium (SiGe) offering, 9HP, is now available for prototyping on the company’s 300mm wafer manufacturing platform. The move signifies the strong growth in data center and high-speed wired/wireless applications that can leverage the scale advantages of a 300mm manufacturing footprint. By tapping into GF’s 300mm manufacturing expertise, clients can take advantage of increased production efficiency and reproducibility for high-speed applications such as optical networks, 5G millimeter-wave wireless communications and automotive radar.

GF is the industry leader in the manufacturing of high-performance SiGe solutions on its 200mm production line in Burlington, Vermont. The migration of 9HP, a 90nm SiGe process, to 300mm wafers manufactured at GF’s Fab 10 facility in East Fishkill, N.Y., continues this leadership and establishes a 300mm foothold for further roadmap development, ensuring continued technology performance enhancements and scaling.

“The increasing complexity and performance demands of high-bandwidth communication systems have created the need for higher performance silicon solutions,” said Christine Dunbar, vice president of RF business unit at GF. “GF’s 9HP is specifically designed to provide outstanding performance, and in 300mm manufacturing will support our client’s requirements for high-speed wired and wireless components that will shape future data communications.”

GF’s 9HP extends a rich history of high-performance SiGe BiCMOS technologies designed to support the massive growth in extremely high data rates at microwave and millimeter-wave frequencies for the next generation of wireless networks and communications infrastructure, such asterabit-level optical networks, 5G mmWave and satellite communications (SATCOM) and instrumentation and defense systems. The technology offers superior low-current/high-frequency performance with improved heterojunction bipolar transistor (HBT) performance and up to a 35 percent increase in maximum oscillation frequency (Fmax) to 370GHz compared to its predecessors, SiGe 8XP and 8HP.

Client prototyping of 9HP on 300mm at Fab 10 in East Fishkill, N.Y. on multi-project wafers (MPWs) is underway now, with qualified process and design kits scheduled in 2Q 2019.