Category Archives: Device Architecture

Researchers at the Energy Department’s National Renewable Energy Laboratory (NREL) discovered single-walled carbon nanotube semiconductors could be favorable for photovoltaic systems because they can potentially convert sunlight to electricity or fuels without losing much energy.

The research builds on the Nobel Prize-winning work of Rudolph Marcus, who developed a fundamental tenet of physical chemistry that explains the rate at which an electron can move from one chemical to another. The Marcus formulation, however, has rarely been used to study photoinduced electron transfer for emerging organic semiconductors such as single-walled carbon nanotubes (SWCNT) that can be used in organic PV devices.

In organic PV devices, after a photon is absorbed, charges (electrons and holes) generally need to be separated across an interface so that they can live long enough to be collected as electrical current. The electron transfer event that produces these separated charges comes with a potential energy loss as the molecules involved have to structurally reorganize their bonds. This loss is called reorganization energy, but NREL researchers found little energy was lost when pairing SWCNT semiconductors with fullerene molecules.

“What we find in our study is this particular system — nanotubes with fullerenes — have an exceptionally low reorganization energy and the nanotubes themselves probably have very, very low reorganization energy,” said Jeffrey Blackburn, a senior scientist at NREL and co-author of the paper “Tuning the driving force for exciton dissociation in single-walled carbon nanotube heterojunctions.”

The paper appears in the new issue of the journal Nature Chemistry. Its other co-authors are Rachelle Ihly, Kevin Mistry, Andrew Ferguson, Obadiah Reid, and Garry Rumbles from NREL, and Olga Boltalina, Tyler Clikeman, Bryon Larson, and Steven Strauss from Colorado State University.

Organic PV devices involve an interface between a donor and an acceptor. In this case, the SWCNT served as the donor, as it donated an electron to the acceptor (here, the fullerene). The NREL researchers strategically partnered with colleagues at Colorado State University to take advantage of expertise at each institution in producing donors and acceptors with well-defined and highly tunable energy levels: semiconducting SWCNT donors at NREL and fullerene acceptors at CSU. This partnership enabled NREL’s scientists to determine that the electron transfer event didn’t come with a large energy loss associated with reorganization, meaning solar energy can be harvested more efficiently. For this reason, SWCNT semiconductors could be favorable for PV applications.

Researchers at the Energy Department’s National Renewable Energy Laboratory (NREL) have uncovered a way to overcome a principal obstacle in using two-dimensional (2D) semiconductors in electronic and optoelectronic devices.

2D semiconductors such as molybdenum disulfide are only a few layers thick and are considered promising candidates for next-generation devices. Scientists first must overcome limitations imposed by a large and tunable Schottky barrier between the semiconductor and a metal contact. The barrier, at the metal/semiconductor junction, creates an obstacle for the flow of electrons or holes through the semiconductor.

The NREL team discovered that the height of the Schottky barrier can be adjusted-or even made to vanish-by using certain 2D metals as electrodes. Such adjustments are not possible with conventional three-dimensional metals because of a strong Fermi level pinning (FLP) effect occurring at the junction of metal and semiconductor, due to electronic states in the semiconductor band gap that are induced by the metal. Increasing the flow of electrons or holes through a semiconductor reduces power losses and improves the device performance.

The NREL theorists considered a family of 2D metals that could bind with the 2D semiconductors through van der Waals interaction. Because this interaction is relatively weak, the metal-induced gap states are suppressed and the FLP effect is negligible. This means that the Schottky barrier becomes highly tunable. By selecting an appropriate 2D metal/2D semiconductor pair, one can reduce the barrier to almost zero (such as H-NbS2/WSe2 for hole conduction).

They noted that using a 2D metal as an electrode would also prove useful for integrating into transparent and flexible electronics because the 2D metal is also transparent and flexible. They also noted that the junction of 2D metal and 2D semiconductor is atomically flat and can have fewer defects, which would reduce carrier scattering and recombination.

The work by Yuanyue Liu, Paul Stradins, and Su-Huai Wei, “Van der Waals metal-semiconductor junction: weak Fermi level pinning enables effective tuning of Schottky barrier,” appears in the new issue of Science Advances.

The trio of researchers predicts that hexagonal phase of niobium disulfide (NbS2) is the most promising for hole injection into a 2D semiconductor, and heavily nitrogen-doped graphene can enable efficient electron injection.

IC Insights’ April Update to the 2016 McClean Report, to be released later this week, includes IC Insights’ final 2015 top 50 company rankings for total semiconductor and IC sales as well as rankings of the leading suppliers of DRAM, flash memory, MPUs, IC foundry services, etc.

Figure 1 ranks the top 13 IC foundries (pure-play and IDM) by foundry sales in 2015.

Apple TSMC sales

TSMC, by far, was the leader with $26.4 billion in sales last year.  In fact, TSMC’s 2015 sales were over 5x that of second-ranked GlobalFoundries (even with the addition of IBM’s chip business in the second half of 2015) and almost 12x the sales of the fifth-ranked China-based foundry SMIC.  As shown, there are only two IDM foundries in the ranking—Samsung and Fujitsu—after IBM and Magnachip fell from the list in 2015.  Despite losing a significant amount of Apple’s business, Samsung easily remained the largest IDM foundry last year, with more than 3x the sales of Fujitsu, the second-largest IDM foundry.

Illustrating the dramatic effect of exchange rate fluctuations on the IC sales numbers, TSMC’s 2015 growth rate was about half (6%) of what it was in its local currency (11%).  Thus, while the company met its stated goal of 10% or better growth in 2015 in NT dollars (840.5 billion), its growth rate in U.S. dollars was only 6%.

Driving home just how important Apple’s foundry business is, TSMC’s foundry sales increased by $1,464 million last year while its sales to Apple jumped by $1,990 million, representing more than 100% of TSMC’s total foundry sales increase in 2015.  As a result, without Apple, TSMC’s foundry sales would have declined by 2% last year, eight points less than the 6% increase it logged when including Apple.

Second ranked GlobalFoundries took over IBM’s IC business in early July of 2015.  It should be noted that besides $515 million in IDM foundry sales IBM made in 2014, the company also had about $1.0 billion of internal transfer IC revenue that year.  As a result, GlobalFoundries’ quarterly sales in 4Q15 were about $1.4 billion, an annual run-rate of $5.6 billion, about 12% greater than the company’s 2015 sales of $5.0 billion. However, without the addition of IBM’s sales in the second half of last year, GlobalFoundries’ sales would have declined by 2% in 2015.

Sales from the top 13 foundries’ shown in Figure 1 were $46.7 billion and represented 93% of the $50.3 billion in total foundry sales in 2015.  This share was two points higher than the 91% share the top 13 represented two years earlier in 2013.  With the barriers to entry (e.g., fab costs, access to leading edge technology, etc.) into the foundry business being so high and rising, IC Insights expects this “top 13” marketshare figure to continue to slowly rise in the future.

Spintronic majority gates could revolutionize circuit design. They will completely change the paradigm – both at device and circuit level – in how to approach scaling.

BY IULIANA RADU and AARON THEAN, imec, Leuven, Belgium

Spin logic devices are an emerging beyond-CMOS technology that may push beyond Moore’s law, enabling functional scaling beyond the 5nm technology node. These exotic devices lend themselves to majority logic operation, which differs in many ways from the classical NAND-based operation. Imec looks into spin torque majority gates and spin wave majority gates, two concepts that completely change the way we think of computing and scaling. As shown at the 2015 IEDM conference, circuit simulations with these majority gates outperform equivalent CMOS circuits in terms of area and power consumption. Meanwhile, experimental work has been started to learn about the materials, about the devices behavior and about the technology challenges that lie ahead.

Spintronic majority gates, an efficient way to build circuits

As we approach 5nm logic technology in 2020, CMOS device density scaling faces serious challenges due to escalating process costs and parasitics. This inevitably leads to questions of sustainability of traditional Moore’s law where cost and data processing supposedly scale favorably with increasing device density. This begs the question: are there specialized devices and computational paradigms out there that break away from these fundamental trappings of CMOS scaling? The search is on and novel beyond-CMOS devices are being intensively studied.

This varied class of devices may enhance and complement the functionality of CMOS circuits. Among the promising concepts are spintronic devices (FIGURE 1), which exploit the electron’s spin, a quantum attribute that relates to magnetism, rather than its charge to perform logic operations. Spin logic devices promise to be non-volatile and lend themselves to ultralow-energy operation. But one of their biggest trumps is the ability to build majority gates, ‘democratic’ devices that return true if more than 50% of their inputs are true. For example, if two inputs are in a true state and a third one is in a false state, the expected state at the output is true. With these majority gates, logic AND and OR operations can be emulated. Also, this concept of majority logic operation differs in many ways from the classical NAND-based logic, where an output is false only if all its inputs are true. It presents a concept shift that completely changes the way we synthesize circuits. But the advantages are huge: majority gates enable arithmetic circuits that are much more compact and energy-efficient than conventional NAND or XOR gate-based circuits. For example, while a one-bit adder in CMOS technology requires about 25 transistors, the equivalent wave computing circuit only requires 5 transducers and 4 waveguides to perform the same operation.

Screen Shot 2016-04-26 at 3.49.09 PM

Two ways of encoding information

Spintronic majority gates can come in several flavors, differing in the way the information is encoded and processed in the device, and in the way transduction from the charge domain to the spin (magnetism) domain is executed. At imec, two concepts are studied extensively: the spin torque majority gate (STMG) and the spin wave majority gate (SWMG).

In a STMG, the information is encoded in magnetic domain walls. Domain walls are interfaces that separate regions with different magnetization direction. The majority gate itself consists of a cross-shaped free layer that is common to 4 magnetic tunnel junctions (3 inputs, 1 output). The magnetization direction of the 3 ‘input’ free layers is switched using spin transfer torque, provided by a current through each of the magnetic tunnel junctions. Based on quantum interactions between electrons known as exchange, the domain walls propagate and interact, and the majority magnetization direction wins. The output state is measured via tunneling magnetoresistance.

In a SWMG, the computation principle is based on the interference of spin waves. The information can be encoded either in the amplitude or in the phase of the waves. Spin waves are low-energy collective excita- tions in magnetic materials. They can be generated by a so-called magneto-electric cell, which converts voltage into a spin wave. Key elements of this cell are a piezoelectric layer (that converts voltage into strain) and a magnetostrictive layer (in which the strain produces a change in magnetization or magne- tization anisotropy). In its turn, the change in magne- tization can generate a spin wave in a magnetic spin wave bus. The same cell is used to read the output state of the majority gate (FIGURE 2).

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Both concepts have been studied intensively, and approaches of how to handle the computation have been proposed. An experimental demonstration is however still missing. At imec, we have enlarged our basic understanding of both STMG and SWMG and used simulations to validate device functioning. We have compared the two types of majority gates against equivalent circuits in 10nm FinFET CMOS technology. And we present our first experimental results, and highlight the main challenges for both concepts.

Spin torque majority gate – compact and technology friendly

We used micromagnetic simulations to validate the functioning of the STMG and identify its operating conditions. For this majority gate, the switching of the magnetization state is current controlled. If the applied current or the pulse length are not enough, the output fails to switch. Even if the applied current pulses provide enough energy to switch, other failure modes can appear. For example, the domain walls that are being formed can become ‘stuck’ at the crossing of the device. This happens when the width of the cross exceeds a certain value, typically in the 15-20nm range. This makes these devices difficult to demonstrate experimentally as it requires patterning and etching to small size and tight pitch between the magnetic tunnel junctions. However, this initial impediment holds great promise for further device scaling. A major advantage of this majority gate is the use of technology friendly materials, compa- rable to the materials used in magnetic memories.

We have benchmarked the device against equivalent 10nm CMOS circuits by comparing key metrics of area, power and delay. On average, the STMG circuits have about 10x smaller area, and provide a means for further scaling. However, being current controlled, the STMG circuits have a longer delay, making them less efficient than equivalent CMOS circuits. Further advances in materials stacks are needed to improve their performance, comparable to those needed in general for magnetic memory.

At imec, we are currently building the first STMG devices on 300mm wafers. Particular attention is paid to the magnetic tunnel junction pillar etch development (FIGURE 3).

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Spin wave majority gate – compact, ultralow-power but challenging materials

We used micromagnetic simulations to model the spin wave propagation in SWMGs and to simulate the magnetic behavior of the magneto-electric cell that converts the applied voltage into a spin wave. This cell is a critical component for the device functionality. We mapped out the parameter space where the magneto-electric cell is expected to work optimally and used these parameter ranges as input for circuit synthesis. Building magneto- electric cells experimentally is very challenging as the materials to be used are not typically used in standard fabs and cleanrooms. For this reason, and to help choose the right materials, we have performed circuit synthesis and benchmarked them against CMOS. Based on materials parameters extracted from these simulations we have chosen a starting set of materials for our experiments.

One of the questions to be answered is how piezoelectrics behave at very high frequencies (gigahertz range) as needed for logic devices. Piezoelectric materials are being used in many applications, where they typically operate at low frequencies (up to hundreds of kHz). At imec, we started first experiments to grow piezoelectric materials in a thin film and to learn how these materials behave in the high frequency domain. And although more experiments are needed to improve the performance and map out the reliability behavior, our preliminary results are very encouraging. An important drawback of the spin wave technology is that the required materials (both the magnetostrictive and the piezoelectric materials) are very different from standard CMOS materials (FIGURE 4).

Screen Shot 2016-04-26 at 3.49.49 PM

The spin wave technology was also benchmarked against CMOS circuits. The spin wave circuits take on average 3.5 times less area and about 400 times lower power than their CMOS counterparts. However, the spin wave circuits are on average 12 times slower, mainly because of the large switching delay of the magneto-electric cell. SWMGs may therefore be used for ultralow-power applications, where latency is a secondary consideration (FIGURE 5).

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Building arithmetic circuits on top of CMOS

Spintronic majority gates could revolutionize circuit design. They will completely change the paradigm – both at device and circuit level – in how to approach scaling. In the future, more experimental work is planned to learn about the new materials required, to validate circuit assessment, and to finally demonstrate functional devices.

Once these technologies have become more mature, we can start thinking of multi-device architectures that combine CMOS-based and spin logic devices. An interesting approach is to stack, on top of CMOS technology, arithmetic circuits made of spintronic majority gates. The high-performance functions could be executed by the CMOS-based devices and the ultralow-power functions by the spin logic arithmetic circuits. So, rather than replacing Si CMOS based transistors in the future, this beyond-CMOS technology is intended to enhance and complement the functionality of CMOS-based devices.

Spintronics belongs to the beyond-CMOS segment, where we look into new materials and device architectures, and even into new computing paradigms and circuits. Beyond-CMOS research is part of imec’s multiple roadmap scenario that is built around 3 pillars: Si extension, beyond Si and beyond CMOS. Each of these segments has its own mission and approach to enabling scaling. And each of the new technologies will bring in enabling modules and devices that will serve the application diversity in the new era of electronics: the internet of things. And the results will support the quest of the semiconductor industry to find solutions that enable continual functional scaling of cost and energy per bit by departing from the familiar CMOS scaling.

Suggested additional reading

1. Spintronic majority gates, I. P. Radu et al., IEDM 2015 (https://www.researchgate.net/publication/286882975_ Spintronic_Majority_Gates)

2. Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS, O. Zografos et al., Proceedings of the 15th International IEEE Conference on Nanotechnology (NANO), 2015(http://infoscience.epfl.ch/ record/211004)

3. “With our multiple roadmap scenario, we anticipate the appli- cation diversity in the new Era of Electronics”, imec annual overview 2015, vision by Aaron Thean (click on the name of Aaron at http://magazine.imec.be/data/80/reader/reader. html?t=1452505511353#!preferred/1/package/80/pub/86/ page/8)

IULIANA RADU is a program manager and AARON THEAN is the Vice President of Process Technologies and the Director of the Logic Devices Research at imec, Leuven, Belgium.

Cadence Design Systems, Inc. (NASDAQ:  CDNS) today announced that, Geoff Ribar, senior vice president and chief financial officer, who joined the company in 2010, has decided to retire from Cadence effective March 31, 2017.

Cadence has initiated a comprehensive search to identify the company’s next chief financial officer.  Mr. Ribar is working with Cadence president and chief executive officer Lip-Bu Tan in the search process. Once the new chief financial officer is appointed, Mr. Ribar will work collaboratively on the transfer of responsibilities and remain actively involved with Cadence through his retirement date.  After retiring next year, Mr. Ribar looks forward to remaining active in the technology and semiconductor industries through board memberships and other professional activities.

Lip-Bu Tan, president and CEO, said, “Geoff has been a tremendous partner to me and the company over the past five and a half years.  As an integral member of the leadership team, he has driven us forward and made long-lasting contributions to the company.  During Geoff’s tenure, we have consistently met or exceeded our financial objectives, improved both our operating margin and cash flow, strengthened the balance sheet, and optimized our return of capital.  Geoff has done an outstanding job of executing on the strategy and management philosophy that the Board and I have put in place, and has built a strong finance team.  Geoff’s departure is bittersweet for all of us, and I congratulate him on a successful career as a CFO and wish him well in the next chapter of his professional life.”

“It has been an honor to serve as CFO of Cadence and I’m extremely grateful for the support of my colleagues and the talented extended team,” said Mr. Ribar. “I also want to thank Lip-Bu for his leadership and trust. I am fully committed to ensuring a smooth transition and maintaining our excellent momentum throughout this transition process.”

North America-based manufacturers of semiconductor equipment posted $1.38 billion in orders worldwide in March 2016 (three-month average basis) and a book-to-bill ratio of 1.15, according to the March Equipment Market Data Subscription (EMDS) Book-to-Bill Report published today by SEMI.  A book-to-bill of 1.15 means that $115 worth of orders were received for every $100 of product billed for the month.

SEMI reports that the three-month average of worldwide bookings in March 2016 was $1.38 billion. The bookings figure is 9.4 percent higher than the final February 2016 level of $1.26 billion, and is 0.9 percent lower than the March 2015 order level of $1.39 billion.

The three-month average of worldwide billings in March 2016 was $1.20 billion. The billings figure is 0.5 percent lower than the final February 2016 level of $1.20 billion, and is 5.3 percent lower than the March 2015 billings level of $1.27 billion.

“Order activity remains steady and is on par with both the previous quarter and one year ago,” said Denny McGuirk, president and CEO of SEMI. “3D NAND and advanced logic are the key drivers for investments.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
October 2015

$1,358.6

$1,325.6

0.98
November 2015

$1,288.3

$1,236.6

0.96
December 2015

$1,349.9

$1,343.5

1.00
January 2016

$1,221.2

$1,310.9

1.07
February 2016 (final)

$1,204.4

$1,262.0

1.05
March 2016 (prelim)

$1,198.5

$1,380.5

1.15

Source: SEMI (www.semi.org), April 2016

Park Systems announced today the appointments of Charlie Park as Senior Vice President of Global Sales, and Jong-Pil Park as Vice President of Production.

“The addition of these highly talented executives is a continuation of Park’s strategic business focus on global expansion,” states Dr. Sang-il Park, Park Systems Founder and CEO. “The new appointments establish the groundwork for an integrated world-wide targeted sales operation and will jointly aggressively increase our production capabilities to meet anticipated product demands.”

Charlie Park’s role as Senior Vice President of Global Sales will focus on further establishing Park Systems trademarked global Atomic Force Microscope (AFM) brand. He brings over three decades of global sales and marketing experience at leading companies including Samsung Electronics where during his tenure as Senior VP he expanded global operations, leading the sales & marketing divisions in both the Korean and European Headquarters. He has had numerous global assignments in the UK, Germany and the Netherlands and will use his successful global sales experience to implement Park’s long-term strategy for growth and innovation leadership in Atomic Force Microscopes.

Jong-Pil Park, PhD-ME, newly appointed Vice President of the Production Division will expand the highly successful production capabilities of Park AFM with quality-driven state-of-the-art systems and leading-edge performance capabilities. His successful 30 year career as an engineering-based expert in production and quality management include operations vice president at Motorola Korea, production VP at Doosan Infracore Co and at Huneed Technologies Company, and a senior engineer at Defense Technology & Quality. His leadership skills combined with technical knowledge of automated atomic force microscope equipment will expand Park Systems world-renowned production systems to meet the AFM needs for an expanding world market.

ams AG (SIX: AMS) today took a step forward in its long-term strategy of increasing manufacturing capacity for its high-performance sensors and sensor solution integrated circuits (ICs), holding a groundbreaking event at the site of its new wafer fabrication plant in Utica, New York.

An artist’s rendering of a semiconductor fab at the Marcy site.

The ceremony featured New York Lieutenant Governor Kathy Hochul, Utica Mayor Robert Palmieri, local dignitaries and senior executives from ams and SUNY Polytechnic Institute.

ams sensor solutions are relied upon globally by manufacturers of smartphones, tablets and other communications devices, automakers, audio and medical equipment manufacturers and others. ams sensors are used in hundreds of millions of devices to recognize light, color, gestures, images, motion, position, environmental and medical parameters and more.

With construction work now underway on the new fab, ams remains on track to reach its target for the first batches of wafers made at the plant in the first half of 2018.

Production capacity at the Utica fab will supplement ams’ existing 180nm and 350nm CMOS and SiGe fab at its headquarters near Graz, Austria. Adding this additional volume to its in-house chip manufacturing facilities positions ams to meet the forecasted growth in demand for its high-performance sensor solution ICs.

New York Governor Andrew Cuomo has made public-private partnerships an important part of this  Nano Utica initiative, which exceeds 4,000 projected jobs over the next decade. Designed to replicate the dramatic success of SUNY Poly’s Nanotech Megaplex in Albany, NANO Utica further cements New York’s international recognition as the preeminent hub for 21st century nanotechnology innovation, education, and economic development.

The Governor says the addition of ams and others to Nano Utica is creating an economic revolution around nano-technology in the Mohawk Valley region, and that the economy there is “gathering momentum unlike ever before.”

The new fab, which is being built to ams’s specifications and which ams will operate under a 20-year lease, is expected initially to offer capacity of at least 150,000 200mm-wafer equivalents per year. Planned expansion thereafter will eventually see the plant operating at a capacity of more than 450,000 200mm-wafer equivalents per year.

The new fab is located close to a campus of SUNY Polytechnic Institute in New York’s Tech Valley, the largest region focused on technology manufacturing in the US and home to other nanotechnology and semiconductor companies. The fab will be capable of producing wafers at the 130nm node, and more advanced nodes in the future.

Today’s celebratory event at the new fab site also marked the success of the partnership behind the project to build, equip and operate another high-technology manufacturing facility in the State of New York. This partnership has benefited from a wide-ranging collaboration between public sector bodies such as the New York governor’s office, the City of Utica and the State University of New York, and various private sector institutions including ams, the fab’s sole leaseholder.

Approximately 250 people gathered at the construction site to see Lt. Governor Hochul and ams CEO Alexander Everke break ground for the foundation of what will be, on completion in 2018, one of the world’s largest analog wafer fabs.

“Building this new wafer fab enables ams to achieve its plans for growth and to meet the increasing demand for sensor solutions produced at advanced manufacturing nodes. Our decision to locate the facility in New York was motivated by the availability of a highly skilled workforce, the proximity to prestigious educational and research institutions, and the favorable business environment, backed by public and private partners,” Mr. Everke said. “What we will create together in Utica will be the most productive ‘More than Moore’ fab worldwide,” he added.

Whether it’s the Internet of Things (IoT), wearables, or industrial automation, new devices and applications are portable, battery-operated and require continuous power.  Wireless connectivity is required for connecting to the Internet.  Today’s devices collect and transmit data from sensors, are always or almost always on and require power.  The semiconductor industry has met the challenge to design devices for low power operation.  But eventually batteries still run out of energy and have to be replaced or recharged.  Energy harvesting can extend battery life or possibly replace batteries altogether for continuous operation.  The new Semico Research report “Energy Harvesting: The Next Billion Dollar Market for Semiconductors” projects semiconductor sales for this market will reach $3 billion by 2020.

An energy harvesting solution requires more than just the energy harvester or transducer.  The key components include a power converter, power management IC (PMIC), MCU, and energy storage.  “An ecosystem of semiconductor vendors is emerging for the nascent energy harvesting market,” says Tony Massimini, Semico Research’s Chief of Technology.  “The ecosystems are gravitating around the vendors of key power components.  They are forming partnerships with producers of energy harvesters, battery suppliers, and other components.”

This study examines the market opportunity for energy harvesting outside of large installations and commercial power generation.  A broad range of markets will employ energy harvesting to either replace batteries or extend battery life. These applications cover wireless sensor nodes (WSN) for bridges, infrastructure, building automation and controls, and home automation (including lighting, security and environmental). Energy harvesting will grow in automotive applications, cell phones, wearables and other consumer electronics.

“The vendors of MCUs, sensors, RF, analog and other components will continue to develop lower power devices”, according to Massimini. “While this puts less drain on a battery and will extend its life, it also lessens the load for an energy harvesting solution.  Energy harvesting solutions are also expected to improve during the forecast period.”

The ASPs for the semiconductor components continue to decline, lowering the costs for an energy harvesting solution.  This is driving higher penetration rates.

Key findings of the report include:

  • The number of energy harvesting solutions will grow to 777 million units by 2020 (CAGR ’15 to ’20 = 80.6%).
  • Smartphone market will become the largest by volume by 2020.
  • WSN in commercial and industrial applications, including bridges, will be the second largest market by 2020
  • Semiconductor revenues in Energy Harvesting will reach $3 billion by 2020(CAGR ’15 to ’20 = 71.4%).

In its recent report “Energy Harvesting: The Next Billion Dollar Marketfor Semiconductors” (MP112-16), presents the market for energy harvesting by key end use markets and the semiconductor content.  Readers will see which market segment is growing fastest and which semiconductor components account for sales potential.  The report discusses the latest trends in energy harvesting, the growing ecosystem, and technical innovations.  Included are profiles of silicon vendors involved with energy harvesting and other key vendors in the ecosystem. The report is 70 pages long and includes 11 tables and 24 figures.

Companies cited in the report: Analog Devices, Atmel, Audience, Cherry Switches, Cymbet, Cypress, enOcean, Linear Technology, Maxim Integrated, Microchip Technology, NXP, Powercast, Renesas, Semtech, Silicon Labs, Silicon Reef, STmicroelectronics, Texas Instruments, Imprint Energy, Sakti3, Solid Power, Apple, Laird, MicroGen, Micropelt, Thermo Life, Thermogen Technologies, Sanyo, EnerBee, Energy Harvesters, K3OPS, Nikola Labs and Imec.

This report is part of Semico Research’s IoT and MEMS portfolios, which also include:

The Smart Economy: The Internet of Everything

IoT Security: At What Cost?

Sensors in Wearables and Mobile: The Many Players

The Smart Home: Big Brother or Swarm Intelligence?

Reflecting the semiconductor industry’s ongoing transition from a focus on geometric scaling to the integration of heterogeneous technologies that will enable the future “smart society,” the annual Symposia on VLSI Technology & Circuits has announced its 2016 program around the theme “Inflections for a Smart Society.” Uniquely positioned at the intersection of IC technology development and the evolving strategies for advanced circuit architecture, the Symposia program will explore the future direction of the microelectronics industry for chipmakers, foundries, and academic researchers.

Focus sessions 

Focus sessions for both Symposia will explore different aspects of this theme. Technology focus sessions include “Systems & Embedded Memory” and “Interconnect & 3D Integration,” addressing the challenges of advanced device design. The Circuits focus sessions are “Industrial & Power Circuit Directions for a Smart Society” and “Innovative Systems for a Smart Society,” examining the development of sensors and power circuits for interconnected systems. Joint focus sessions shared by the Technology and Circuits program include “Smart Power,” “Analog/RF Integration & Design-technology Co-Optimization in CMOS,” “Embedded Memories,” and “Design in Scaled Technologies,” enabling participants from each of the Symposia to share ideas on the intersection of these critical technology areas.

Panel discussions 

Panel discussions provide an opportunity for Symposia participants to interact with leading industry experts in examining critical issues surrounding major industry developments. The Technology panel, “How Moore’s Law, Industry Consolidation and System Trends Are Shaping the Memory Roadmap,” will explore the technical and economic limits of DRAM and NAND Flash memories, along with the system requirements driving future memory technology.

Two Circuits panels approach the Symposia theme with topics focused on innovation and co-optimization at the circuit level, including “Top Circuit Techniques: Life With & Without Them,” which reviews high-impact circuit design techniques; while “It’s All A Common Platform – How Do I Build A Differentiated Product?” which examines how software and hardware co-design, user interface, and other innovations continue to drive competitive products at the circuit level.

A joint Technology & Circuits panel moderated by Professor Subramanian Iyer from UCLA debates the crucial question of how Moore’s Law is being adapted by the IC industry to new business opportunities in the IoT era, in a session titled “More Moore, More than Moore or Mo(o)re Slowly?” with a high profile panel composed of industry executives and experts.

Short Courses 

Full-day short courses by leading industry and academic experts precede each Symposia, enabling participants to more fully explore subjects related to the conference theme, including a Technology Short course, “Inflections in VLSI Technologies – Cloud & Beyond,” with sessions that cover high performance computing, silicon photonics, memory technologies, cloud computing and novel power devices.

Two Circuits short courses are offered, including “Advanced Wirelines Techniques,” which covers 28 – 56Gb/s design standards, low power CMOS, analog NRZ and silicon photonic transceivers, and integrated electronic-photonic communications circuits. A second short course, “Circuit Design in FinFET, FDSOI & Advanced Memory Technologies,” examines the impact of FinFETs in processor design, analog & mixed-signal CMOS and embedded memory designs; as well as UTBB FDSOI technology for SRAM and digital logic. (Short courses require a separate registration fee.)

This year, the annual Symposium on VLSI Technology and Circuits will be held at the Hilton Hawaiian Village, Honolulu, Hawaii from June 13-16, 2016 (Technology) and June 14-17, 2016 (Circuits). This year marks the 36th anniversary for the Symposium on VLSI Technology, and the 30th anniversary for the Symposium on VLSI Circuits. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan.

Sponsoring Organizations

The Symposium on VLSI Technology is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society.

The Symposium on VLSI Circuits is sponsored by the IEEE Solid State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers.

Further Information, Registration and complete program 
Visit: http://www.vlsisymposium.org.