Category Archives: Device Architecture

The Electronic System Design (ESD) Alliance (formerly the EDA Consortium) and Semico Research today announced that they have entered into a joint marketing agreement (JMA) to work together on several business initiatives in support of the semiconductor design ecosystem.

The JMA will enable the ESD Alliance and Semico, a semiconductor marketing and consulting research company noted for its coverage of the intellectual property (IP) market, to promote their common business goals. Semico will assist the ESD Alliance in broadening its reach into the IP community, a large part of the semiconductor design ecosystem, by promoting it at Semico events, on its website and through promotional emails.

Additionally, Semico will provide a discount to ESD Alliance members for purchase of individual research reports, offer enterprise-wide access to its IPI Monthly Report and extend admission discounts to Semico conference events.

In exchange, Semico has become an associate member of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem. The ESD Alliance will post availability of new Semico research reports and provide a link to its website for Semico blogs and articles.

“Semico is connected to and understands the needs of IP community,” says Bob Smith, the ESD Alliance’s executive director. “Our new mission is focused on representing the design ecosystem and IP is a key component. We will rely on its Semico’s expertise as we expand our presence and showcase our benefits to IP vendors and suppliers.”

“The ESD Alliance recognizes that the IP community is an important element of the semiconductor design ecosystem and one that will benefit from its newly expanded charter and ongoing initiatives,” notes Jim Feldham, president of Semico. “We look forward to working with the the ESD Alliance to raise the visibility of the importance of the IP market.”

For more information on other aspects of the ESD Alliance and Semico partnership, visit: www.esd-alliance.org or www.semico.com.

IC Insights recently released its new Global Wafer Capacity 2016-2020 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2020.  In 2008, 300mm wafers took over as the industry’s primary wafer size in terms of total surface area used. Furthermore, the number of 300mm wafer fabrication facilities in operation continues to grow and is expected to reach 100 this year (Figure 1).

Some highlights regarding 300mm wafer fabs are shown below.

•    A couple fabs that were scheduled to open in 2013 were delayed until 2014.  That, in conjunction with the closure of two large 300mm fabs by ProMOS in 2013, caused the number of active volume-production 300mm fabs to decline for the first time in 2013.

•    At the end of 2015, there were 95 production-class IC fabs utilizing 300mm wafers (there are numerous R&D IC fabs and a few high-volume fabs that make “non-IC” products such as CMOS image sensors using 300mm wafers, but these are not included in the count).

•    Currently, there are eight 300mm wafer fabs scheduled to open in 2017, which would be the highest single-year increase since 2014 when nine 300mm fabs were added.

•    By the end of 2020 there are expected to be 22 more 300mm fabs in operation, bringing the total number of 300mm fabs used for IC fabrication to 117.  If 450mm wafers enter production, the peak number of 300mm fabs may be somewhere around 125.  For comparison, the highest number of volume-production 200mm wafer fabs in operation was 210 (in December of 2015 there were 148).

Today’s 300mm wafer fabs can be huge, but they are being equipped in a modular format, with each “module” generally having the capacity to process somewhere around 25K-45K wafers per month.  Each module is closely connected to nearby fab modules.  TSMC has perfected this modular approach, with its Fab 12, 14, and 15 sites being expanded in phases.

Figure 1

Figure 1

Development of 450mm wafer technology continues to progress toward production, albeit at a tempered pace. Since lithography is one of the biggest challenges in the 450mm wafer transition, ASM Lithography’s announcement in March 2014 that it would temporarily hold off on the development of equipment for 450mm wafers made some in the industry believe it was a signal that the transition would never happen.  ASML reported also that the decision to postpone its 450mm development program was made at the request of its customers.

IC Insights does not believe that ASML’s announcement, along with a couple other signs of a pause in 450mm development, means the 450mm wafer transition won’t happen, but they do indicate that the pilot production status for 450mm won’t be reached until probably 2019.  Volume production might start two to three years after that.

IC Insights’ Global Wafer Capacity 2016-2020—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity report assesses the IC industry’s capacity by wafer size, minimum process geometry, technology type, geographic region, and by device type through 2020. The report includes detailed profiles of the companies with the greatest fab capacity and gives comprehensive specifications on existing wafer fab facilities.

Leti, an institute of CEA Tech, today announced the continuation of its collaboration with Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, to develop CoolCube, Leti’s new sequential integration technology that eliminates the need for through-silicon vias (TSVs) and enables the stacking of active layers of transistors in the third dimension.

The extended project’s goals include building a complete CoolCube ecosystem that takes the technology from design to fabrication.

CoolCube was created by Leti as a unique and innovative device scale-stacking technology that allows the design and fabrication of very high-density and high-performance circuits.

By introducing an innovative stacking process combined with low-temperature transistor processing, the technology allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.

Mobile devices, in which minimal power consumption is key, are the primary segment for chips manufactured with the CoolCube technology. It also enables designers to include back-side imagers in chips, and co-integration of NEMS in a CMOS fabrication process.

Launched in 2014 so that Qualcomm Technologies could evaluate CoolCube’s potential, the project achieved several breakthroughs and original design methodology that demonstrated that it can provide a concrete solution for true 3D chips.*

“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.”

As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs that will accelerate adoption of the technology.

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”

By James Hayward, Technology Analyst, IDTechEx

Last week, IDTechEx gave the opening presentation at the 2016 Korea Summit for Smart Wearable Devices, excellently hosted by KDIA and KSA in Seoul, Korea. Wearable sensors once again dominated discussion throughout the day, with latest examples of options in MEMS, textiles and more presented at length in the conference. Additional discussions throughout the day extended to topics like glucose sensing (including enzyme-free examples), sensor fusion and beyond.

Sensor development is driving the next generation of wearable devices, and this development is now going further than simply attaching sensors to devices that can be stuck on the body. Professor Mark Allen of the University of Pennsylvania gave a fascinating presentation about development of advanced MEMS for wearable devices. MEMS remains the dominant force in wearable sensing, but examples are now becoming broader than the increasingly commoditized, off-the-shelf and near ubiquitous IMU. IDTechExResearch’s bestselling report on the topic, “Wearable Sensors 2016-2026: Market Forecasts, Technologies, Players” finds that IMUs continue to dominate the wearable sensing space, counting for almost half of the total wearable sensor shipments in 2016.

The majority of wearable sensors today are found placed on the body within devices. One step further involves inserting sensors more permanently, whether via something like a skin patch that can be worn for weeks or months at a time, or to use Professor Allen’s example from work at Georgia Tech, magnetometers to detect motion of a magnetic stud inserted as a tongue piercing. Here, the use case is to enable patients suffering significant paralysis to other areas of the body to control an electric wheelchair using the tongue. The next step is to ingest sensors – Proteus Digital Health provide perhaps the most popularized example here, but devices like pill cameras are also regularly used in the diagnostic and clinical trial settings. The next steps involve the full implantation of a sensor, either permanently or through a planned lifetime followed by degradation.

Professor Allen spoke of some of their recently FDA approved work towards implantable sensors for intra cardiac pressure sensing. By fabricating a MEMS devices using ceramics, they created a biologically stable sensor that can be inserted inside the heart in high-risk patients to enable predictive diagnosis and treatment of heart disease. With the group prolifically producing new work, one area is looking at using a core-shell structure to make biodegradable sensors that can maintain structure and communication for a useful lifetime before dissolving. Sensor development is constantly improving the value proposition in many wearable and implantable products, producing state-of-the-art products for the medical space in particular.

IDTechEx Research covers all of the main types of wearable sensors found in products today, as well as sensors of the future in their report “Wearable Sensors 2016-2026: Market Forecasts, Technologies, Players“. The report groups sensors in prominent categories. For each sensor, the technologies and major players are described, backed up by detailed interviews and company profiles of key bodies in each sector. The report also views the big picture, discussing the implications of sensor fusion and the relative merits of each sensor type for various applications. This extensive primary research is used to produce detailed market forecasts for each sensor type over the next decade. Market data is provided for the growth of each sensor type, and is used to illustrate key trends that are observable in various application sectors.

sensors

The global semiconductor materials market decreased 1.5 percent in 2015 compared to 2014 while worldwide semiconductor revenues decreased 0.2 percent. The impact of exchange rate changes, coupled with lower overall semiconductor unit growth, contributed to the year-over-year revenue decline.

According to the SEMI Material Market Data Subscription, Total wafer fabrication materials and packaging materials were $24.1 billion and $19.3 billion, respectively. Comparable revenues for these segments in 2014 were $24.2 billion for wafer fabrication materials and $19.8 billion for packaging materials. The wafer fabrication materials segment decreased 1 percent year-over-year, while the packaging materials segment decreased 2 percent. However, if bonding wire were excluded from the packaging materials segment, the segment would have remained flat relative to last year. The continuing transition to copper-based bonding wire from gold is negatively impacting overall packaging materials revenues. The depreciation of the Yen further impacted the total materials market due to the importance of materials suppliers based in Japan.

For the sixth consecutive year, Taiwan was the largest consumer of semiconductor materials due to its large foundry and advanced packaging base, totaling $9.4 billion. Korea rose in the rankings to claim the second spot during the same time. Annual revenue growth was the strongest in the Korean and Chinese markets. The materials market in North America and Europe experienced nominal growth of 1 percent, while the materials markets in Taiwan, Rest of World and Japan contracted. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.)

2014 and 2015 Regional Semiconductor Materials Markets (US$ Billions)

Region 2014 2015 % Change
Taiwan

9.60

9.41

-2%

South Korea

7.03

7.16

2%

Japan

7.01

6.57

-6%

Rest of World

6.39

6.05

-5%

China

6.01

6.12

2%

North America

5.00

5.04

1%

Europe

3.01

3.05

1%

Total

44.04

43.40

-1%

Source: SEMI, April 2016

The transistor is the most fundamental building block of electronics, used to build circuits capable of amplifying electrical signals or switching them between the 0s and 1s at the heart of digital computation. Transistor fabrication is a highly complex process, however, requiring high-temperature, high-vacuum equipment.

Now, University of Pennsylvania engineers have shown a new approach for making these devices: sequentially depositing their components in the form of liquid nanocrystal “inks.”

Their new study, published in Science, opens the door for electrical components to be built into flexible or wearable applications, as the lower-temperature process is compatible with a wide array of materials and can be applied to larger areas.

The researchers’ nanocrystal-based field effect transistors were patterned onto flexible plastic backings using spin coating but could eventually be constructed by additive manufacturing systems, like 3-D printers.

The study was lead by Cherie Kagan, the Stephen J. Angello Professor in the School of Engineering and Applied Science, and Ji-Hyuk Choi, then a member of her lab, now a senior researcher at the Korea Institute of Geoscience and Mineral Resources. Han Wang, Soong Ju Oh, Taejong Paik and Pil Sung Jo of the Kagan lab contributed to the work. They collaborated with Christopher Murray, a Penn Integrates Knowledge Professor with appointments in the School of Arts & Sciences and Penn Engineering; Murray lab members Xingchen Ye and Benjamin Diroll; and Jinwoo Sung of Korea’s Yonsei University.

The researchers began by taking nanocrystals, or roughly spherical nanoscale particles, with the electrical qualities necessary for a transistor and dispersing these particles in a liquid, making nanocrystal inks.

Kagan’s group developed a library of four of these inks: a conductor (silver), an insulator (aluminum oxide), a semiconductor (cadmium selenide) and a conductor combined with a dopant (a mixture of silver and indium). “Doping” the semiconductor layer of the transistor with impurities controls whether the device transmits a positive or negative charge.

“These materials are colloids just like the ink in your inkjet printer,” Kagan said, “but you can get all the characteristics that you want and expect from the analogous bulk materials, such as whether they’re conductors, semiconductors or insulators.

“Our question was whether you could lay them down on a surface in such a way that they work together to form functional transistors.”

The electrical properties of several of these nanocrystal inks had been independently verified, but they had never been combined into full devices.

“This is the first work,” Choi said, “showing that all the components, the metallic, insulating, and semiconducting layers of the transistors, and even the doping of the semiconductor could be made from nanocrystals.”

Such a process entails layering or mixing them in precise patterns.

First, the conductive silver nanocrystal ink was deposited from liquid on a flexible plastic surface that was treated with a photolithographic mask, then rapidly spun to draw it out in an even layer. The mask was then removed to leave the silver ink in the shape of the transistor’s gate electrode. The researchers followed that layer by spin-coating a layer of the aluminum oxide nanocrystal-based insulator, then a layer of the cadmium selenide nanocrystal-based semiconductor and finally another masked layer for the indium/silver mixture, which forms the transistor’s source and drain electrodes. Upon heating at relatively low temperatures, the indium dopant diffused from those electrodes into the semiconductor component.

“The trick with working with solution-based materials is making sure that, when you add the second layer, it doesn’t wash off the first, and so on,” Kagan said. “We had to treat the surfaces of the nanocrystals, both when they’re first in solution and after they’re deposited, to make sure they have the right electrical properties and that they stick together in the configuration we want.”

Because this entirely ink-based fabrication process works at lower temperatures than existing vacuum-based methods, the researchers were able to make several transistors on the same flexible plastic backing at the same time.

“Making transistors over larger areas and at lower temperatures have been goals for an emerging class of technologies, when people think of the Internet of things, large area flexible electronics and wearable devices,” Kagan said. “We haven’t developed all of the necessary aspects so they could be printed yet, but because these materials are all solution-based, it demonstrates the promise of this materials class and sets the stage for additive manufacturing.”

With the semiconductor industry in Vietnam expected to grow at a compound annual growth rate (CAGR) of 14.3% over the period of 2014 to 2019, momentum is growing in this emerging market. The electronics supply chain will convene at SEMICON Southeast Asia (SEA) from 26-28 April at the Subterranean Penang International Convention and Exhibition Centre (SPICE) in Penang, Malaysia to explore new opportunities and technology.

The increase in Vietnam is driven by the recent increase in demand for devices. Electronics accounted for 23% of all Vietnam exports in 2014, up from only 5% in 2010, making it a key development focus of the Vietnamese government (Vietnam Trade Promotion Agency). “Foreign direct investment” manufactured goods make up a large portion of the electronics export market, with only a small percentage contributed by local Vietnam companies. The electronics industry in Vietnam increased its market share of the electronics industry to 38% in 2014, and with the increasing number of electronic items, Vietnam finds itself at the cusp of being an important electronics exporter within the region.

SEMI, the global industry association serving the electronics manufacturing supply chain, will include programs pertinent to Vietnam’s semiconductor industry at the upcoming SEMICON SEA 2016, the region’s premier showcase for microelectronics innovation.

According to Ng Kai Fai, president of SEMI Southeast Asia, “Forums and discussion sessions during SEMICON SEA 2016 benefit electronic players from Vietnam in terms of technology development as well as the bigger picture of Vietnam’s market segment. The conference is an ideal platform for local semiconductor companies and start-ups to learn more about the technology trends that can be applied to Vietnam’s electronics growing importance. At the same time, multinational corporations use this event to learn about the Vietnam supply chain, assisting the build-up of a local ecosystem over the long run.”

“SEMICON SEA 2016 offers a complete platform for engaging customers, suppliers, engineers and decision-makers from across the industry. With the objective to champion regional collaboration, the showcase will open new business opportunities for customers and foster stronger cross-regional engagement. The event is sold-out for exhibitors for the first-time ever. With 200 global exhibitors and more than 60 industry luminaries presenting at the event, it offers a compelling reason why Vietnamese semiconductor stakeholders should attend this “don’t miss” electronics event,” Ng Kai Fai added.

SEMICON SEA 2016 will focus on the key trends and solutions in semiconductor design and manufacturing, including emphasis on serving the needs of expanding applications markets many of which require development of specialised materials, packaging, and test technologies, as well as new architectures and processes.

To register for SEMICON SEA 2016 or to explore exhibiting opportunities, visit http://www.semiconsea.org/ or contact Ms. Shannen Koh at [email protected].

Sponsors for SEMICON SEA 2016 include Advantest, Applied Materials, AMEC, ASE, Chip Shine, Edward Technologies, GLOBALFOUNDRIES, EV Group, Indium, KLA-Tencor, Kulicke & Soffa, Lam Research, SCREEN, Siemens, Tokyo Electron and Xcerra Corporation. Partners include Invest Penang, LEDExpo Thailand 2016, VLSI Consultancy, MATRADE, Malaysia Investment & Development Authority (MIDA), Ministry of Tourism and Culture Malaysia, Malaysia Convention & Exhibition Bureau (MyCEB), Penang Tourism, SAMENTA and Singapore Manufacturing Federation.

Entegris, Inc. (Nasdaq:ENTG), a provider of yield-enhancing materials and solutions for advanced manufacturing processes, announced the appointment of Sue Lee as Senior Vice President, General Counsel and Secretary. Ms. Lee is assuming the role from Peter Walcott, who is retiring after a 35-year career with Entegris and its predecessor companies.

Sue Lee

Sue Lee

Most recently, Ms. Lee was general counsel and corporate secretary with CYREN, a network security firm. Prior to CYREN, she served as general counsel for Harmonix Music Systems, was vice president of business & legal affairs for MTV Networks, and was counsel at Genzyme Corporation. Prior to joining Genzyme, Ms. Lee worked at Cleary Gottlieb Steen & Hamilton in New York. Born in Taiwan, Ms. Lee received her bachelor’s degree magna cum laude from Harvard University and her J.D. from Harvard Law School.

Bertrand Loy, president and CEO of Entegris commented, “I am delighted to welcome Sue to the Entegris team. Sue brings us an impressive background of deep corporate legal expertise and broad experience with international technology companies.”

TowerJazz, the global specialty foundry, today announced its SiGe Terabit Platform targeting high-speed wireline communications for the terabit age. Wireline data traffic is increasing dramatically, with traffic at Google famously increasing by 50 times over the last six to seven years, or at 75 percent per year.  Estimates vary, but experts agree on double digit CAGRs and a 2020 market for high speed optical components in excess of $9 billion.  TowerJazz addresses this market through a family of customized foundry silicon-germanium (SiGe) BiCMOS technologies and is today announcing availability of its highest performance process to date: S4. TowerJazz customers include the who’s-who for components that carry the world’s high-speed data traffic such as: BroadcomInphiMACOMMaximMaxlinear and Semtech, among others.

SiGe Terabit Platform – HX, H2, H3, H4, S4

The TowerJazz SiGe Terabit Platform includes advanced CMOS, together with low-noise, high-speed, and high power SiGe devices and unique patented features that enable best-in-class performance for the most demanding ICs in high-speed communication links.  These components include, for example, trans-impedance amplifiers (TIAs) on the receive path and laser drivers on the transmit path. The addition of S4 to the SiGe Terabit Platform extends a rich history of process technologies that include HX and H2 (addressing 10 to 28Gbps requirements), H3 with SiGe speeds of 280GHz (addressing requirements up to 100Gbps), and now H4 and S4 with transistor speeds that exceed 300GHz and can reduce power consumption by nearly an order of magnitude.

Two recent demonstrations, both in TowerJazz H3 technology, showcase the value of TowerJazz’s SiGe Terabit Platform. The first is UCI’s demonstration of TIA performance at 50 Gbps (2015 BCTM). Dr. Payam Heydari,  IEEE Distinguished Lecturer & Full Professor of Electrical Engineering and Computer Science, University of California, Irvine, said, “We measured up to 70Gbps data rate, using a NRZ (non-return to zero) architecture with an eye of 50Gbps. We estimate this chip will consume less than 0.5mW per GHz.”

The second is Bell Labs, the innovation engine of Nokia with its demonstration of a 112Gbps transceiver (2015 IEEE CSICS). Dr. Shahriar Shahramian, Technical Manager, Bell Labs, and the lead author in the publication, said, “To my knowledge, this is the world’s first demonstration of a >100GBs serial datalink built with a silicon IC.” He added that the “56-GBaud, 4-PAM transmission over 2-km of SSMF (single mode fiber) has been experimentally demonstrated.”

“These demonstrations used our H3 process and each represents record performance in data rate, as well as demonstrating new standards in data transmission over single mode fiber” said Dr. David Howard, TowerJazz Executive Director & Fellow. “We are very excited to introduce our newest process, S4, which enables our SiGe Terabit Platform to deliver higher speed and lower power and we look forward to the ground-breaking results our partners and customers will demonstrate next.”

Samsung Electronics Co., Ltd. announced today that it has begun mass producing the industry’s first 10-nanometer (nm) class, 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. DDR4 is quickly becoming the most widely produced memory for personal computers and IT networks in the world, and Samsung’s latest advancement will help to accelerate the industry-wide shift to advanced DDR4 products.

Samsung 10nm-class DRAM-Group_002

Samsung opened the door to 10nm-class DRAM for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered using currently available ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.

Samsung’s roll-out of the 10nm-class (1x) DRAM marks yet another milestone for the company after it first mass produced 20-nanometer (nm) 4Gb DDR3 DRAM in 2014.

“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”

Samsung’s leading-edge 10nm-class 8Gb DDR4 DRAM significantly improves the wafer productivity of 20nm 8Gb DDR4 DRAM by more than 30 percent.

The new DRAM supports a data transfer rate of 3,200 megabits per second (Mbps), which is more than 30 percent faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.

The industry-first 10nm-class DRAM is the result of Samsung’s advanced memory design and manufacturing technology integration. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology) lithography, and ultra-thin dielectric layer deposition.

Unlike NAND flash memory, in which a single cell consists of only a transistor, each DRAM cell requires a capacitor and a transistor that are linked together, usually with the capacitor being placed on top of the area where the transistor rests. In the case of the new 10nm-class DRAM, another level of difficulty is added because they have to stack very narrow cylinder-shaped capacitors that store large electric charges, on top of a few dozen nanometer-wide transistors, creating more than eight billion cells.

Samsung successfully created the new 10nm-class cell structure by utilizing a proprietary circuit design technology and quadruple patterning lithography. Through quadruple patterning, which enables use of existing photolithography equipment, Samsung also built the core technological foundation for the development of the next-generation 10nm-class DRAM (1y).

In addition, the use of a refined dielectric layer deposition technology enabled further performance improvements in the new 10nm-class DRAM. Samsung engineers applied ultra-thin dielectric layers with unprecedented uniformity to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, resulting in sufficient capacitance for higher cell performance.

Based on its advancements with the new 10nm-class DDR4 DRAM, Samsung expects to also introduce a 10nm-class mobile DRAM solution with high density and speed later this year, which will further solidify its leadership in the ultra-HD smartphone market.

While introducing a wide array of 10nm-class DDR4 modules with capacities ranging from 4GB for notebook PCs to 128GB for enterprise servers, Samsung will be extending its 20nm DRAM line-up with its new 10nm-class DRAM portfolio throughout the year.