Category Archives: Device Architecture

Technion, Israel’s technological institute, announced this week that Intel is collaborating with the institute on its new artificial intelligence (AI) research center. The announcement was made at the center’s inauguration attended by Dr. Michael Mayberry, Intel’s chief technology officer, and Dr. Naveen Rao, Intel corporate vice president and general manager of the Artificial Intelligence Products Group.

“AI is not a one-size-fits-all approach, and Intel has been working closely with a range of industry leaders to deploy AI capabilities and create new experiences. Our collaboration with Technion not only reinforces Intel Israel’s AI operations, but we are also seeing advancements to the field of AI from the joint research that is under way and in the pipeline,” said Naveen Rao, Intel corporate vice president and general manager of Artificial Intelligence Products Group

The center features Technion’s computer science, electrical engineering, industrial engineering and management departments, among others, all collaborating to drive a closer relationship between academia and industry in the race to AI. Intel, which invested undisclosed funds in the center, will represent the industry in leading AI-dedicated computing research.

Intel is committed to accelerating the promise of AI across many industries and driving the next wave of computing. Research exploring novel architectural and algorithmic approaches is a critical component of Intel’s overall AI program. The company is working with customers across verticals – including healthcare, autonomous driving, sports/entertainment, government, enterprise, retail and more – to implement AI solutions and demonstrate real value. Along with Technion, Intel is also involved in AI research with other universities and organizations worldwide.

Intel and Technion have enjoyed a strong relationship through the years, as generations of Technion graduates have joined Intel’s development center in Haifa, Israel, as engineers. Intel has also previously collaborated with Technion on AI as part of the Intel Collaborative Research Institute for Computational Intelligence program.

By Alan Weber

Even for someone who has been in this industry since the days of the TI Datamath 4-function calculator and the TMS1100 4-bit microcontroller (yes, that’s been a LONG time – the movie Grease premiered the same year!), it is sometimes hard to grasp the scope and complexity of what happens in today’s leading-edge semiconductor gigafabs. In fact, the only way to comprehend the enormous volume of transactions that occur is to consider what happens in a single minute – this is illustrated in the infographic we have labeled “The Gigafab Minute.”*

It’s amazing enough to think that a single factory can start 100,000 wafers every month on their cyclical journey through 1500 process steps… and have 99%+ of them emerge 4 months later to be delivered to packaging houses and then on to waiting customers. It’s quite another to realize that all of this happens continuously (24 x 7) and automatically.

“How is this possible?” you ask.

Well, a big part of the solution is the body of SEMI standards which have evolved since the early 80s to keep pace with the ever-changing demands of the industry. From an automation standpoint, many of these standards deal with the communications between manufacturing equipment and the factory information and control systems that are essential for managing these complex, hyper-competitive global enterprises.

A significant characteristic of these standards is that they have been carefully designed to be “additive.” This means that new generations of SEMI’s communications standards do not supplant or obsolete the previous generations, but rather provide new capabilities in an incremental fashion. To appreciate the importance of this in actual practice, consider how the GEM, GEM300, and EDA/Interface A standards support the transactions that occur in a single Gigafab Minute.

Starting at 1:00 o’clock on the infographic and moving clockwise, you first notice that 2.31 wafers enter the line. Of course, these are actually released in 25-wafer 300mm FOUPs (Front-Opening Unified Pod), but 100K wafers per month translates to 2.31 per minute. Since these factories run continuously, once the line is full, it stays full. And with an average total cycle time of 4 months, this means that there are 400K wafers of WIP (work in process) in the factory at any given time. This number, and the total number of equipment (5000+), drive the rest of the calculations.

GEM (Generic Equipment Model) – SEMI E30, etc.

The GEM messaging standards were initially defined in the early 90s to support the factory scheduling and dispatching applications that decide what lots should go to what equipment, the automated material handling systems that deliver and pick-up material to/from the equipment accordingly, the recipe management systems that ensure each process step is executed properly, and the MES (Manufacturing Execution System) transactions that maintain the fidelity of the factory system’s “digital twin.”

Every minute of every day, GEM messages support and chronicle the following activities: 240 process steps are completed (i.e., 240 25-wafer lots are processed), 300 recipes are downloaded along with a set of run-specific adjustable control parameters, and 600 FOUPs are moved from one place to another (equipment, stockers, under-track storage, etc.). For each of these activities, the factory’s MES is notified instantaneously.

GEM300 – SEMI E40, E87, E90, E94, E157

With the advent of 300mm manufacturing in the mid-to-late 90s, a global team of volunteer system engineers from the leading chip makers defined the GEM300 standards to support fully automated manufacturing operations. Starting at 5:00 o’clock on the infographic, the number of transactions per minute jumps almost 3 orders of magnitude, from the monitoring of 900 control jobs across 4000 process tools to the tracking of 360,000 individual recipe step change events. This level of event granularity is essential for the latest generation of FDC (Fault Detection and Classification) applications, because precise data framing is a key prerequisite for minimizing the false alarm rate while still preventing serious process excursions. In this context, more than 6000 recipe-, product- and chamber-specific fault models may be evaluated every minute.

Simultaneously, the applications that monitor instantaneous throughput to prevent “productivity excursions” and identify systemic “wait time waste” situations depend on detailed intra-tool wafer movement events. In a fab with hundreds of multi-chamber, single-wafer processes, 75,000 or more of these events occur every minute.

EDA (Equipment Data Acquisition) – SEMI E120, E125, E132, E134, E164, etc.

Rounding out the SEMI standards in our example gigafab is the suite of EDA standards which complement the command and control functions of GEM/GEM300 with flexible, high-performance, model-based data collection. The EDA standards enable the on-demand collection of the volume and variety of “big data” required from the equipment to support the advanced analysis, machine learning, and other AI (Artificial Intelligence) applications that are becoming increasingly prevalent in leading semiconductor manufacturers. As EUV (Extreme Ultraviolet) lithography moves from pilot production to high-volume manufacturing at the 7nm process node and beyond, the litho process area will become a major source of process data by itself, generating 10 GB of data every minute. This is in addition to the 100 GB of data collected from other process areas.

The End Result

The final wedge (12:00 o’clock) in our infographic highlights the real objective – which is producing the millions of integrated circuits that fuel our global economy and provide the technologies that are an integral part of our modern way of life. Assuming a nominal die size of 50 square mm (typical of an 8 GB DRAM), the 2.31 wafers we started at 1:00 o’clock result in almost 3200 individual chips. But none of this would be possible without the pervasive factory automation technology we now take for granted. So, as you finish reading this posting on whatever device you happen to be using, take a micro-moment to acknowledge and thank the hundreds of standards volunteers whose insights and efforts made this a reality!

You may not be responsible for running a gigafab anytime soon, but the SEMI standards used in this setting are no less applicable to any Smart Manufacturing environment. Give us a call if you’d like to know more about how these technologies can benefit your operations for many years to come.

Alan Weber is Vice President, New Product Innovations, at Cimetrix Incorporated. Previously he served on the Board of Directors for eight years before joining the company as a full-time employee in 2011. Alan has been a part of the semiconductor and manufacturing automation industries for over 40 years. He holds bachelor’s and master’s degrees in Electrical Engineering from Rice University.

Originally published on the SEMI blog.

To scale down a transistor below a 5nm node is one of the vital concerns for VLSI industry as there are various challenges due to the shrinking of components. Several researches are going on worldwide to overcome the challenges of future technology nodes. Among them, this article reviews the potential transistor structures and materials like Carbon Nano-tube FET, Gate-All-Around FET, and Compound Semiconductors as solutions to overcome the problems of scaling the existing silicon FinFET transistor below 5nm node.

By Pavan H Vora, Akash Verma, Dhaval Parikh

The ‘Semiconductor era’ started in 1960 with the invention of the integrated circuit. In an integrated circuit, all the active-passive components and their interconnection are integrated on a single silicon wafer, offering numerous advantages in terms of portability, functionality, power, and performance. The VLSI industry is following Moore’s law for many decades, which says, “the number of transistors on a chip becomes double approximately every two years”. To get the benefits of a scaled-down transistor, VLSI industry is continuously improving transistor structure and material, manufacturing techniques, and tools for designing IC. Various techniques, which have been adopted for transistors so far, include high-K dielectric, metal gate, strained silicon, double patterning, controlling channel from more than one side, silicon on insulator and many more techniques. Some of these techniques are discussed in ‘A Review Paper on CMOS, SOI and FinFET Technology’[1].

Nowadays, the demand of the internet of things, autonomous vehicles, machine learning, artificial intelligence, and internet traffic is growing exponentially, which acts as a driving force for scaling down transistor below the existing 7nm node for higher performance. However, there are several challenges of scaling down a transistor size.

Issues with Sub-Micron Technology:

Every time we scale down a transistor size, a new technology node is generated. We have seen transistor sizes such as 28nm, 16nm, etc. Scaling down a transistor enables faster switching, higher density, low power consumption, lower cost per transistor, and numerous other gains. The CMOS (complementary metal-oxide-semiconductor) transistor base IC technology performs well up to 28nm node. However, the short channel effects become uncontrollable if we shrink down CMOS transistor below 28 nm. Below this node, a horizontal electric field generated by drain-source supply tries to govern the channel. As a result, the gate is unable to control leakage paths, which are far from the gate.

16nm/7nm Transistor Technology: FinFet and FD-SOI:

The VLSI industry has adopted FinFET and SOI transistor for 16nm and 7nm nodes, as both the structures are able to prevent the leakage issue at these nodes. The main objective of both the structures is to maximize gate-to-channel capacitance and minimize drain-to-channel capacitance[1]. In both transistor structures, the channel thickness scaling is introduced as the new scaling parameter. As the channel thickness is reduced, there are no paths, which are far from the gate area. Thus, gates have a good control over the channel, which eliminates short channel effects.

In Silicon-on-Insulator (SOI) transistor, a buried oxide layer is used, which isolates the body from the substrate shown in Figure 1(a).Owing to the BOX layer, drain-source parasitic junction capacitances are reduced, which results in faster switching. The main challenge with the SOI transistor is that it is difficult to manufacture a thin silicon layer on the wafer.

Figure 1: a) FD-SOI Structure b) FinFET Structure and Channel

FinFET, which is also called as tri-gate controls channel is shown from three sides in Figure 1(b).  There is a thin vertical Si-body, which looks like a back fin of fish wrapped by the gate structure. A width of the channel is almost two times Fin height. Thus, to get higher driving strength, a multi-Fin structure is used. One of the gains with FinFET is higher driving current. The main challenge with FinFET is the complex manufacturing process.

Challenges with Technology Node below 5nm: What Next?

Reducing the body thickness results into lower mobility as surface roughness scattering increases. Since FinFET is a 3-D structure, it is less efficient in terms of thermal dissipation. Also, if we scale down the FinFET transistor size further, say below 7nm, the leakage issue becomes dominant again. Consequently, many other problems come into consideration like self-heating, threshold flattening, etc. These concerns lead to research on other possible transistor structures and replacing existing materials with new effective materials.

According to the ITRS roadmap (International Technology Roadmap for Semiconductors), the next technology nodes are 5nm, 3nm, 2.5nm, and 1.5nm. Many different types of research and studies are going on in VLSI industry and academia for potential solutions to deal with these future technology nodes. Here we discuss some promising solutions like carbon nanotube FET, GAA transistor structure, and compound semiconductor for future technology nodes.

Figure 2: Transistor Technology Roadmap

CNTFET – Carbon Nano Tube FET:

CNT (Carbon Nanotube) showcases a new class of semiconductor material that consists of a single sheet of carbon atoms rolled up to form a tubular structure. CNTFET is a field-effect transistor (FET) that uses semiconducting CNT as a channel material between the two metal electrodes, which behave as source and drain contacts. Here we will discuss carbon nanotube material and how it is beneficial to FET at a lower technology node.

  • What is a Carbon Nanotube?

CNT is a tubular shaped material, made of carbon, having diameters measurable on the nanometer scale. They have a long and hollow structure and are formed from sheets of carbon that are one atom thick. It is called “Graphene”. Carbon nanotubes have varied structures, differing in length, thickness, helicity, and the number of layers. Majorly, they are classified as Single Walled Carbon Nanotube (SWCNT) and Multi-Walled Carbon Nanotube (MWCNT). As shown in Figure 3(a), one can see that SWCNTs are made up of a single layer of graphene, whereas MWCNTs are made up of multiple layers of graphene.

Figure 3: a) Single Walled and Multi Walled CNTs b) Chirality Vector Representation

  • Properties of Carbon Nanotube:

The carbon nanotube delivers excellent properties in areas of thermal and physical stability as discussed below:

  1. Both Metallic and Semiconductor Behavior

The CNT can exhibit metallic and semiconductor behavior. This change in behavior depends on the direction in which the graphene sheet is rolled. It is termed as chirality vector. This vector is denoted by a pair of integer (n, m) as shown in Figure 3(b). The CNT behaves as metallic if ‘n’ equals to ‘m’ or the difference of ‘n’ and ‘m’ is the integral multiple of three or else it behaves as a semiconductor [2].

  1. Incredible Mobility

SWCNTs have a great potential for application in electronics because of their capacity to behave as either metal or as a semiconductor, symmetric conduction and their capacity to carry large currents. Electrons and holes have a high current density along the length of a CNT due to the low scattering rates along the CNT axis. CNTs can carry current around 10 A/nm2, while standard metal wires have a current carrying capacity that is only around 10 nA/nm2[3].

  1. Excellent Heat Dissipation

Thermal management is an important parameter for the electronic devices’ performance. Carbon nanotubes (CNTs) are well-known nanomaterials for excellent heat dissipation. Moreover, they have a lesser effect of the rise in temperature on the I-V characteristics as compared to silicon [4].

CNT in Transistor Applications: CNFET

The bandgap of carbon nanotubes can be changed by its chirality and diameter and thus, the carbon nanotube can be made to behave like a semiconductor. Semiconducting CNTs can be a favorable candidate for nanoscale transistor devices for channel material as it offers numerous advantages over traditional silicon-MOSFETs. Carbon nanotubes conduct heat similar to the diamond or sapphire. Also, they switch more reliably and use much less power than silicon-based devices [5].

In addition, the CNFETS have four times higher trans-conductance than its counterpart. CNT can be integrated with a High-K material, which is offering good gate control over the channel. The carrier velocity of CNFET is twice as compared to MOSFET, due to increased mobility. A carrier mobility of N-type and P-type CNFET is similar in offering advantages in terms of same transistor size. In CMOS, PMOS (P-type metal-oxide-semiconductor) transistor size is approximately 2.5 times more than NMOS (N-type metal-oxide-semiconductor) transistor as mobility values are different.

The Fabrication process of CNTFET is a very challenging task as it requires precision and accuracy in the methodologies.Here we discuss the Top-gated CNTFET fabrication methodology.

The first step in this technique starts from the placement of carbon nanotubes onto the silicon oxide substrate. Then the individual tubes are isolated. Source and drain contacts are defined and patterned using advanced lithography. The contact resistance is then reduced by refining the connection between the contacts and CNT. The deposition of a thin top-gate dielectric is performed on the nanotube via evaporation technique. Lastly, to complete the process, the gate contact is deposited on the gate dielectric [6].

Figure 4: Concept of Carbon-Nanotube FET

Challenges of CNTFET:

There are lots of challenges in the roadmap of commercial CNFET technology.  Majority of them have been resolved to a certain level, but a few of them are yet to be overcome. Here we will discuss some of the major challenges of CNTFET.

  1. Contact Resistance

For any advanced transistor technology, the increase in contact resistance due to the low size of transistors becomes a major performance problem. The performance of the transistor degrades as the resistance of contacts increases significantly due to the scaling down of transistors. Until now, decreasing the size of the contacts on a device caused a huge drop in execution — a challenge facing both silicon and carbon nanotube transistor technologies [7].

  1. Synthesis of Nanotube

Another challenge with CNT is to change its chirality such that it behaves like a semiconductor. The synthesized tubes have a mixture of both metals and semiconductors. But, since only the semiconducting ones are useful for qualifying to be a transistor, engineering methodologies need to be invented to get a significantly better result at separating metal tubes from semiconducting tubes.

  1. To develop a non-lithographic process to place billions of these nanotubes onto the specific location of the chip poses a challenging task.

Currently, many engineering teams are carrying out research about CNTFET devices and their logic applications, both in the industries and in the universities. In the year 2015, researchers from one of the leading semiconductor companies succeeded in combining metal contacts with nanotubes using “close-bonded contact scheme”. They achieved this by putting a metal contact at the ends of the tube and making them react with the carbon to form different compounds. This technique helped them to shrink contacts below 10 nanometers without compromising the performance [8].

Gate-All-Around FET: GAAFET

One of the futuristic potential transistor structures is Gate-all-around FET. The Gate-all-around FETs are extended versions of FinFET. In GAAFET, the gate material surrounds the channel region from the four directions. In a simple structure, a silicon nanowire as a channel is wrapped by the gate structure. A vertically stacked multiple horizontal nanowires structure is proven excellent for boosting current per given area. This concept of multiple vertically stacked gate-all-around silicon nanowire is shown in Figure 5.

Figure 5: Vertically Stacked Nanowires GAAFET

Apart from silicon material, some other materials like InGaAs, germanium nanowires can also be utilized for better mobility.

There are many hurdles for GAAFET in terms of complex gate manufacturing, nanowires, and contacts. One of the challenging processes is fabricating nanowires from the silicon layer as it requires a new approach for the etching process.

There are many research labs and institute working for Gate-all-around FET for lower nodes. Recently, Leuven based R&D firm claimed that they achieved excellent electrostatic control over a channel with GAAFET at sub 10nm diameter nanowire. Last year, one of the leading semiconductor companies unveiled a 5nm chip, which contains 30 billion transistors on a 50mm2chip using stacked nanowire GAAFET technology. It claimed to achieve 40% improvement in performance compared to 10nm node or 70% improvement in power consumption at the same performance.

Compound Semiconductors:

Another promising way to scale down a transistor node is the selection of novel material that exhibits higher carrier mobility. A compound semiconductor with ingredients from columns III and V are having higher mobility compared to silicon. Some compound semiconductor examples are Indium Gallium Arsenide (InGaAs), Gallium Arsenide (GaAs), and Indium Arsenide (InAs). According to various studies, integration of compound semiconductor with FinFET and GAAFET showing excellent performance at lower nodes.

The main concerns with compound semiconductor are large lattice mismatch between silicon and III-V semiconductor, resulting in defects of the transistor channel. One of the firms developed a FinFET containing V-shaped trenches into the silicon substrate. These trenches filled with indium gallium arsenide and forming the fin of the transistor. The bottom of the trench is filled with indium phosphide to reduce the leakage current. With this trench structure, it has been observed that defects terminate at the trench walls, enabling lower defects in the channel.

Conclusion:

From the 22nm node to 7nm node, FinFETs have been proven successful and it may be scaled down to one more node. Beyond that, there are various challenges like self-heating, mobility degradation, threshold flattening, etc. We have discussed how carbon nanotube’s excellent properties of motilities, heat dissipation, high current carrying capability offer promising solutions for replacing existing silicon technology. As the stack of horizontal nanowire opened a “fourth gate”, Gate-all-around transistor structure is also a good candidate for replacing vertical Fin structure of FinFET for achieving good electrostatic property. It is not clear what comes next in the technology roadmap. However, in the futuristic transistor technology, there must be changes of existing material, structure, EUV (Extreme ultraviolet) lithography process, and packaging to sustain Moore’s law.

References:

[1]  Pavan Vora, Ronak Lad, “A Review Paper on CMOS, SOI and FinFET Technology”, www.design-reuse.com/articles/

[2]  P.A Gowri Sankar, K. Udhaya Kumar, “Investigating The Effect of Chirality On Coaxial Carbon Nanotube Field Effect Transistor”, 2012 International Conference on Computing, Electronics and Electrical Technologies (ICCEET)

[3] Rashmita Sahoo, S.K Sahoo, “Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation”, 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

[4] Yijian Ouyang and Jing Guo, “Heat dissipation in carbon nanotube transistors”, Appl. Phys. Lett. 89, 183122 (2006)

[5] Philip G. Collins & Phaedon Avouris, “Nanotubes for Electronics”, Scientific American 283, 62 – 69 (2000)

[6] Wind, S. J.; Appenzeller, J.; Martel, R.; Derycke, V.; Avouris, Ph. (2002). “Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes”, Applied Physics Letters. 80 (20): 3817. Bibcode:2002ApPhL..80.3817W.

[7] Aaron D. Franklin, Wilfried Haensch, “Defining and overcoming the contact resistance challenge in scaled carbon nanotube transistors”, 72nd Device Research Conference

[8] IBM, “IBM Research Breakthrough Paves Way for Post-Silicon Future with Carbon Nanotube Electronics”, https://www-03.ibm.com/press/us/en/pressrelease/47767.wss

About Authors:

Pavan Vora

Pavan Vora is working as an ASIC Physical Design Engineer at eInfochips, an Arrow company. He has more than 3 years of experience in ASIC designs for cutting technology nodes such as 12nm, 16nm FinFET, and 28nm. Pavan has expertise in ASIC P&R, LEC, LVS, Static Timing Analysis, Signal EM, DRC, and IR drop and has been awarded a Gold Medal in Master of Engineering in VLSI System Design.

Akash Verma

Akash Verma is working as an ASIC Trainee Engineer at eInfochips, an Arrow company. He has completed his bachelors in Electronics & Communication from the GIT, Gandhinagar. He is currently working on networking ASIC chip at 7nm FinFET technology, in which his accountabilities include block level APR, Static Timing Analysis and Physical Verification. His interest lies in Analog Mixed Signal designs and EDA tool’s algorithmic methodologies.

Dhaval Parikh

Dhaval Parikh is working as a Technical Manager at eInfochips, an Arrow company. He has more than 11 years of industry experience and has worked in various ASIC designs of IP’s & SoC’s, from 180nm to cutting technology node 7nm. He has been responsible for all the aspects of physical design and verification along with executing multiple projects simultaneously.

About eInfochips:

eInfochips, an Arrow company, is a global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company’s service offerings include digital transformation and connected IoT solutions across various cloud platforms, including AWS and Azure.

Along with Arrow’s $27B in revenues, 19,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. eInfochips acts as a catalyst to Arrow’s Sensor-to-Sunset initiative and offers complete edge-to-cloud capabilities for its clients through Arrow Connect.

According to data compiled by Inkwood Research, the global semiconductor market is projected to grow at a CAGR of 7.67% during the forecast period from 2017 to 2024. Data reflects that the market is driven by rising demand for consumer electronics, the growing automotive semiconductor market, the emerging internet of things (IoT) market and investments into New Product Development and R&D. Consumer electronics are primarily fueling the market due to demand for products such as tablets, smartphones, laptops and wearable devices. As semiconductor technology begins to advance, new segments are swiftly being integrated into the market, such as Machine Learning. Squire Mining Ltd. (OTC: SQRMF), Intel Corporation (NASDAQ: INTC), Texas Instruments Incorporated (NASDAQ: TXN), NXP Semiconductors N.V. (NASDAQ: NXPI), Skyworks Solutions, Inc. (NASDAQ: SWKS)

According to data by MarketsandMarkets, the global machine learning sector is expected to grow from USD 1.41 Billion in 2017 to USD 8.81 Billion in 2022 while registering a CAGR of 44.1% during the forecast period. The segment is rapidly growing due to many businesses adopting machine learning to gather intelligence for security and consumer interaction benefits, which can help eliminate human errors. However, machine learning is also being integrated into modern day technology, such as the automotive industry, to build autonomous vehicles. In a report by Forbes, Daniel Newman Principal Analyst and Founding Partner of Futurum Research, explained, “When dealing with a technology as advanced as machine learning, there simply isn’t an industry that would not benefit. I mean how could a business not take advantage of a technology that would make them more successful? In the next year, there will be multiple new uses for machine learning in all of these industries available for the taking and I’m not just talking about in marketing and sales.”

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Yesterday, the Company announced breaking news that, “to report on its prototype ASIC chip testing event held in Seoul, South Korea. With executives and board members from Squire, Future Farm, CoinGeek, Gaonchips and Samsung Electronics in attendance, Peter Kim, President of Squire’s subsidiary AraCore Technology Corp. (“Aracore”), and his team of front-end microchip engineers and programmers, unveiled and tested a working prototype mining system comprised of a newly engineered FPGA (field programmable gate array) ASIC microchip that will be converted into AraCore’s first ASIC chip utilizing 10 nanometer technology for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. The test results confirm Aracore’s original design specifications indicating that the ASIC chip, once mass manufactured by Samsung Electronics, will be capable of delivering a projected hash rate of 18 to 22 terahash per second (TH/s) with an energy consumption of between 700 and 800 watts.

Taras Kulyk, Chief Executive Officer of CoinGeek Mining and Hardware, said ‘The CoinGeek team is very pleased with the progress of our strategic partners; Squire Mining and Aracore. With this next generation technology, CoinGeek will continue to pull the blockchain industry out of the proverbial basement and into the boardroom.’

Stefan Matthews, Chairman of nChain, one of the industry leaders in blockchain research and development, and a director of Squire Mining added, ‘The early results indicate that this ASIC microchip has the potential to be the next generation leader in providing hash power for enterprise mining of Bitcoin Cash and other associated crypto currencies. It has also demonstrated the potential to rapidly process consensus protocols across the blockchain faster whilst utilizing less energy than anything currently in this sector.’

Hash rate speed and microchip efficiency are the two most important measuring criteria in the crypto-mining industry to enable end-users to maximize profitability and ROI in their day to day mining operations.

Simon Moore, Executive Chairman and CEO of Squire Mining, stated, ‘Aracore’s time and investment to date have been validated by the impressive results of this new microchip. Once completed, we believe the speed and efficiency of our ASIC microchip combined with our respective mining systems powered by this Samsung manufactured microchip together have the potential to substantially increase the profitability of enterprise mining facilities around the globe. We look forward to releasing our mining system to the market in the first half of next year through our exclusive distribution partners CoinGeek, and competing for a significant piece of this multi-billion-dollar enterprise mining market.’

In its September Update to The 2018 McClean Report, IC Insights discloses that over the past two years, DRAM manufacturers have been operating their memory fabs at nearly full capacity, which has resulted in steadily increasing DRAM prices and sizable profits for suppliers along the way.  Figure 1 shows that the DRAM average selling price (ASP) reached $6.79 in August 2018, a 165% increase from two years earlier in August of 2016. Although the DRAM ASP growth rate has slowed this year compared to last, it has remained on a solid upward trajectory through the first eight months of 2018.

Figure 1

The DRAM market is known for being very cyclical and after experiencing strong gains for two years, historical precedence now strongly suggests that the DRAM ASP (and market) will soon begin trending downward.  One indicator suggesting that the DRAM ASP is on the verge of decline is back-to-back years of huge increases in DRAM capital spending to expand or add new fab capacity (Figure 2). DRAM capital spending jumped 81% to $16.3 billion in 2017 and is expected to climb another 40% to $22.9 billion this year. Capex spending at these levels would normally lead to an overwhelming flood of new capacity and a subsequent rapid decline in prices.

Figure 2

However, what is slightly different this time around is that big productivity gains normally associated with significant spending upgrades are much less at the sub-20nm process node now being used by the top DRAM suppliers as compared to the gains seen in previous generations.

At its Analyst Day event held earlier this year, Micron presented figures showing that manufacturing DRAM at the sub-20nm node required a 35% increase in the number of mask levels, a 110% increase in the number of non-lithography steps per critical mask level, and 80% more cleanroom space per wafer out since more equipment—each piece with a larger footprint than its previous generation—is required to fabricate ≤20nm devices. Bit volume increases that previously averaged around 50% following the transition to a smaller technology node, are a fraction of that amount at the ≤20nm node.  The net result is suppliers must invest much more money for a smaller increase in bit volume output.  So, the recent uptick in capital spending, while extraordinary, may not result in a similar amount of excess capacity, as has been the case in the past.

As seen in Figure 2, the DRAM ASP is forecast to rise 38% in 2018 to $6.65, but IC Insights forecasts that DRAM market growth will cool as additional capacity is brought online and supply constraints begin to ease. (It is worth mentioning that Samsung and SK Hynix in 3Q18 reportedly deferred some of their expansion plans in light of expected softening in customer demand.)

Of course, a wildcard in the DRAM market is the role and impact that the startup Chinese companies will have over the next few years.  It is estimated that China accounts for approximately 40% of the DRAM market and approximately 35% of the flash memory market.

At least two Chinese IC suppliers, Innotron and JHICC, are set to participate in this year’s DRAM market. Although China’s capacity and manufacturing processes will not initially rival those from Samsung, SK Hynix, or Micron, it will be interesting to see how well the country’s startup companies perform and whether they will exist to serve China’s national interests only or if they will expand to serve global needs.

 

SMART Global Holdings, Inc. (“SMART” or the “Company”) (NASDAQ: SGH), parent company of SMART Modular Technologies, Inc., today announced the appointment of Bryan Ingram, Senior Vice President and General Manager of the Wireless Semiconductor Division of Broadcom Inc., to its board of directors and its Compensation Committee, effective October 2, 2018.

“Bryan brings significant operating skills and an extensive network of relationships with industry leaders in all parts of the electronics and semiconductor supply chain, including the largest handset manufacturers in the world,” said Ajay Shah, Chairman of the Board, President & CEO of SMART. “Bryan is responsible for one of the largest divisions within Broadcom, and his long history of executive leadership in the global semiconductor industry will be of great benefit to SMART as we continue to execute our expansion strategy.”

Mr. Ingram currently leads the Wireless Semiconductor Division at Broadcom Inc. and has served in various executive roles for over 13 years, at Broadcom Inc. and its predecessor Avago Technologies Limited, which acquired Broadcom Corp. in 2015. Mr. Ingram also held executive positions at the predecessor to Avago within Agilent Technologies. From 1986 to 1999 Mr. Ingram held various management positions at Hewlett Packard and Westinghouse. Mr. Ingram holds a Bachelor of Science in Electrical Engineering from the University of Illinois and a Master of Science in Electrical Engineering from Johns Hopkins University.

With the appointment of Mr. Ingram, the board of SMART Global Holdings now has four independent directors and a total of nine members.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, to day announced worldwide sales of semiconductors reached $40.16 billion for the month of August 2018, an increase of 14.9 percent compared to the August 2017 total of $34.96 billion. Global sales in August 2018 were 1.7 percent higher than the July 2018 total of $39.49 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales continued to bound upward in August, easily outperforming sales from last August and narrowly surpassing last month’s total,” said John Neuffer, president and CEO, Semiconductor Industry Association. “While year-to-year growth has moderated somewhat in recent months, sales remain strong across every major semiconductor product category and regional market, with the China and Americas markets standing out with the largest year-year growth.”

Regionally, sales increased compared to August 2017 in China (27.3 percent), the Americas (15.0 percent), Europe (9.5 percent), Japan (8.4 percent), and Asia Pacific/All Other (4.7 percent). Sales were up compared to last month in China (2.1 percent), the Americas (3.6 percent), and Asia Pacific/All Other (1.3 percent), and decreased slightly inJapan (-0.1 percent), and Europe (-1.4 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2018 SIA Databook.

Visionary keynote speakers and industry luminaries will share insights on Smart technologies that are shaping the future at SEMICON Japan 2018, the largest and most influential exhibition in Japan for electronics manufacturing. Registration for SEMICON Japan, at Tokyo Big Sight in Tokyo on December 12-14, is now open for the exhibition and programs.

Themed “Dreams Start Here,” SEMICON Japan 2018 reflects the promise of AI (artificial intelligence), Internet of Things (IoT) and Smart technologies.

SEMICON Japan 2018 is the gathering place to connect the people, technologies and business across the electronics manufacturing supply chain, from semiconductor manufacturing to autonomous cars, robotics and other Smart applications.

Representing segments across the supply chain, the industry visionaries will present at SEMICON Japan’s SuperTHEATER in seven keynote forums, all with simultaneous English-Japanese translation.

Opening Keynotes – Alternative Future Envisioned by New Leaders 

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Motoi Ishibashi

CTO of Rhizomatiks, a leading media art company in Japan that staged the Rio Olympic Games closing ceremony. It will orchestrate the opening performance at SEMICON Japan 2018.

 
 

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Toru Nishikawa

President & CEO of Preferred Networks, a deep-learning research startup conducting collaborative research with technology giants including Toyota, Fanuc, NVIDA, Intel and Microsoft.
 

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Semiconductor Executive Forum – Views by Top Three in the Era of Smart World 

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Dr. Yasuo Naruke

President and CEO of Toshiba Memoryrepresenting memory sector

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Thomas Morgenstern

Senior VP and GM of GLOBALFOUNDRIESrepresenting foundry sector

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Junko Sunaga

President of Qualcomm Japan representing fabless sector

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SMART Transportation Summit – The Future Created by SMART Innovation 

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Takashi Imai

President and CEO of Toyota Info Technology Center

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Kazuyuki Iwata

Operating officer, Energy & Mobility Management System Executive LPL,

at Honda R&D

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Hajime Kumabe

Executive director, Engineering Research

and Development Center, at Denso
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Klaus Meder

President and representative director of Bosch
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Additional SEMICON Japan 2018 highlights include:

  • SEMI Market Forum on the growing China and global semiconductor ecosystem with speakers from IHS Markit and SEMI.
  • SMART Technology Forum on the front line of AI with speakers from the University of Tokyo, Microsoft Japan, Amazon Web Services and DefinedCrowd.
  • Manufacturing Innovation Forum on EUV lithography with speakers from ASML and Xilinx.
  • Mirai (future) Vision Forum on how advanced science and technology could transform the human body with speakers from Leave a Nest and more.

SEMICON Japan Sponsors

  • Platinum sponsors include Disco Corporation, Hitachi High-Technologies Corporation, Screen Semiconductor Solutions Co., Ltd., and Tokyo Electron Limited.
  • Gold sponsors include Advantest, Applied Materials, Ebara, Fasford Technology, Hitachi Chemical, JSR, Kokusai Electric, Lam Research, Nikon, and Tokyo Seimitsu.

For more information and to register for SEMICON Japan, click here.

Recognizing the importance of obsolescence mitigation in embedded and industrial systems, two of the biggest names in advanced storage, memory and semiconductor technologies have teamed up to ensure the continuous supply of legacy DDR2 memory modules in the market. ATP, a leading manufacturer of high-performance industrial memory and storage solutions, will collaborate with global semiconductor leader Micron Technology, Inc. to continue manufacturing Micron DDR2 SO-DIMMs, UDIMMs and RDIMMs after Micron announced end-of-life (EOL) notices for these modules.

According to the collaboration agreement, ATP will produce DDR2 DRAM modules for customers that cannot upgrade to newer-generation platforms and still maintain the use of platforms supporting these memory types. With DDR2 still widely deployed in the US, Japan and Europe, ATP and Micron expect these markets to benefit significantly from the consistent supply of DDR2 memory for industrial/embedded systems installed in high-reliability and mission-critical environments. All modules will be manufactured, tested and validated by ATP, according to the equivalent specifications and testing/validation processes of the respective Micron part number.

“Micron is dedicated to maximizing customers’ infrastructure investments by ensuring prolonged support for legacy systems and applications. Our proven partnership with ATP gives our customers the benefit of receiving similar Micron products and services to support their current platforms while ATP ensures the stability of their operations well into the future,” said Kris Baxter, vice president, Micron Technology, Inc.

“A long product cycle is vital to the sustainability of industrial business operations,” said Marco Mezger, vice president, ATP Electronics, Inc. “The DDR2 Continuity Program demonstrates ATP’s enduring partnership with Micron as well as our shared commitment to extend supply stability, not only of the latest-generation products, but also of legacy memory modules to continue supporting the memory requirements of customers that are not yet able to make the transition. Through this collaboration, customers will be assured of steady supply to support their operations.”

The DDR2 Continuity Program will be implemented on a staggered basis within three manufacturing phases. DDR2 DRAM modules from ATP will be available in select form factors and densities starting Q4 2018. Please check with your ATP contact for specific module configurations with ATP longevity extension or send an email to [email protected].

By Jaegwan Shim

Korea is on track to top all other regions in fab investment, spending $63 billion between 2017 and 2020, with powerhouses Samsung Electronics Co. and SK Hynix leading the way, according to latest World Fab Forecast Report by SEMI. Samsung Electronics increased fab investments $770 million to $12 billion this year, and SK Hynix upped its spending a significant $2.8 billion to $7.25 billion in 2018.

Korea’s investment companies anticipate continued growth for both companies in the second half of 2018.

Under this halo of extraordinary investment, nearly 380 SEMI Korea members and industry analysts gathered for 2018 SEMI Korea Members Day on September 22 to share insights on semiconductor market trends and new technologies that could help members bolster their competitiveness. Following are key takeaways from the event.

Korea semiconductor market to grow 16% in 2018

That’s according to IDC Korea VP Kim Soo-kyung, who noted that data center, memory and Internet of Things (IoT) are becoming key growth drivers for the semiconductor industry. He encouraged semiconductor companies to closely track development of automotive technology and the industry semiconductor market, both key growth areas.

SEMI Korea president H.D. Cho opens SEMI Korea Members Day 2018

Continuing fab investment will lead to oversupply, but display will shine

Market entry by Chinese companies will also spur the oversupply, said Jeong Won-Seok, an analyst at HI Investment Corp. He noted that the oversupply will force Korea into stiffer competition with other regions. However, with OLED used for a wide variety of devices and the display industry seeing rapid growth, the sector will remain ripe for growth among Korean companies.

Interconnecting various applications is a big semiconductor industry trend

The need for these interconnections will stand out in the mobility and high-performance computing (HPC) markets, said Kim Jin-Young, director at Amkor Technology Korea, who addressed trends in packaging technology. He also emphasized interconnection cost efficiency as key to maximizing competitiveness.

Smart Manufacturing is driving mass customization

As semiconductor industry growth continues, production methods are shifting from ‘mass production’ to ‘mass customization,’ increasing the importance of Smart Manufacturing in driving greater production efficiency, noted BISTel VP Jeon Kyeong-Sik. Building a Smart Manufacturing platform to support large-scale production of specialized database and artificial intelligence (AI) chips will boost production efficiency, reduce costs and improve risk management. Virtual simulation will be a key enabling technology.

SEMI analyst Clark Tseng presenting at SEMI Korea Members Day 2018

Surge in data volume and technology advances to drive long-term semiconductor industry growth

These key industry drivers will continue to power fab investment growth, with spending focused on 3D NAND, DRAM, and foundry, said Clark Tseng, a SEMI analyst. China alone will see eye-watering growth with the region’s investments in domestic companies surging 46% from 2018 to 2019 and fab investment by Chinese domestic companies outpacing spending by foreign companies in China, Tseng predicted.

SEMI membership rises with industry growth

Culminating the event, SEMI Korea president H.D. Cho said, “With the growth of the semiconductor market, the number of SEMI members is gradually increasing, and we will help member companies grow with various activities such as Korea Members Day.”

Jaegwan Shim is a marketing specialist at SEMI Korea. 

Originally published on the SEMI blog.