Category Archives: Device Architecture

Amid rapid custom silicon growth and innovation, Open-Silicon today announced the appointment of semiconductor industry veteran Anand Bariya as VP of engineering. Anand will be responsible for managing the physical implementation of silicon, and facilitating the delivery of reliable parts with predictable schedules. He will be instrumental in the strategic planning of silicon engineering, from RTL to working silicon, and will oversee Open-Silicon’s physical design teams. Anand will report to Shafy Eltoukhy, SVP of Operations and GM of Open-Silicon, a SiFive company.

“I’m proud to join the team at Open-Silicon,” said Anand. “The company is a proven leader with a strong record of providing custom silicon solutions. I look forward to working closely with customers and partners to develop innovative, full turnkey custom solutions that not only meet the highest quality and reliability expectations, but are delivered with predictable schedules.”

Anand has over 25 years of experience in the semiconductor industry, both in Silicon Valley and in India. Prior to joining Open-Silicon, he served as senior director at Broadcom in India, where he managed engineering operations. Prior to that, he spent over six years at NetLogic Microsystems (later acquired by Broadcom), where he served as vice president and managing director. Before joining NetLogic, he managed the ASIC Design Center at Toshiba America. He has also held management positions at Vitesse Semiconductor, Cadence Design Systems and National Semiconductor. Anand earned a PhD in chemical and electrical engineering at Stanford University, and a bachelor’s degree in chemical engineering at the Indian Institute of Technology, Bombay.

“Anand brings extensive leadership and a deep understanding of the engineering required for complex SoC design and delivery,” said Shafy Eltoukhy, SVP of Operations and GM of Open-Silicon, a SiFive company. “His proven leadership and track record of execution and delivery will be instrumental in building on Open-Silicon’s momentum in custom SoCs.”

TowerJazz, the global specialty foundry, today provided further details on its 13th annual U.S. Technical Global Symposium (TGS) to be held on November 7, 2018 at the Hilton Santa Clara, CA. During TGS, the company will share its vision on industry megatrends: “Wireless Everything, Smart Everything, Green Everything” – and the means by which its analog specialty portfolio helps customers to differentiate their technology solutions.

The event will commence with TowerJazz CEO, Russell Ellwanger, who will share plans with respect to the Company’s focus on “full circle value creation,” including strategic growth, technology leadership, and capacity expansion. TowerJazz executives will then share the latest technology roadmap developments of the Company’s RF/high performance analog, CMOS image sensors, power management, and aerospace & defense offerings, in addition to its industry-leading design enablement capabilities.

To view the agenda, focus areas for the technical sessions, and/or register for the event, please visit here.

Keysight Technologies, Inc. (NYSE: KEYS), a technology company that helps enterprises, service providers, and governments accelerate innovation to connect and secure the world, today announced that the company’s 3D planar electromagnetic (EM) simulator, Momentum, has been certified for GLOBALFOUNDRIES (GF) 22FDX®, 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology.

Keysight’s Momentum is a 3D planar EM simulator used for passive circuit modeling and analysis. It accepts arbitrary design geometries (including multi-layer structures) and uses frequency-domain Method of Moments (MoM) technology to accurately simulate complex EM effects including coupling and parasitics.

As a result of the certification, designers can now perform accurate EM simulation with GF’s cutting-edge 22FDX technology, facilitating analysis of electromagnetic effect and behavior in today’s ever shrinking and complex designs. Momentum stack-up files are integrated with the latest 22FDX PDK available from GF.

“The certification of GF 22FDX for Keysight’s EM simulator is testimony to the continuous collaboration between GF and Keysight under Keysight’s Foundry Program,” said Punmark Ngangom, RFIC Foundry Program Manager for Keysight Technologies. “Our mutual customers will now be able to leverage Keysight’s GF certified Momentum stack-up files, which are available with GF’s standard 22FDX PDK package.”

Keysight’s Momentum has also been certified for RF/mmWave-optimized metal options with different inductors, attaining highly precise correlation with silicon measurements and circuit models up to 100 GHz per GF’s certification standards.

GOWIN Semiconductor Corp., a developer of programmable logic devices, announces 2 new additions to the current families of embedded memory FPGA devices, the GW1NR-LV4MG81 and GW1NSR-LX2CQN48.  As computing functions are being distributed to edge locations, the need for silicon to adapt to these new uses is becoming prevalent.  The 2 new embedded FPGA devices were designed with low power, small package size, and low cost in mind.

Adopting an edge to cloud infrastructure is challenging.  Each portion of the chain has its own unique characteristics in design.  For the edge, size of sensor or data gatherer affects product real estate; power consumption affects the power source, especially battery life.  The new embedded memory FPGA devices solve these issues by enhancing the integration of multiple devices into a nice, single package device.

“GOWIN’s vision has always been one of developing new products for customer’s needs,” said Jason Zhu, CEO of GOWIN Semiconductor.  “We saw a lack of product integration at the edge and aimed to fix this with easy to use solutions at cost-effective price points.”

The GW1NR-LV4MG81 is a 4K LUT FPGA fabric with 64Mb internal high-speed memory.  The package size is ultra-small, 4.5mm x 4.5 mm PBGA and .83mm thick.  A great logic device for applications where the thickness is an issue.  Power consumption has been optimized to the lowest possible using TSMC’s 55nm LP process.  And up to 69 user IO’s are available supporting GOWIN’s flexible IO structures.

In a 5mm x 5mm QFN package, the GW1NSR-LX2CQN48 is GOWIN’s first device that combines a 2K LUT FPGA fabric with 32Mb internal high-speed memory and an Arm Cortex M3 microprocessor.  With additional user programmable flash, internal SRAM, ADC, and both USB2.0 and MIPI D-PHY interfaces, this makes the GW1NSR-LX2CQN48 a true SoC to solve low power requirements at the edge and elsewhere.

GOWIN offers a complete all-in-one toolchain for both FPGA fabric programming and Cortex M3 programming.  In addition, a complete library of IP cores and reference designs are available to assist in developing platform solutions.  All of these resources are available for download on GOWIN’s website, www.gowinsemi.com.

Global fab equipment spending will increase 14 percent this year to US$62.8 billion and is expected to rise 7.5 percent, to US$67.5 billion, in 2019, marking the fourth consecutive year of spending growth and the highest investment year for fab equipment in the history of the industry, according to the latest World Fab Forecast Report published today by SEMI. Investments in new fab construction are also nearing a record with a fourth consecutive year of growth predicted and capital outlays next year approaching US$17 billion.

Investments for fab technology and product upgrades, as well as for additional capacity, will grow as the emergence of numerous new fabs significantly increases equipment demand, the forecast shows. The World Fab Forecast Report currently tracks 78 new fabs and lines that have or will start construction between 2017 to 2020 (with various probabilities) and will eventually require more US$220 billion in fab equipment (Figure 1). Construction spending for these fabs and lines is expected to reach US$53 billion during this period.

Figure 1: Shows the investment potential of new fabs and lines starting construction between 2017 and 2020.

Korea is projected to lead other regions in fab equipment investments with US$63 billion, US$1 billion more than second-place China. Taiwan is expected to claim the third spot at US$40 billon, followed by Japan at US$22 billion and the Americas at US$15 billion. Europe and Southeast Asia will share sixth place, with investments totaling US$8 billion each. Fully 60 percent of these fabs will serve the Memory sector (the lion’s share will be 3D NAND), and a third will go to Foundry.

Of the 78 fab construction projects starting construction between 2017 and 2020, 59 began construction in the first two years (2017 and 2018), while 19 are expected to begin in the last two years (2019 and 2020) of the tracking period.

Equipping a new fab typically takes one to one and a half years, though some fabs take two years and others longer, depending on various factors as such the company, fab size, product type and region. Approximately half of the projected US$220 billion will be spent from 2017 and 2020, with less than 10 percent invested in 2017 and 2018, nearly 40 percent in 2019 and 2020, and the rest after 2020.

While the US$220 billion estimate is based on current insights of known and announced fab plans, total spending could exceed this level as many companies continue to announce plans for new fabs. Since the last quarterly publication of the report published last quarter, 18 new records – all new fabs – have been added to the forecast. Up-to-date and detailed analysis, with a bottoms-up approach, is available by subscribing to SEMI’s World Fab Forecast Report.

Since its June 1 publication, more than 340 updates have been made to the World Fab Forecast. The report now includes more than 1,200 records of current and future front-end semiconductor facilities from high-volume production to research and development. The report covers data and predictions through 2019, including milestones, detailed investments by quarter, product types, technology nodes and capacities down to fab and project level.

Learn more about the SEMI fab databases at www.semi.org/en/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats.

Adesto® Technologies (NASDAQ: IOTS), a provider of innovative application-specific semiconductors and systems for the IoT era, announced the successful completion of its previously announced acquisition of Echelon Corporation (NASDAQ: ELON). Echelon® is a developer of open-standard networking platforms for connecting, monitoring and controlling devices in commercial and industrial applications.

The definitive agreement was initially announced on June 29, 2018, and Echelon shareholders approved the transaction at a Special Meeting of Shareholders held on September 13, 2018. The transaction closed and became effective today, with each share of Echelon being converted into the right to receive $8.50 in cash, without interest. The cash transaction represents a total equity value of approximately $45 million, and a total enterprise value of about $30 million. Echelon’s trailing 12-month revenue as of the second quarter ended June 30, 2018 was approximately $31.6 million. As a result of the transaction’s close, the common stock of Echelon will no longer be listed for trading on the NASDAQ stock exchange, effective immediately.

Adesto expects to realize cost synergies of approximately $6 million to $8 million in the first 12 months, with more than half to be realized in the fourth quarter of 2018. The Company also expects the acquisition to be accretive to EBITDA and non-GAAP EPS within the first 12 months.

“This acquisition marks a pivotal step for Adesto as we continue to expand our innovative solutions to help customers unlock the true potential of the IoT,” said Narbeh Derhacobian, CEO of Adesto. “We now provide not only semiconductors, but also open-standard networking platforms and tools for connecting, monitoring and controlling devices in commercial and industrial IoT deployments. We have significantly expanded our served available market, while also increasing our revenue and potential for margin expansion. Together with our differentiated non-volatile memory products and our mixed-signal and RF ASICs and IP, we’re able to deliver the essential building blocks that allow seamless access to data, and control of things, in an increasingly connected world.”

The Echelon group will now become Adesto’s Embedded Systems Division, led by Chris Jodoin, former SVP of operations and planning at Echelon.

According to Jodoin, “As part of Adesto, we will continue to support, promote and expand on Echelon’s 30-year heritage, which has become synonymous with intelligent Industrial IoT products and solutions. Our increased scale will enable us to embark on new product initiatives and provide enhanced customer support and access. We look forward to building on our base of an estimated 140 million installed LON-powered devices, and to enabling our customers to achieve success across their applications in smart buildings, smart manufacturing and other industrial segments.”

Over the last several years, Echelon has made significant progress with its Lighting Solutions business. Adesto is currently exploring several strategic alternatives for this product line in order to better align the core Echelon business with Adesto’s long-term focus.

Adesto will provide updates on the Echelon integration as part of its upcoming earnings conference call to be held in early November. Details regarding the date and time of the conference call will be provided at a later date.

By Walt Custer

Global economy

Manufacturing activity continues to expand – but at a slowing pace (Chart 1). The Global PMI was 52.5 in August, down from 52.8 in July and its recent high of 54.5 in December. PMI values >50 indicate an expansion.

World manufacturing growth has slowed but its growth rate varies significantly by region. Chart 2 compares the PMI values over time for the World, USA, Europe and China. Recently China and Europe have registered slower growth but U.S. growth is expanding (based on the Institute for Supply Management’s PMI). How long U.S. manufacturing will continue to accelerate remains to be seen. Geopolitical issues abound.

Semiconductor industry

In the semiconductor industry both semiconductors and SEMI capital equipment continued to register double-digit growth in July (Chart 3), but these growth rates are now moderating. In July, World semiconductor shipments were up 17.4 percent and SEMI capital equipment sales rose 13.9 percent on a 3-month growth basis.

However, SEMI equipment growth rates also vary widely by region. Per Chart 4, China growth is accelerating, Taiwan and South Korea are contracting, and Europe and the USA are still expanding but at slower rates.

Timely World and regional industry information is key to understanding present and future business conditions and this data requires careful watching in these fast-changing times.

Walt Custer of Custer Consulting Group is an analyst focused on the global electronics industry.

Originally published on the SEMI blog.

The market for microcontrollers—the IC industry’s original system-on-chip (SoC) product category—is expected to continue hitting record-high annual revenues through 2022 after worldwide sales dropped 6% in 2016 because of a slowdown in MCU unit shipments. After drawing down MCU inventories in 2016, systems manufacturers stepped up purchases of microcontrollers in 2017 with unit shipments surging 22% and strong growth continuing in 2018.  In its Mid-Year Update to The 2018 McClean Report, IC insights raised its projection for MCU shipments to 18% in 2018 with the unit volume reaching nearly 30.6 billion. MCU revenues are now forecast to rise 11% in 2018 to an all-time high of $18.6 billion, followed by 9% growth in 2019 to about $20.4 billion (Figure 1).

Figure 1

The Mid-Year Update also raised the five-year growth projection of MCU sales to a CAGR of 7.2%, reaching nearly $23.9 billion in 2022, with unit shipments increasing by a compound annual growth rate of 11.1% to about 43.8 billion in the final forecast year.

The ASP for microcontrollers fell to the lowest point ever in 2017 and prices are continuing to drop at about the same rate in 2018. However, the annual rate of decline has eased in the last five years compared to earlier this decade.  IC Insights’ new forecast for MCU ASP shows the average selling price falling by a CAGR of -3.5% in the 2017-2022 period, much slower than the -5.8% decline seen during the 2012-2017 period and the 20-year CAGR of -6.3% between 1997 and 2017.

A key factor in the 2017 recovery of MCU sales from the decline in 2016 was a turnaround in the smartcard microcontroller segment. About 40% of total MCU shipments are currently for smartcard applications, but that is down from about half early in this decade. Excluding smartcard MCUs, sales of “general” microcontrollers for embedded systems, automated control, sensing applications, and IoT-connected things are forecast to grow 11% in 2018 to $16.4 billion after rising 14% in 2017.  Shipments of general MCUs are projected to climb 25% in 2018 to 18.9 billion units after rising 21% in 2017.   General microcontrollers now represent a little over 60% of MCU unit shipments and are forecast to reach 68% of the total in 2022.  Currently, general MCUs generate about 88% of total microcontroller revenues, and they are expected to reach 90% of the entire market value in 2022.

Across nearly all MCU applications, strong growth in 32-bit microcontrollers has reshaped the market as suppliers aggressively promote more powerful designs that are cost competitive with 8-bit and 16-bit devices, which have typically been used in consumer products and other high-volume systems.  In some cases new 32-bit MCUs are being priced below the cost of 8-bit microcontrollers.  On average, 32-bit MCUs were selling for about twice the amount of the ASP for all microcontrollers in 2012 ($1.76 for 32-bit versus $0.88 for total MCUs).  In 2018, the ASP for 32-bit MCUs is expected to be just $0.09 higher than the ASP for all MCUs, and by 2022, the difference is forecast to shrink to $0.05 ($0.60 for 32-bit versus an average of $0.55 for total MCUs).

SUNY Polytechnic Institute (SUNY Poly) announced today that Professor of Nanobioscience Dr. Nate Cady has been awarded $500,000 in funding from the National Science Foundation to develop advanced computing systems based on a novel approach to the creation of non-volatile memory architecture. This research, which will also support student opportunities, aims to advance today’s typical computing model, in which processing and memory are separate, by bringing them together to make the entire process faster and more energy efficient.

“I am proud to congratulate Professor Cady on this National Science Foundation (NSF) award which is focused on enabling advanced computing capabilities, and notably, has important implications for advances in artificial intelligence,” said SUNY Poly Interim President Dr. Grace Wang. “The NSF’s selection of Dr. Cady’s research for this funding exemplifies the quality and impact of SUNY Poly’s research where our faculty and students leverage our world-class high-tech resources, explore new frontiers, and develop critical technologies for our society.”

The research will enable the design of a scalable computing infrastructure that uses nanoscale non-volatile memory (NVM) devices for both storage and computation. One of the current limits to computing speed is the result of current personal computing architecture, which separates the processor and memory and leads to a cap on data throughput, known as the “von Neumann bottleneck.” By combining storage and computation on the same device, the project circumvents this barrier and creates scalable solutions for extreme-scale computing—computing that is up to one thousand times more capable than current comparable computing—based on wires that cross each other to form memory cells at every intersection. This more powerful capability is made possible because each memory cell, acting like a synapse of the human brain, can be switched on or off, similar to the 1’s and 0’s of current computing, but it can also store many other values between the on or off states, increasing the amount of information that a given memory cell can store exponentially.

“This grant showcases the incredible potential of our faculty to tackle real-world problems with high-tech solutions that stem from the SUNY Poly’s advanced labs, cleanrooms, and capabilities. This news is especially exciting for a number of our graduate students who will be able to focus on this promising research area where they will be at the cutting-edge,” said SUNY Poly Interim Provost Dr. Steven Schneider.

“Dr. Cady’s research is a powerful example of the kind of expertise that SUNY Poly’s faculty possess as our innovation-centered ecosystem provides us with unique opportunities to move the technologies of the future forward,” said SUNY Poly Interim Dean of the College of Nanoscale Sciences; Empire Innovation Professor of Nanoscale Science; and Executive Director, Center for Nanoscale Metrology Dr. Alain Diebold.

“I look forward to advancing this non-volatile memory research at SUNY Poly, using the institution’s cutting-edge fabrication facilities in order to address current computing bottlenecks that slow computing capability and waste energy,” said Dr. Cady. “This grant will drive the development of computing and memory infrastructure that will be evaluated using high-performance simulations and experimental benchmarking within our state-of-the-art laboratory at SUNY Poly where we are eager to develop the architecture that can help revolutionize processing and memory capabilities for next-gen computers.”

Dr. Cady’s research will support SUNY Poly graduate students who will be able to obtain hands-on experience developing the computing/memory structures. The materials for this project will be developed, demonstrated, and then integrated with traditional complementary metal-oxide-semiconductor (CMOS) computer chips as part of a larger production, which will utilize SUNY Poly’s 200mm and 300mm state-of-the-art fabrication facilities. The University of Central Florida is receiving its own funds for collaborative research related to this effort.

Computing using multiple parallel flows of current through data stored in nanoscale “crossbars” is often fast and more energy-efficient, but the design of such crossbars is highly unintuitive for human designers. More specifically, this project explores formal methods for more efficiently conducting Boolean searches and using artificial intelligence techniques such as best-first search, in addition to automatically synthesizing non-volatile memory crossbar designs from specifications written in a high-level programming language.

Japan is at the heart of the semiconductor industry as the era of artificial intelligence (AI) dawns. SEMICON Japan 2018 will highlight AI and SMART technologies in Japan’s industry-leading event. Registration is now open for SEMICON Japan, Japan’s largest global electronics supply chain event, December 12-14 at Tokyo Big Sight in Tokyo.

Themed “Dreams Start Here,” SEMICON Japan 2018 reflects the promise of AI, Internet of Things (IoT) and other SMART technologies that are shaping the future. Japan is positioned to help power a semiconductor industry expansion that is enabling this new path ahead, supplying one-third of the world’s semiconductor equipment and half of its chip IC materials.

According to VLSI Research, seven of the world’s top 15 semiconductor equipment manufacturers in 2017 are headquartered in Japan. In the semiconductor materials market, Japanese companies dominate silicon wafers, photoresists, sputtering targets, bonding wires, lead frames, mold compounds and more. For SEMICON Japan visitors, the event is the ideal platform for connecting with Japan’s leading suppliers.

The SMART Application Zone at SEMICON Japan will once again connect SMART industries with the semiconductor supply chain to foster collaboration across the electronics ecosystem.

SEMICON Japan Keynotes

SEMICON Japan opening keynotes will feature two young leaders of Japan’s information and communications technology (ICT) industry sharing their vision for the industry:

Motoi Ishibashi, CTO of Rhizomatiks, will discuss the latest virtual and mixed reality technologies. Rhizomatiks, a Japanese media art company that staged the Rio Olympic Games closing ceremony, will orchestrate the opening performance at SEMICON Japan 2018. The company is dedicated to creating large-scale commercial projects combining technology with the arts.

Toru Nishikawa, president and CEO at Preferred Networks, will explore computer requirements for enabling deep learning applications. Preferred Networks, a deep-learning research startup, is conducting collaborative research with technology giants including Toyota Motors, Fanuc, NVIDIA, Intel and Microsoft.

Registration

For more information and to register for SEMICON Japan, visit www.semiconjapan.org/en/. Registration for the opening keynotes and other programs will open October 1.