Category Archives: Device Architecture

ON Semiconductor is collaborating with Optimal Plus to gather, analyze and build actionable insights out of the company’s manufacturing data. As a supplier to the automotive industry, ON Semiconductor is pioneering innovative technologies that enable all aspects of automated driving and vehicle electrification. The company is also committed to developing the semiconductor technology capable of supporting the rigors of IoT and empowering businesses to capitalize on their investments to drive profitability and ultimately success.

Following an initial pilot project that demonstrated new levels of control and visibility into the company’s manufacturing operations, ON Semiconductor and Optimal Plus will further leverage their solutions to connect the ON Semiconductor global manufacturing footprint as demand continues to grow for the company’s complementary metal oxide semiconductor (CMOS) and charge-coupled device (CCD) image sensors and other technologies that are powering disruptive applications in strategic growth markets.

“Demand for power products for automotive applications continues to grow. With an expansive portfolio for power and automotive applications, we continue to see strong growth in our power related revenue for automotive applications,” said Mark Goranson, ON Semiconductor senior vice president manufacturing. “With a broad range of power products for a complete spectrum of voltages starting from low voltage to high voltage, we also have one of the most comprehensive portfolios of power devices and modules. Partnering with Optimal Plus is a key element to enable the shift from detect to predict and eventually prevent.”

“The Intelligent Sensing Group within ON Semiconductor is innovating vision beyond the human eye and holds imaging and technology leadership in automotive, space, industrial and medical mission-critical market segments,” said Mitch Mooney, general manager of ON Semiconductor Nampa, Idaho operations. “Optimal Plus provides advanced analytics with real-time visibility of our test operations through their leading-edge software that enables big data analysis of all our test parameters. We expect significant benefits in capital efficiency, yield enhancements and quality improvements.”

ON Semiconductor is deploying Optimal Plus solutions to provide increased visibility into their manufacturing processes, from e-test to wafer sort, and final test including communication between geographically-dispersed semiconductor teams. The solution includes deep, multi-stage product analytics for near real-time response capabilities. A core element of the deployment will be enabling ON Semiconductor to lower their Defective Parts Per Million (DPPM) rates to the single digit range.

“The Optimal Plus platform was designed to deliver the actionable insights that ON Semiconductor requires to intelligently adapt operations to increase product yield, quality and productivity,” said Dan Glotter, Optimal Plus Founder and CEO. “Together, ON Semiconductor and Optimal Plus are demonstrating how operations optimization is keeping manufacturers ahead of an increased adoption of Industrial IoT, electric vehicles, machine vision and other disruptive applications in automotive and industrial end markets.”

IC Insights forecasts total semiconductor capital expenditures will rise to $102.0 billion this year, marking the first time that the industry has spent more than $100 billion on capital expenditures in one year.  The $102.0 billion spending level represents a 9% increase over $93.3 billion spent in 2017, which was a 38% surge over 2016.

Figure 1 shows that more than half of industry capital spending is forecast for memory production—primarily DRAM and flash memory—including upgrades to existing wafer fab lines and brand new manufacturing facilities. Collectively, memory is forecast to account for 53% of semiconductor capital expenditures this year. The share of capital spending for memory devices has increase substantially in six years, nearly doubling from 27% ($14.7 billion) in 2013 to a forecast of 53% ($54.0 billion) of total industry capex in 2018, which amounts to a 2013-2018 CAGR of 30%.

Figure 1

Of the major product categories shown, DRAM/SRAM is forecast to show the largest increase in spending, but flash memory is expected to account for the largest share of capex spending this year (Figure 2).  Capital spending for the DRAM/SRAM segment is forecast to show a 41% surge in 2018 after a strong 82% increase in 2017.  Capital spending for flash memory is forecast to rise 13% in 2018 after a 91% increase in 2017.

Figure 2

After two years of big increases in capital expenditures, a major question looming is whether high levels of spending will lead to overcapacity and a softening of prices.  Historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness.  With Samsung, SK Hynix, Micron, Intel, Toshiba/Western Digital/SanDisk, and XMC/Yangtze River Storage Technology all planning to significantly ramp up 3D NAND flash capacity over the next couple of years (and new Chinese memory startup companies entering the market), IC Insights believes that the future risk for overshooting 3D NAND flash market demand is high and growing.

Roger Carpenter, a Google hardware engineer with 30 years of experience in electronic design automation and chip design, has been elected to the Silicon Integration Initiative board of directors. Si2 is a research and development joint venture that provides standard interoperability solutions for integrated circuit design tools.

Before joining Google, Carpenter held executive roles at three EDA firms: Magma Design Automation, Javelin Design Automation and Envis. His design experience includes positions at Wave Computing, Broadcom, Chromatic Research and Xilinx. A holder of more than a dozen patents, Carpenter received a Bachelor’s and Master’s of Electrical Engineering and Computer Science from the Massachusetts Institute of Technology.

John Ellis, Si2 president and CEO, said that Google’s membership on the Si2 board reflects the increasing impact of vertical integration in the electronics industry.  “A recent Si2 industry survey showed that over 80 percent of our end users develop some specialized, internal design tools. This proprietary software meets their unique needs and performance requirements,” Ellis said.

“Directly accessing the Si2 OpenAccess data base by making use of our Application Programming Interface, designers and integrators have greater control over their bottom line by optimizing their design flow and, in turn, shortening product time-to-market. It’s critical that system houses like Google, along with their unique semiconductor design software needs, are now represented on the Si2 board.”

The twelve members of the Si2 board represent leading semiconductor manufacturers and foundries, fabless companies, and EDA software providers.

Micron Technology, Inc., (NASDAQ:MU) today announced plans to invest $3 billion by 2030 to increase memory production at its plant in Manassas, Virginia, creating 1,100 new jobs roughly over the next decade. These investments are contemplated in Micron’s long-term model to invest capital expenditure in the low thirties as a percent of revenue. The expansion will position the Manassas site — located about 40 miles west of Washington, D.C. — to support Micron’s leadership in the rapidly growing market for high quality, high reliability memory products.

Source: Micron

“Micron’s Manassas site manufactures our long-lifecycle products that are built using our mature process technologies, and primarily sold into the automotive, networking and industrial markets,” said Micron President and CEO Sanjay Mehrotra. “These products support a diverse set of applications such as industrial automation, drones, the IoT (Internet of Things) and in-vehicle experience applications for automotive. This business delivers strong profitability and stable, growing free cash flow. Micron is grateful for the extensive engagement of state and local officials since early this year to help bring our Manassas expansion to fruition. We are excited to increase our commitment to the community through the creation of new highly skilled jobs, expanded facilities and education initiatives.”

“Micron’s expansion in the City of Manassas represents one of the largest manufacturing investments in the history of Virginia and will position the Commonwealth as a leader in unmanned systems and Internet of Things,” said Governor Northam. “This $3 billion investment will have a tremendous impact on our economy by creating 1,100 high-demand jobs, and solidifies Micron as one of the Commonwealth’s largest exporters. We thank Micron for choosing to deepen their roots in Virginia and look forward to partnering in their next chapter of major growth.”

The initial clean room expansion is expected to be completed in the fall of 2019 with production ramp in the first half of 2020. This expansion will add less than 5% to Micron’s global clean room space footprint and will primarily support enablement of DRAM and NAND technology transitions as well as modest capacity increase at the site, in-line with growing customer demand for Micron’s long-lifecycle products.

“As a leading global supplier of automotive electronics systems and components, ZF appreciates the long-standing support of Micron to our business,” said Karsten Mueller, vice president, Corporate Materials Management, Global Commodity Electronics at ZF Friedrichshafen AG. “Meeting the ever-increasing demands for automotive applications will require significantly greater memory as the dual trends of advanced safety and autonomy drive the industry forward. Micron’s decision to expand the manufacturing and R&D capabilities at this IATF-certified facility is another indication that this growth should only accelerate in the future.”

As part of this expansion, Micron will also establish a global research development center in Manassas for the development of memory and storage solutions focused mainly on the automotive, industrial and networking markets. The research and development center will include laboratories, test equipment and a staff of approximately 100 engineers.

The Virginia Economic Development Partnership (VEDP) worked with the City of Manassas and the General Assembly’s Major Employment and Investment (MEI) Project Approval Commission to secure the project for Virginia. Micron will be eligible to receive an MEI custom performance grant of $70 million for site preparation and facility costs, subject to approval by the Virginia General Assembly. Additionally, the City of Manassas and utility partners are providing a broader, comprehensive support package to enable the expansion, including substantial infrastructure upgrades and additional incentives.

GLOBALFOUNDRIES today announced an important step in its transformation, continuing the trajectory launched with the appointment of Tom Caulfield as CEO earlier this year. In line with the strategic direction Caulfield has articulated, GF is reshaping its technology portfolio to intensify its focus on delivering truly differentiated offerings for clients in high-growth markets.

GF is realigning its leading-edge FinFET roadmap to serve the next wave of clients that will adopt the technology in the coming years. The company will shift development resources to make its 14/12nm FinFET platform more relevant to these clients, delivering a range of innovative IP and features including RF, embedded memory, low power and more. To support this transition, GF is putting its 7nm FinFET program on hold indefinitely and restructuring its research and development teams to support its enhanced portfolio initiatives. This will require a workforce reduction, however a significant number of top technologists will be redeployed on 14/12nm FinFET derivatives and other differentiated offerings.

“Demand for semiconductors has never been higher, and clients are asking us to play an ever-increasing role in enabling tomorrow’s technology innovations,” Caulfield said. “The vast majority of today’s fabless customers are looking to get more value out of each technology generation to leverage the substantial investments required to design into each technology node. Essentially, these nodes are transitioning to design platforms serving multiple waves of applications, giving each node greater longevity. This industry dynamic has resulted in fewer fabless clients designing into the outer limits of Moore’s Law. We are shifting our resources and focus by doubling down on our investments in differentiated technologies across our entire portfolio that are most relevant to our clients in growing market segments.”

In addition, to better leverage GF’s strong heritage and significant investments in ASIC design and IP, the company is establishing its ASIC business as a wholly-owned subsidiary, independent from the foundry business. A relevant ASIC business requires continued access to leading-edge technology. This independent ASIC entity will provide clients with access to alternative foundry options at 7nm and beyond, while allowing the ASIC business to engage with a broader set of clients, especially the growing number of systems companies that need ASIC capabilities and more manufacturing scale than GF can provide alone.

GF is intensifying investment in areas where it has clear differentiation and adds true value for clients, with an emphasis on delivering feature-rich offerings across its portfolio. This includes continued focus on its FDXTM platform, leading RF offerings (including RF SOI and high-performance SiGe), analog/mixed signal, and other technologies designed for a growing number of applications that require low power, real-time connectivity, and on-board intelligence. GF is uniquely positioned to serve this burgeoning market for “connected intelligence,” with strong demand in new areas such as autonomous driving, IoT and the global transition to 5G.

“Lifting the burden of investing at the leading edge will allow GF to make more targeted investments in technologies that really matter to the majority of chip designers in fast-growing markets such as RF, IoT, 5G, industrial and automotive,” said Samuel Wang, research vice president at Gartner. “While the leading edge gets most of the headlines, fewer customers can afford the transition to 7nm and finer geometries.  14nm and above technologies will continue to be the important demand driver for the foundry business for many years to come. There is significant room for innovation on these nodes to fuel the next wave of technology.”

Lattice Semiconductor Corporation (NASDAQ: LSCC), a provider of customizable smart connectivity solutions, announced the appointment of Jim Anderson as the Company’s President and Chief Executive Officer, and to the Company’s Board of Directors, effective September 4, 2018. Mr. Anderson brings broad technology industry experience and a proven track record of leading and transforming businesses to drive sustained growth and profitability. Mr. Anderson joins Lattice from Advanced Micro Devices (AMD) where he served as the General Manager and Senior Vice President of the Computing and Graphics Business Group.

Jeff Richardson, Chairman of the Board, said, “On behalf of the Board, we are pleased to announce the appointment of Jim Anderson as Lattice’s new President and Chief Executive Officer. Jim brings a strong combination of business and technical leadership with a deep understanding of our target end markets and customers. The transformation he drove of AMD’s Computing and Graphics business over the past few years is just a recent example of his long track record of creating significant shareholder value. We are excited to bring Jim’s proven leadership to Lattice as we accelerate all aspects of the company in order to capture the enormous opportunity that lies ahead.” Mr. Richardson added, “The Board would also like to thank Glen Hawk for his leadership and service to Lattice as COO and then as Interim CEO during the Company’s management transition.” Glen has agreed to serve as Special Advisor to the CEO through October 31, 2018, to help ensure a smooth transition before leaving Lattice to pursue other opportunities.

Mr. Anderson said, “I want to thank the Board of Directors for its confidence and the opportunity to lead Lattice as President and CEO, with a focus on driving sustained growth and profitability. Lattice has an impressive history of innovation in programmable solutions. I am excited about the opportunity to help bring that innovation to growing end markets, while deepening partnerships with our customers. Lattice has a compelling combination of ground-breaking hardware and software solutions, global reach, and talented employees that forms a strong foundation for industry leadership and success.”

Jim Anderson brings to the role over 20 years of broad technology industry experience across many markets, including consumer, enterprise/datacenter, and telecom. In his role leading AMD’s Computing and Graphics business group since 2015, Mr. Anderson drove a strategic and operational transformation that brought disruptive new products to the market and delivered market-leading revenue growth and significant profitability expansion for AMD. Prior to AMD, he held a broad range of leadership positions spanning general management, engineering, sales, marketing, and strategy at companies including, Intel, Broadcom Limited (formerly, Avago Technologies), and LSI Corporation.

Mr. Anderson holds an MBA and Master of Science in electrical engineering and computer science from the Massachusetts Institute of Technology, a Master of Science in electrical engineering from Purdue University, and a Bachelor of Science in electrical engineering from the University of Minnesota. Mr. Anderson has received four patents for innovations in computer architecture. He also serves on the Board of Directors of Qylur Intelligent Systems, Inc.

By Jay Chittooran

In testimony last week before a U.S. government interagency panel considering tariffs on $200 billion worth of Chinese goods, SEMI called for the removal of nearly 100 tariff lines, all of which cover items critical to the semiconductor manufacturing process, including materials and machines.

Jonathan Davis, global vice president of advocacy at SEMI, explained in his testimony that while SEMI strongly supports efforts to better protect valuable intellectual property (IP), tariffs will not help address Chinese trade practices, and will ultimately have significant and unintended consequences. SEMI asserts that these tariffs will harm companies in the semiconductor supply chain by increasing business costs, introducing uncertainty, and stifling innovation. Collectively, SEMI estimates that this round of tariffs will cost its 400 U.S. members more than tens of millions annually in additional duties. All told, SEMI estimates that all U.S. and Chinese retaliatory tariffs will cost members nearly $700 million in annual duties.

SEMI’s full written comments note that these tariffs, on top of those already in force and the retaliatory tariffs, will hamstring the industry. The tariffs seem to target U.S. firms for simply operating in China. Given that tools and materials are extremely complex, precise, and difficult to manufacture, it is unreasonable to believe that a constituent component can simply be replaced with a part from another source. Further, this U.S. government approach does not take into account that many items  subject to these tariffs are not available, at sufficient quality and cost, from domestic sources, or even non-Chinese sources. We stand steadfast in our belief that this trade action will raise prices, put thousands of high-paying and high skill jobs at risk, and curb growth.

Over the past four months, SEMI submitted written comments and offered testimony on the two previous rounds of tariffs, citing the damaging impact tariffs would have on the U.S. semiconductor industry. The first round of tariffs – on $34 billion worth of Chinese goods – took effect July 6, and the second round – targeting $16 billion in Chinese imports – will be imposed on August 23. The tariffs hit machines and tools central to the semiconductor industry, including equipment used to manufacture wafers, boules, and chips as well as test, inspection and sensing equipment.

We urge SEMI members to review the $200 billion U.S. tariff list to determine the level, if any, of impact. We also strongly encourage members to review Chinese retaliatory lists as well. Any SEMI members who have questions, should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Originally published on the SEMI blog.

GOWIN Semiconductor Corp., an innovator of programmable logic devices, announces their development of RISC-V Microprocessor IP implemented in their current ARORA® Family GW-2A FPGA products.  In addition, GOWIN launches an Industry Early Adopter Program to kickstart engineering design activity.  The Industry EAP includes: an FPGA programming bit-file reference design with RISC-V Microprocessor core, AHB & APB Bus, Memory Control & Peripherals, as well as the GW-2A development board for a complete, ready to use solution.

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. The RISC-V ISA has been designed with small, fast, and low-power real-world implementations in mind without over-architecting for a particular microarchitecture style. The instruction set also has a substantial body of supporting software for a comprehensive design ecosystem.

“GOWIN’s FPGA solutions showcase the growing adoption of RISC-V around the world. It’s exciting to see how the RISC-V ecosystem is maturing as more companies design innovative implementations based on the free and open ISA,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation.

The GOWIN Arora® Family GW-2A FPGAs offer best-in-class performance at an effective cost. With abundant logic, high performance DSP resources, and high speed I/O, the family is optimized for co-processing of computation tasks while hosting the RISC-V Microprocessor soft core. The Arora® family is also the first FPGA with embedded DRAM in the industry, allowing customers to design without using up I/O for external memory.

GOWIN also announces today the appointment of Edge Electronics as their US National Distributor and EBBM, Inc as their East Coast Manufacturers Representative.  “Demand is high for our innovative FPGA products serving the low to mid density logic element markets,” said Scott Casper, Director of Sales for GOWIN’s Americas Region, “The need for the right channel partners is necessary for our growth.  We are excited to be working with Edge and EBBM as we continue our Americas expansion plan.”

“GOWIN Semiconductor is a natural fit alongside our semiconductor and LCD solutions product offerings, both of which are geared toward serving North American industrial, medical and automotive OEM markets among others,” says Michael Pollina, Edge Electronics’ VP Operations & Procurement. “GOWIN’s collection of development tools in tandem with Edge’s engineering team will make it simple for customers to transition existing designs or start new projects with low power, space-efficient and cost-effective FPGA solutions.”

“We are thrilled to be working with GOWIN, one of the Silicon60 Most Remarkable Global Technology Startups,” said Chief Executive Officer of EBBM, Inc., Alex Angelou. “EBBM, Inc has been helping custom logic architects quickly articulate their design and beat their competition to market for 14 years. GOWIN’s One-Stop Complete Solution, including DVK, EDA, IP, is a perfect match to bring the competitive advantage to more companies,” said EBBM, Inc. Chief Strategy Officer Ken Cheo.

TowerJazz, the global specialty foundry, today announced its participation at European Microwave Week (EuMW), being held in Madrid, Spain on September 25 – 27, 2018. The Company will showcase its extensive RF silicon process capability including its advanced SiGe and RF SOI technologies, addressing the emerging 5G and mmWave markets and focusing on high-data rate mobile and automotive applications.

TowerJazz will present its best-in-class, high volume SiGe BiCMOS technology for 5G mobile transmit-receive chips with greater than 12 Gbps data rates, with record performance at the 28GHz band, representing a more than 10-times improvement in data rate vs. 4G LTE, and meeting many other technical specification requirements of the emerging 5G standard. The Company will also highlight its 5G RF SOI technology which includes its newest 65nm process ramping on 300mm wafers with best-in-class LNA and switch performance to address integration in the front-end-module. The process can reduce losses in an RF switch improving battery life and boosting data rates in handsets and IoT terminals.

During the conference, TowerJazz will participate on a panel to discuss RF semiconductor solutions for 5G systems. The panel session is scheduled for September 25, 2018 from 11:00 a.m. until noon.

Semiconducting heterostructures have been key to the development of electronics and opto-electronics. Many applications in the infrared and terahertz frequency range exploit transitions, called intersubband transitions, between quantized states in semiconductor quantum wells. These intraband transitions exhibit very large oscillator strengths, close to unity. Their discovery in III-V semiconductor heterostructures depicted a huge impact within the condensed matter physics community and triggered the development of quantum well infrared photodetectors as well as quantum cascade lasers.

Schematic illustration of charge carriers confined within a TMD flake comprising different thicknesses. Charge carriers in the ground state (blue) can be excited upon resonant light excitation to a higher state (pink). Credit: ICFO/Fabien Vialla

Quantum wells of the highest quality are typically fabricated by molecular beam epitaxy (sequential growth of crystalline layers), which is a well-established technique. However, it poses two major limitations: Lattice-matching is required, restricting the freedom in materials to choose from, and the thermal growth causes atomic diffusion and increases interface roughness.

2D materials can overcome these limitations since they naturally form a quantum well with atomically sharp interfaces. They provide defect free and atomically sharp interfaces, enabling the formation of ideal QWs, free of diffusive inhomogeneities. They do not require epitaxial growth on a matching substrate and can therefore be easily isolated and coupled to other electronic systems such as Si CMOS or optical systems such as cavities and waveguides.

Surprisingly enough, intersubband transitions in few-layer 2D materials had never been studied before, neither experimentally nor theoretically. Thus, in a recent study published in Nature Nanotechnology, ICFO researchers Peter Schmidt, Fabien Vialla, Mathieu Massicotte, Klaas-Jan Tielrooij, Gabriele Navickaite, led by ICREA Prof at ICFO Frank Koppens, in collaboration with the Institut Lumière Matière – CNRS, Technical University of Denmark, Max Planck Institute for the Structure and Dynamics of Matter, CIC nanoGUNE, and the National Graphene Institute, report on the first theoretical calculations and first experimental observation of inter-sub-band transitions in quantum wells of few-layer semiconducting 2D materials (TMDs).

In their experiment, the team of researchers applied scattering scanning near-field optical microscopy (s-SNOM) as an innovative approach for spectral absorption measurements with a spatial resolution below 20 nm. They exfoliated TMDs, which comprisedterraces of different layer thicknesses over lateral sizes of about a few micrometers. They directly observed the intersubband resonances for these different quantum well thicknesses within a single device. They also electrostatically tuned the charge carrier density and demonstrated intersubband absorption in both the valence and conduction band. These observations were complemented and supported with detailed theoretical calculations revealing many-body and non-local effects.

The results of this study pave the way towards an unexplored field in this new class of materials and offer a first glimpse of the physics and technology enabled by intersubband transitions in 2D materials, such as infrared detectors, sources, and lasers with the potential for compact integration with Si CMOS.